1 /* $NetBSD: intr.h,v 1.5 2011/05/02 00:17:35 matt Exp $ */ 2 /*- 3 * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas <matt@3am-software.com>. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef _MIPS_INTR_H_ 32 #define _MIPS_INTR_H_ 33 34 #ifdef _KERNEL_OPT 35 #include "opt_multiprocessor.h" 36 #endif 37 38 /* 39 * This is a common <machine/intr.h> for all MIPS platforms. 40 */ 41 42 #define IPL_NONE 0 43 #define IPL_SOFTCLOCK (IPL_NONE+1) 44 #define IPL_SOFTBIO (IPL_SOFTCLOCK) /* shares SWINT with softclock */ 45 #define IPL_SOFTNET (IPL_SOFTBIO+1) 46 #define IPL_SOFTSERIAL (IPL_SOFTNET) /* shares SWINT with softnet */ 47 #define IPL_VM (IPL_SOFTSERIAL+1) 48 #define IPL_SCHED (IPL_VM+1) 49 #define IPL_DDB (IPL_SCHED+1) 50 #define IPL_HIGH (IPL_DDB+1) 51 52 #define _IPL_N (IPL_HIGH+1) 53 #define _IPL_NAMES(pfx) { pfx"none", pfx"softclock/bio", pfx"softnet/serial", \ 54 pfx"vm", pfx"sched", pfx"ddb", pfx"high" } 55 56 #define IST_UNUSABLE -1 /* interrupt cannot be used */ 57 #define IST_NONE 0 /* none (dummy) */ 58 #define IST_PULSE 1 /* pulsed */ 59 #define IST_EDGE 2 /* edge-triggered */ 60 #define IST_LEVEL 3 /* level-triggered */ 61 #define IST_LEVEL_HIGH 4 /* level triggered, active high */ 62 #define IST_LEVEL_LOW 5 /* level triggered, active low */ 63 64 #define IPI_NOP 0 /* do nothing, interrupt only */ 65 #define IPI_AST 1 /* force ast */ 66 #define IPI_SHOOTDOWN 2 /* do a tlb shootdown */ 67 #define IPI_SYNCICACHE 3 /* sync icache for pages */ 68 #define IPI_KPREEMPT 4 /* schedule a kernel preemption */ 69 #define IPI_SUSPEND 5 /* DDB suspend signaling */ 70 #define IPI_HALT 6 /* halt cpu */ 71 #define IPI_XCALL 7 /* xcall */ 72 #define NIPIS 8 73 74 #ifdef __INTR_PRIVATE 75 struct splsw { 76 int (*splsw_splhigh)(void); 77 int (*splsw_splsched)(void); 78 int (*splsw_splvm)(void); 79 int (*splsw_splsoftserial)(void); 80 int (*splsw_splsoftnet)(void); 81 int (*splsw_splsoftbio)(void); 82 int (*splsw_splsoftclock)(void); 83 int (*splsw_splraise)(int); 84 void (*splsw_spl0)(void); 85 void (*splsw_splx)(int); 86 int (*splsw_splhigh_noprof)(void); 87 void (*splsw_splx_noprof)(int); 88 void (*splsw__setsoftintr)(uint32_t); 89 void (*splsw__clrsoftintr)(uint32_t); 90 int (*splsw_splintr)(uint32_t *); 91 void (*splsw_splcheck)(void); 92 }; 93 94 struct ipl_sr_map { 95 uint32_t sr_bits[_IPL_N]; 96 }; 97 #else 98 struct splsw; 99 #endif /* __INTR_PRIVATE */ 100 101 typedef int ipl_t; 102 typedef struct { 103 ipl_t _spl; 104 } ipl_cookie_t; 105 106 #ifdef _KERNEL 107 108 #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS) 109 #define __HAVE_PREEMPTION 1 110 #define SOFTINT_KPREEMPT (SOFTINT_COUNT+0) 111 #endif 112 113 #ifdef __INTR_PRIVATE 114 extern struct splsw mips_splsw; 115 extern struct ipl_sr_map ipl_sr_map; 116 #endif /* __INTR_PRIVATE */ 117 118 int splhigh(void); 119 int splhigh_noprof(void); 120 int splsched(void); 121 int splvm(void); 122 int splsoftserial(void); 123 int splsoftnet(void); 124 int splsoftbio(void); 125 int splsoftclock(void); 126 int splraise(int); 127 void splx(int); 128 void splx_noprof(int); 129 void spl0(void); 130 int splintr(uint32_t *); 131 void _setsoftintr(uint32_t); 132 void _clrsoftintr(uint32_t); 133 134 struct cpu_info; 135 136 void ipi_init(struct cpu_info *); 137 void ipi_process(struct cpu_info *, uint64_t); 138 139 /* 140 * These make no sense *NOT* to be inlined. 141 */ 142 static inline ipl_cookie_t 143 makeiplcookie(ipl_t s) 144 { 145 return (ipl_cookie_t){._spl = s}; 146 } 147 148 static inline int 149 splraiseipl(ipl_cookie_t icookie) 150 { 151 return splraise(icookie._spl); 152 } 153 154 #endif /* _KERNEL */ 155 #endif /* _MIPS_INTR_H_ */ 156