xref: /netbsd-src/sys/arch/mips/include/intr.h (revision 439a3189a8d54b064f7dd4df7615e0d73d4b17ce)
1*439a3189Ssimonb /* $NetBSD: intr.h,v 1.13 2021/02/16 05:11:26 simonb Exp $ */
2c42ab079Smrg 
3e544d504Smatt /*-
4e544d504Smatt  * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
5e544d504Smatt  * All rights reserved.
6e544d504Smatt  *
7e544d504Smatt  * This code is derived from software contributed to The NetBSD Foundation
8e544d504Smatt  * by Matt Thomas <matt@3am-software.com>.
9e544d504Smatt  *
10e544d504Smatt  * Redistribution and use in source and binary forms, with or without
11e544d504Smatt  * modification, are permitted provided that the following conditions
12e544d504Smatt  * are met:
13e544d504Smatt  * 1. Redistributions of source code must retain the above copyright
14e544d504Smatt  *    notice, this list of conditions and the following disclaimer.
15e544d504Smatt  * 2. Redistributions in binary form must reproduce the above copyright
16e544d504Smatt  *    notice, this list of conditions and the following disclaimer in the
17e544d504Smatt  *    documentation and/or other materials provided with the distribution.
18e544d504Smatt  *
19e544d504Smatt  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20e544d504Smatt  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21e544d504Smatt  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22e544d504Smatt  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23e544d504Smatt  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24e544d504Smatt  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25e544d504Smatt  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26e544d504Smatt  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27e544d504Smatt  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28e544d504Smatt  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29e544d504Smatt  * POSSIBILITY OF SUCH DAMAGE.
30e544d504Smatt  */
31e544d504Smatt 
32e544d504Smatt #ifndef _MIPS_INTR_H_
33e544d504Smatt #define	_MIPS_INTR_H_
34e544d504Smatt 
35e544d504Smatt #ifdef _KERNEL_OPT
36e544d504Smatt #include "opt_multiprocessor.h"
37e544d504Smatt #endif
38e544d504Smatt 
39e544d504Smatt /*
40e544d504Smatt  * This is a common <machine/intr.h> for all MIPS platforms.
41e544d504Smatt  */
42e544d504Smatt 
43e544d504Smatt #define	IPL_NONE	0
44e544d504Smatt #define	IPL_SOFTCLOCK	(IPL_NONE+1)
45e544d504Smatt #define	IPL_SOFTBIO	(IPL_SOFTCLOCK)	/* shares SWINT with softclock */
46e544d504Smatt #define	IPL_SOFTNET	(IPL_SOFTBIO+1)
47e544d504Smatt #define	IPL_SOFTSERIAL	(IPL_SOFTNET)	/* shares SWINT with softnet */
48e544d504Smatt #define	IPL_VM		(IPL_SOFTSERIAL+1)
49e544d504Smatt #define	IPL_SCHED	(IPL_VM+1)
50e544d504Smatt #define	IPL_DDB		(IPL_SCHED+1)
51e544d504Smatt #define	IPL_HIGH	(IPL_DDB+1)
52e544d504Smatt 
5331984c0bSmatt #define	IPL_SAFEPRI	IPL_SOFTSERIAL
5431984c0bSmatt 
55e544d504Smatt #define	_IPL_N		(IPL_HIGH+1)
56e544d504Smatt #define	_IPL_NAMES(pfx)	{ pfx"none", pfx"softclock/bio", pfx"softnet/serial", \
57e544d504Smatt 			  pfx"vm", pfx"sched", pfx"ddb", pfx"high" }
58e544d504Smatt 
59e544d504Smatt #define	IST_UNUSABLE	-1		/* interrupt cannot be used */
60e544d504Smatt #define	IST_NONE	0		/* none (dummy) */
61e544d504Smatt #define	IST_PULSE	1		/* pulsed */
62e544d504Smatt #define	IST_EDGE	2		/* edge-triggered */
63e544d504Smatt #define	IST_LEVEL	3		/* level-triggered */
64e544d504Smatt #define	IST_LEVEL_HIGH	4		/* level triggered, active high */
65e544d504Smatt #define	IST_LEVEL_LOW	5		/* level triggered, active low */
66e544d504Smatt 
672d299731Smatt #define	IST_MPSAFE	0x100		/* interrupt is MPSAFE */
682d299731Smatt 
69e544d504Smatt #define	IPI_NOP		0		/* do nothing, interrupt only */
70e544d504Smatt #define	IPI_AST		1		/* force ast */
71e544d504Smatt #define	IPI_SHOOTDOWN	2		/* do a tlb shootdown */
72e544d504Smatt #define	IPI_SYNCICACHE	3		/* sync icache for pages */
73e544d504Smatt #define	IPI_KPREEMPT	4		/* schedule a kernel preemption */
74e544d504Smatt #define	IPI_SUSPEND	5		/* DDB suspend signaling */
75e544d504Smatt #define	IPI_HALT	6		/* halt cpu */
7685aa5867Smatt #define	IPI_XCALL	7		/* xcall */
778011b285Srmind #define	IPI_GENERIC	8		/* generic IPI */
788d2429aaSmatt #define	IPI_WDOG	9		/* tickle a wdog */
798d2429aaSmatt #define	NIPIS		10
80e544d504Smatt 
81e544d504Smatt #ifdef __INTR_PRIVATE
82e544d504Smatt struct splsw {
83e544d504Smatt 	int	(*splsw_splhigh)(void);
84e544d504Smatt 	int	(*splsw_splsched)(void);
85e544d504Smatt 	int	(*splsw_splvm)(void);
86e544d504Smatt 	int	(*splsw_splsoftserial)(void);
87e544d504Smatt 	int	(*splsw_splsoftnet)(void);
88e544d504Smatt 	int	(*splsw_splsoftbio)(void);
89e544d504Smatt 	int	(*splsw_splsoftclock)(void);
90e544d504Smatt 	int	(*splsw_splraise)(int);
91e544d504Smatt 	void	(*splsw_spl0)(void);
92e544d504Smatt 	void	(*splsw_splx)(int);
93e544d504Smatt 	int	(*splsw_splhigh_noprof)(void);
94e544d504Smatt 	void	(*splsw_splx_noprof)(int);
95e544d504Smatt 	void	(*splsw__setsoftintr)(uint32_t);
96e544d504Smatt 	void	(*splsw__clrsoftintr)(uint32_t);
97e544d504Smatt 	int	(*splsw_splintr)(uint32_t *);
98e544d504Smatt 	void	(*splsw_splcheck)(void);
99e544d504Smatt };
100e544d504Smatt 
101e544d504Smatt struct ipl_sr_map {
102e544d504Smatt 	uint32_t sr_bits[_IPL_N];
103e544d504Smatt };
104e544d504Smatt #else
105e544d504Smatt struct splsw;
106e544d504Smatt #endif /* __INTR_PRIVATE */
107e544d504Smatt 
108e544d504Smatt typedef int ipl_t;
109e544d504Smatt typedef struct {
110e544d504Smatt         ipl_t _spl;
111e544d504Smatt } ipl_cookie_t;
112e544d504Smatt 
113e544d504Smatt #ifdef _KERNEL
114e544d504Smatt 
115f9d40dbbSskrll #if 0
116e544d504Smatt #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
117e544d504Smatt #define	__HAVE_PREEMPTION	1
118e544d504Smatt #define	SOFTINT_KPREEMPT	(SOFTINT_COUNT+0)
119e544d504Smatt #endif
120f9d40dbbSskrll #endif
121e544d504Smatt 
122e544d504Smatt #ifdef __INTR_PRIVATE
123e544d504Smatt extern	struct splsw	mips_splsw;
124e544d504Smatt extern	struct ipl_sr_map ipl_sr_map;
125e544d504Smatt #endif /* __INTR_PRIVATE */
126e544d504Smatt 
127e544d504Smatt int	splhigh(void);
128*439a3189Ssimonb int	__noprofile splhigh_noprof(void);
129e544d504Smatt int	splsched(void);
130e544d504Smatt int	splvm(void);
131e544d504Smatt int	splsoftserial(void);
132e544d504Smatt int	splsoftnet(void);
133e544d504Smatt int	splsoftbio(void);
134e544d504Smatt int	splsoftclock(void);
135e544d504Smatt int	splraise(int);
136e544d504Smatt void	splx(int);
137*439a3189Ssimonb void	__noprofile splx_noprof(int);
138e544d504Smatt void	spl0(void);
139e544d504Smatt int	splintr(uint32_t *);
140e544d504Smatt void	_setsoftintr(uint32_t);
141e544d504Smatt void	_clrsoftintr(uint32_t);
142e544d504Smatt 
143e544d504Smatt struct cpu_info;
144e544d504Smatt 
145e544d504Smatt void	ipi_init(struct cpu_info *);
146e544d504Smatt void	ipi_process(struct cpu_info *, uint64_t);
147e544d504Smatt 
148e544d504Smatt /*
149e544d504Smatt  * These make no sense *NOT* to be inlined.
150e544d504Smatt  */
151e544d504Smatt static inline ipl_cookie_t
makeiplcookie(ipl_t s)152e544d504Smatt makeiplcookie(ipl_t s)
153e544d504Smatt {
154e544d504Smatt 	return (ipl_cookie_t){._spl = s};
155e544d504Smatt }
156e544d504Smatt 
157e544d504Smatt static inline int
splraiseipl(ipl_cookie_t icookie)158e544d504Smatt splraiseipl(ipl_cookie_t icookie)
159e544d504Smatt {
160e544d504Smatt 	return splraise(icookie._spl);
161e544d504Smatt }
162e544d504Smatt 
163e544d504Smatt #endif /* _KERNEL */
164e544d504Smatt #endif /* _MIPS_INTR_H_ */
165