1 /* $NetBSD: cpuregs.h,v 1.4 1994/10/26 21:09:45 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)machConst.h 8.1 (Berkeley) 6/10/93 39 * 40 * machConst.h -- 41 * 42 * Machine dependent constants. 43 * 44 * Copyright (C) 1989 Digital Equipment Corporation. 45 * Permission to use, copy, modify, and distribute this software and 46 * its documentation for any purpose and without fee is hereby granted, 47 * provided that the above copyright notice appears in all copies. 48 * Digital Equipment Corporation makes no representations about the 49 * suitability of this software for any purpose. It is provided "as is" 50 * without express or implied warranty. 51 * 52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h, 53 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL) 54 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h, 55 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL) 56 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h, 57 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL) 58 */ 59 60 #ifndef _MACHCONST 61 #define _MACHCONST 62 63 #define MACH_KUSEG_ADDR 0x0 64 #define MACH_CACHED_MEMORY_ADDR 0x80000000 65 #define MACH_UNCACHED_MEMORY_ADDR 0xa0000000 66 #define MACH_KSEG2_ADDR 0xc0000000 67 #define MACH_MAX_MEM_ADDR 0xbe000000 68 #define MACH_RESERVED_ADDR 0xbfc80000 69 70 #define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 71 #define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR) 72 #define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 73 #define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR) 74 75 #define MACH_CODE_START 0x80030000 76 77 /* 78 * The bits in the cause register. 79 * 80 * MACH_CR_BR_DELAY Exception happened in branch delay slot. 81 * MACH_CR_COP_ERR Coprocessor error. 82 * Interrupt pending bits defined below. 83 * MACH_CR_EXC_CODE The exception type (see exception codes below). 84 */ 85 #define MACH_CR_BR_DELAY 0x80000000 86 #define MACH_CR_COP_ERR 0x30000000 87 #define MACH_CR_EXC_CODE 0x0000003C 88 #define MACH_CR_EXC_CODE_SHIFT 2 89 90 /* 91 * The bits in the status register. All bits are active when set to 1. 92 * 93 * MACH_SR_CO_USABILITY Control the usability of the four coprocessors. 94 * MACH_SR_BOOT_EXC_VEC Use alternate exception vectors. 95 * MACH_SR_TLB_SHUTDOWN TLB disabled. 96 * MACH_SR_PARITY_ERR Parity error. 97 * MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss. 98 * MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits. 99 * MACH_SR_SWAP_CACHES Swap I-cache and D-cache. 100 * MACH_SR_ISOL_CACHES Isolate D-cache from main memory. 101 * Interrupt enable bits defined below. 102 * MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode. 103 * MACH_SR_INT_ENA_OLD Old interrupt enable bit. 104 * MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode. 105 * MACH_SR_INT_ENA_PREV Previous interrupt enable bit. 106 * MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode. 107 * MACH_SR_INT_ENA_CUR Current interrupt enable bit. 108 */ 109 #define MACH_SR_COP_USABILITY 0xf0000000 110 #define MACH_SR_COP_0_BIT 0x10000000 111 #define MACH_SR_COP_1_BIT 0x20000000 112 #define MACH_SR_BOOT_EXC_VEC 0x00400000 113 #define MACH_SR_TLB_SHUTDOWN 0x00200000 114 #define MACH_SR_PARITY_ERR 0x00100000 115 #define MACH_SR_CACHE_MISS 0x00080000 116 #define MACH_SR_PARITY_ZERO 0x00040000 117 #define MACH_SR_SWAP_CACHES 0x00020000 118 #define MACH_SR_ISOL_CACHES 0x00010000 119 #define MACH_SR_KU_OLD 0x00000020 120 #define MACH_SR_INT_ENA_OLD 0x00000010 121 #define MACH_SR_KU_PREV 0x00000008 122 #define MACH_SR_INT_ENA_PREV 0x00000004 123 #define MACH_SR_KU_CUR 0x00000002 124 #define MACH_SR_INT_ENA_CUR 0x00000001 125 #define MACH_SR_MBZ 0x0f8000c0 126 127 /* 128 * The interrupt masks. 129 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 130 */ 131 #define MACH_INT_MASK 0xff00 132 #define MACH_INT_MASK_5 0x8000 133 #define MACH_INT_MASK_4 0x4000 134 #define MACH_INT_MASK_3 0x2000 135 #define MACH_INT_MASK_2 0x1000 136 #define MACH_INT_MASK_1 0x0800 137 #define MACH_INT_MASK_0 0x0400 138 #define MACH_HARD_INT_MASK 0xfc00 139 #define MACH_SOFT_INT_MASK_1 0x0200 140 #define MACH_SOFT_INT_MASK_0 0x0100 141 142 /* 143 * The bits in the context register. 144 */ 145 #define MACH_CNTXT_PTE_BASE 0xFFE00000 146 #define MACH_CNTXT_BAD_VPN 0x001FFFFC 147 148 /* 149 * Location of exception vectors. 150 */ 151 #define MACH_RESET_EXC_VEC 0xBFC00000 152 #define MACH_UTLB_MISS_EXC_VEC 0x80000000 153 #define MACH_GEN_EXC_VEC 0x80000080 154 155 /* 156 * Coprocessor 0 registers: 157 * 158 * MACH_COP_0_TLB_INDEX TLB index. 159 * MACH_COP_0_TLB_RANDOM TLB random. 160 * MACH_COP_0_TLB_LOW TLB entry low. 161 * MACH_COP_0_TLB_CONTEXT TLB context. 162 * MACH_COP_0_BAD_VADDR Bad virtual address. 163 * MACH_COP_0_TLB_HI TLB entry high. 164 * MACH_COP_0_STATUS_REG Status register. 165 * MACH_COP_0_CAUSE_REG Exception cause register. 166 * MACH_COP_0_EXC_PC Exception PC. 167 * MACH_COP_0_PRID Processor revision identifier. 168 */ 169 #define MACH_COP_0_TLB_INDEX $0 170 #define MACH_COP_0_TLB_RANDOM $1 171 #define MACH_COP_0_TLB_LOW $2 172 #define MACH_COP_0_TLB_CONTEXT $4 173 #define MACH_COP_0_BAD_VADDR $8 174 #define MACH_COP_0_TLB_HI $10 175 #define MACH_COP_0_STATUS_REG $12 176 #define MACH_COP_0_CAUSE_REG $13 177 #define MACH_COP_0_EXC_PC $14 178 #define MACH_COP_0_PRID $15 179 180 /* 181 * Values for the code field in a break instruction. 182 */ 183 #define MACH_BREAK_INSTR 0x0000000d 184 #define MACH_BREAK_VAL_MASK 0x03ff0000 185 #define MACH_BREAK_VAL_SHIFT 16 186 #define MACH_BREAK_KDB_VAL 512 187 #define MACH_BREAK_SSTEP_VAL 513 188 #define MACH_BREAK_BRKPT_VAL 514 189 #define MACH_BREAK_KDB (MACH_BREAK_INSTR | \ 190 (MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT)) 191 #define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \ 192 (MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT)) 193 #define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \ 194 (MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT)) 195 196 /* 197 * Mininum and maximum cache sizes. 198 */ 199 #define MACH_MIN_CACHE_SIZE (16 * 1024) 200 #define MACH_MAX_CACHE_SIZE (256 * 1024) 201 202 /* 203 * The floating point version and status registers. 204 */ 205 #define MACH_FPC_ID $0 206 #define MACH_FPC_CSR $31 207 208 /* 209 * The floating point coprocessor status register bits. 210 */ 211 #define MACH_FPC_ROUNDING_BITS 0x00000003 212 #define MACH_FPC_ROUND_RN 0x00000000 213 #define MACH_FPC_ROUND_RZ 0x00000001 214 #define MACH_FPC_ROUND_RP 0x00000002 215 #define MACH_FPC_ROUND_RM 0x00000003 216 #define MACH_FPC_STICKY_BITS 0x0000007c 217 #define MACH_FPC_STICKY_INEXACT 0x00000004 218 #define MACH_FPC_STICKY_UNDERFLOW 0x00000008 219 #define MACH_FPC_STICKY_OVERFLOW 0x00000010 220 #define MACH_FPC_STICKY_DIV0 0x00000020 221 #define MACH_FPC_STICKY_INVALID 0x00000040 222 #define MACH_FPC_ENABLE_BITS 0x00000f80 223 #define MACH_FPC_ENABLE_INEXACT 0x00000080 224 #define MACH_FPC_ENABLE_UNDERFLOW 0x00000100 225 #define MACH_FPC_ENABLE_OVERFLOW 0x00000200 226 #define MACH_FPC_ENABLE_DIV0 0x00000400 227 #define MACH_FPC_ENABLE_INVALID 0x00000800 228 #define MACH_FPC_EXCEPTION_BITS 0x0003f000 229 #define MACH_FPC_EXCEPTION_INEXACT 0x00001000 230 #define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000 231 #define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000 232 #define MACH_FPC_EXCEPTION_DIV0 0x00008000 233 #define MACH_FPC_EXCEPTION_INVALID 0x00010000 234 #define MACH_FPC_EXCEPTION_UNIMPL 0x00020000 235 #define MACH_FPC_COND_BIT 0x00800000 236 #define MACH_FPC_MBZ_BITS 0xff7c0000 237 238 /* 239 * Constants to determine if have a floating point instruction. 240 */ 241 #define MACH_OPCODE_SHIFT 26 242 #define MACH_OPCODE_C1 0x11 243 244 /* 245 * The low part of the TLB entry. 246 */ 247 #define VMMACH_TLB_PF_NUM 0xfffff000 248 #define VMMACH_TLB_NON_CACHEABLE_BIT 0x00000800 249 #define VMMACH_TLB_MOD_BIT 0x00000400 250 #define VMMACH_TLB_VALID_BIT 0x00000200 251 #define VMMACH_TLB_GLOBAL_BIT 0x00000100 252 253 #define VMMACH_TLB_PHYS_PAGE_SHIFT 12 254 255 /* 256 * The high part of the TLB entry. 257 */ 258 #define VMMACH_TLB_VIRT_PAGE_NUM 0xfffff000 259 #define VMMACH_TLB_PID 0x00000fc0 260 #define VMMACH_TLB_PID_SHIFT 6 261 #define VMMACH_TLB_VIRT_PAGE_SHIFT 12 262 263 /* 264 * The shift to put the index in the right spot. 265 */ 266 #define VMMACH_TLB_INDEX_SHIFT 8 267 268 /* 269 * The number of TLB entries and the first one that write random hits. 270 */ 271 #define VMMACH_NUM_TLB_ENTRIES 64 272 #define VMMACH_FIRST_RAND_ENTRY 8 273 274 /* 275 * The number of process id entries. 276 */ 277 #define VMMACH_NUM_PIDS 64 278 279 /* 280 * TLB probe return codes. 281 */ 282 #define VMMACH_TLB_NOT_FOUND 0 283 #define VMMACH_TLB_FOUND 1 284 #define VMMACH_TLB_FOUND_WITH_PATCH 2 285 #define VMMACH_TLB_PROBE_ERROR 3 286 287 /* 288 * Kernel virtual address for user page table entries 289 * (i.e., the address for the context register). 290 */ 291 #define VMMACH_PTE_BASE 0xFFC00000 292 293 #endif /* _MACHCONST */ 294