1 /* $NetBSD: cpu.h,v 1.70 2003/01/17 23:36:08 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 39 */ 40 41 #ifndef _CPU_H_ 42 #define _CPU_H_ 43 44 #include <mips/cpuregs.h> 45 46 /* 47 * Exported definitions unique to NetBSD/mips cpu support. 48 */ 49 50 #ifdef _KERNEL 51 #ifndef _LOCORE 52 #include <sys/sched.h> 53 54 #if defined(_KERNEL_OPT) 55 #include "opt_lockdebug.h" 56 #endif 57 58 struct cpu_info { 59 struct schedstate_percpu ci_schedstate; /* scheduler state */ 60 u_long ci_cpu_freq; /* CPU frequency */ 61 u_long ci_cycles_per_hz; /* CPU freq / hz */ 62 u_long ci_divisor_delay; /* for delay/DELAY */ 63 u_long ci_divisor_recip; /* scaled reciprocal of previous; 64 see below */ 65 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 66 u_long ci_spin_locks; /* # of spin locks held */ 67 u_long ci_simple_locks; /* # of simple locks held */ 68 #endif 69 }; 70 71 /* 72 * To implement a more accurate microtime using the CP0 COUNT register 73 * we need to divide that register by the number of cycles per MHz. 74 * But... 75 * 76 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 77 * and MULTU are only 12 clocks on the same CPU. 78 * 79 * The strategy we use is to calculate the reciprical of cycles per MHz, 80 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 81 * HI register and have the results of the division. 82 */ 83 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 84 do { \ 85 KASSERT((cpu)->ci_divisor_delay != 0); \ 86 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 87 } while (0) 88 89 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 90 asm volatile("multu %1,%2 ; mfhi %0" \ 91 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 92 93 #endif /* !_LOCORE */ 94 #endif /* _KERNEL */ 95 96 /* 97 * CTL_MACHDEP definitions. 98 */ 99 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 100 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 101 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 102 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 103 104 /* 105 * Platform can override, but note this breaks userland compatibility 106 * with other mips platforms. 107 */ 108 #ifndef CPU_MAXID 109 #define CPU_MAXID 5 /* number of valid machdep ids */ 110 111 #define CTL_MACHDEP_NAMES { \ 112 { 0, 0 }, \ 113 { "console_device", CTLTYPE_STRUCT }, \ 114 { "booted_kernel", CTLTYPE_STRING }, \ 115 { "root_device", CTLTYPE_STRING }, \ 116 { "llsc", CTLTYPE_INT }, \ 117 } 118 #endif 119 120 #ifdef _KERNEL 121 #ifndef _LOCORE 122 extern struct cpu_info cpu_info_store; 123 124 #define curcpu() (&cpu_info_store) 125 #define cpu_number() (0) 126 #define cpu_proc_fork(p1, p2) 127 #endif /* !_LOCORE */ 128 129 /* 130 * Macros to find the CPU architecture we're on at run-time, 131 * or if possible, at compile-time. 132 */ 133 134 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 135 #define CPU_ARCH_MIPS1 (1 << 0) 136 #define CPU_ARCH_MIPS2 (1 << 1) 137 #define CPU_ARCH_MIPS3 (1 << 2) 138 #define CPU_ARCH_MIPS4 (1 << 3) 139 #define CPU_ARCH_MIPS5 (1 << 4) 140 #define CPU_ARCH_MIPS32 (1 << 5) 141 #define CPU_ARCH_MIPS64 (1 << 6) 142 143 #ifndef _LOCORE 144 /* XXX simonb 145 * Should the following be in a cpu_info type structure? 146 * And how many of these are per-cpu vs. per-system? (Ie, 147 * we can assume that all cpus have the same mmu-type, but 148 * maybe not that all cpus run at the same clock speed. 149 * Some SGI's apparently support R12k and R14k in the same 150 * box.) 151 */ 152 extern int cpu_arch; 153 extern int mips_cpu_flags; 154 extern int mips_has_r4k_mmu; 155 extern int mips_has_llsc; 156 extern int mips3_pg_cached; 157 158 #define CPU_MIPS_R4K_MMU 0x0001 159 #define CPU_MIPS_NO_LLSC 0x0002 160 #define CPU_MIPS_CAUSE_IV 0x0004 161 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 162 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 163 #define CPU_MIPS_CACHED_CCA_SHIFT 4 164 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 165 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 166 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 167 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 168 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 169 #define MIPS_NOT_SUPP 0x8000 170 171 #ifdef _LKM 172 /* Assume all CPU architectures are valid for LKM's */ 173 #define MIPS1 1 174 #define MIPS3 1 175 #define MIPS4 1 176 #define MIPS32 1 177 #define MIPS64 1 178 #endif 179 180 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 181 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 182 #endif 183 184 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 185 #ifdef MIPS1 186 # define CPUISMIPS3 0 187 # define CPUIS64BITS 0 188 # define CPUISMIPS32 0 189 # define CPUISMIPS64 0 190 # define CPUISMIPSNN 0 191 # define MIPS_HAS_R4K_MMU 0 192 # define MIPS_HAS_CLOCK 0 193 # define MIPS_HAS_LLSC 0 194 #endif /* MIPS1 */ 195 196 #if defined(MIPS3) || defined(MIPS4) 197 # define CPUISMIPS3 1 198 # define CPUIS64BITS 1 199 # define CPUISMIPS32 0 200 # define CPUISMIPS64 0 201 # define CPUISMIPSNN 0 202 # define MIPS_HAS_R4K_MMU 1 203 # define MIPS_HAS_CLOCK 1 204 # define MIPS_HAS_LLSC (mips_has_llsc) 205 #endif /* MIPS3 || MIPS4 */ 206 207 #ifdef MIPS32 208 # define CPUISMIPS3 1 209 # define CPUIS64BITS 0 210 # define CPUISMIPS32 1 211 # define CPUISMIPS64 0 212 # define CPUISMIPSNN 1 213 # define MIPS_HAS_R4K_MMU 1 214 # define MIPS_HAS_CLOCK 1 215 # define MIPS_HAS_LLSC 1 216 #endif /* MIPS32 */ 217 218 #ifdef MIPS64 219 # define CPUISMIPS3 1 220 # define CPUIS64BITS 1 221 # define CPUISMIPS32 0 222 # define CPUISMIPS64 1 223 # define CPUISMIPSNN 1 224 # define MIPS_HAS_R4K_MMU 1 225 # define MIPS_HAS_CLOCK 1 226 # define MIPS_HAS_LLSC 1 227 #endif /* MIPS64 */ 228 229 #else /* run-time test */ 230 231 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 232 #define MIPS_HAS_LLSC (mips_has_llsc) 233 234 /* This test is ... rather bogus */ 235 #define CPUISMIPS3 ((cpu_arch & \ 236 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 237 238 /* And these aren't much better while the previous test exists as is... */ 239 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 240 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 241 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 242 #define CPUIS64BITS ((cpu_arch & \ 243 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 244 245 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 246 #endif /* run-time test */ 247 248 /* Shortcut for MIPS3 or above defined */ 249 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 250 #define MIPS3_PLUS 1 251 #else 252 #undef MIPS3_PLUS 253 #endif 254 255 256 /* 257 * definitions of cpu-dependent requirements 258 * referenced in generic code 259 */ 260 #define cpu_wait(p) /* nothing */ 261 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 262 263 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 264 265 /* 266 * Arguments to hardclock and gatherstats encapsulate the previous 267 * machine state in an opaque clockframe. 268 */ 269 struct clockframe { 270 int pc; /* program counter at time of interrupt */ 271 int sr; /* status register at time of interrupt */ 272 int ppl; /* previous priority level at time of interrupt */ 273 }; 274 275 /* 276 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 277 * in machine-independent code. These differ on r4000 and r3000 systems; 278 * provide them in the port-dependent file that includes this one, using 279 * the macros below. 280 */ 281 282 /* mips1 versions */ 283 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 284 #define MIPS1_CLKF_BASEPRI(framep) \ 285 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 286 287 /* mips3 versions */ 288 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 289 #define MIPS3_CLKF_BASEPRI(framep) \ 290 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 291 292 #ifdef IPL_ICU_MASK 293 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 294 #endif 295 296 #define CLKF_PC(framep) ((framep)->pc) 297 #define CLKF_INTR(framep) (0) 298 299 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 300 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 301 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 302 #endif 303 304 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 305 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 306 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 307 #endif 308 309 #ifdef IPL_ICU_MASK 310 #undef CLKF_BASEPRI 311 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 312 #endif 313 314 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 315 #define CLKF_USERMODE(framep) \ 316 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 317 #define CLKF_BASEPRI(framep) \ 318 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 319 #endif 320 321 /* 322 * This is used during profiling to integrate system time. It can safely 323 * assume that the process is resident. 324 */ 325 #define PROC_PC(p) \ 326 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 327 328 /* 329 * Preempt the current process if in interrupt from user mode, 330 * or after the current trap/syscall if in system mode. 331 */ 332 #define need_resched(ci) \ 333 do { \ 334 want_resched = 1; \ 335 if (curproc != NULL) \ 336 aston(curproc); \ 337 } while (/*CONSTCOND*/0) 338 339 /* 340 * Give a profiling tick to the current process when the user profiling 341 * buffer pages are invalid. On the MIPS, request an ast to send us 342 * through trap, marking the proc as needing a profiling tick. 343 */ 344 #define need_proftick(p) \ 345 do { \ 346 (p)->p_flag |= P_OWEUPC; \ 347 aston(p); \ 348 } while (/*CONSTCOND*/0) 349 350 /* 351 * Notify the current process (p) that it has a signal pending, 352 * process as soon as possible. 353 */ 354 #define signotify(p) aston(p) 355 356 #define aston(p) ((p)->p_md.md_astpending = 1) 357 358 extern int want_resched; /* resched() was called */ 359 360 /* 361 * Misc prototypes and variable declarations. 362 */ 363 struct lwp; 364 struct user; 365 366 extern struct lwp *fpcurlwp; /* the current FPU owner */ 367 extern struct pcb *curpcb; /* the current running pcb */ 368 extern struct segtab *segbase; /* current segtab base */ 369 370 /* trap.c */ 371 void netintr(void); 372 int kdbpeek(vaddr_t); 373 374 /* mips_machdep.c */ 375 void dumpsys(void); 376 int savectx(struct user *); 377 void mips_init_msgbuf(void); 378 void savefpregs(struct lwp *); 379 void loadfpregs(struct lwp *); 380 381 /* locore*.S */ 382 int badaddr(void *, size_t); 383 int badaddr64(uint64_t, size_t); 384 385 /* mips_machdep.c */ 386 void cpu_identify(void); 387 void mips_vector_init(void); 388 389 #endif /* ! _LOCORE */ 390 #endif /* _KERNEL */ 391 #endif /* _CPU_H_ */ 392