1 /* $NetBSD: cpu.h,v 1.117 2015/06/11 15:50:17 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 48 #if defined(_KERNEL_OPT) 49 #include "opt_cputype.h" 50 #include "opt_lockdebug.h" 51 #include "opt_multiprocessor.h" 52 #endif 53 54 #ifndef _LOCORE 55 #include <sys/cpu_data.h> 56 #include <sys/device_if.h> 57 #include <sys/evcnt.h> 58 #include <sys/kcpuset.h> 59 60 typedef struct cpu_watchpoint { 61 register_t cw_addr; 62 register_t cw_mask; 63 uint32_t cw_asid; 64 uint32_t cw_mode; 65 } cpu_watchpoint_t; 66 /* (abstract) mode bits */ 67 #define CPUWATCH_WRITE __BIT(0) 68 #define CPUWATCH_READ __BIT(1) 69 #define CPUWATCH_EXEC __BIT(2) 70 #define CPUWATCH_MASK __BIT(3) 71 #define CPUWATCH_ASID __BIT(4) 72 #define CPUWATCH_RWX (CPUWATCH_EXEC|CPUWATCH_READ|CPUWATCH_WRITE) 73 74 #define CPUWATCH_MAX 8 /* max possible number of watchpoints */ 75 76 u_int cpuwatch_discover(void); 77 void cpuwatch_free(cpu_watchpoint_t *); 78 cpu_watchpoint_t *cpuwatch_alloc(void); 79 void cpuwatch_set_all(void); 80 void cpuwatch_clr_all(void); 81 void cpuwatch_set(cpu_watchpoint_t *); 82 void cpuwatch_clr(cpu_watchpoint_t *); 83 84 struct cpu_info { 85 struct cpu_data ci_data; /* MI per-cpu data */ 86 void *ci_nmi_stack; /* NMI exception stack */ 87 struct cpu_softc *ci_softc; /* chip-dependent hook */ 88 device_t ci_dev; /* owning device */ 89 cpuid_t ci_cpuid; /* Machine-level identifier */ 90 u_long ci_cctr_freq; /* cycle counter frequency */ 91 u_long ci_cpu_freq; /* CPU frequency */ 92 u_long ci_cycles_per_hz; /* CPU freq / hz */ 93 u_long ci_divisor_delay; /* for delay/DELAY */ 94 u_long ci_divisor_recip; /* unused, for obsolete microtime(9) */ 95 struct lwp *ci_curlwp; /* currently running lwp */ 96 volatile int ci_want_resched; /* user preemption pending */ 97 int ci_mtx_count; /* negative count of held mutexes */ 98 int ci_mtx_oldspl; /* saved SPL value */ 99 int ci_idepth; /* hardware interrupt depth */ 100 int ci_cpl; /* current [interrupt] priority level */ 101 uint32_t ci_next_cp0_clk_intr; /* for hard clock intr scheduling */ 102 struct evcnt ci_ev_count_compare; /* hard clock intr counter */ 103 struct evcnt ci_ev_count_compare_missed; /* hard clock miss counter */ 104 struct lwp *ci_softlwps[SOFTINT_COUNT]; 105 volatile u_int ci_softints; 106 struct evcnt ci_ev_fpu_loads; /* fpu load counter */ 107 struct evcnt ci_ev_fpu_saves; /* fpu save counter */ 108 struct evcnt ci_ev_dsp_loads; /* dsp load counter */ 109 struct evcnt ci_ev_dsp_saves; /* dsp save counter */ 110 struct evcnt ci_ev_tlbmisses; 111 112 /* 113 * Per-cpu pmap information 114 */ 115 int ci_tlb_slot; /* reserved tlb entry for cpu_info */ 116 u_int ci_pmap_asid_cur; /* current ASID */ 117 struct pmap_tlb_info *ci_tlb_info; /* tlb information for this cpu */ 118 union pmap_segtab *ci_pmap_segtabs[2]; 119 #define ci_pmap_user_segtab ci_pmap_segtabs[0] 120 #define ci_pmap_kern_segtab ci_pmap_segtabs[1] 121 #ifdef _LP64 122 union pmap_segtab *ci_pmap_seg0tabs[2]; 123 #define ci_pmap_user_seg0tab ci_pmap_seg0tabs[0] 124 #define ci_pmap_kern_seg0tab ci_pmap_seg0tabs[1] 125 #else 126 vaddr_t ci_pmap_srcbase; /* starting VA of ephemeral src space */ 127 vaddr_t ci_pmap_dstbase; /* starting VA of ephemeral dst space */ 128 #endif 129 130 u_int ci_cpuwatch_count; /* number of watchpoints on this CPU */ 131 cpu_watchpoint_t ci_cpuwatch_tab[CPUWATCH_MAX]; 132 133 #ifdef MULTIPROCESSOR 134 volatile u_long ci_flags; 135 volatile uint64_t ci_request_ipis; 136 /* bitmask of IPIs requested */ 137 /* use on chips where hw cannot pass tag */ 138 uint64_t ci_active_ipis; /* bitmask of IPIs being serviced */ 139 uint32_t ci_ksp_tlb_slot; /* tlb entry for kernel stack */ 140 struct evcnt ci_evcnt_all_ipis; /* aggregated IPI counter */ 141 struct evcnt ci_evcnt_per_ipi[NIPIS]; /* individual IPI counters*/ 142 struct evcnt ci_evcnt_synci_activate_rqst; 143 struct evcnt ci_evcnt_synci_onproc_rqst; 144 struct evcnt ci_evcnt_synci_deferred_rqst; 145 struct evcnt ci_evcnt_synci_ipi_rqst; 146 147 #define CPUF_PRIMARY 0x01 /* CPU is primary CPU */ 148 #define CPUF_PRESENT 0x02 /* CPU is present */ 149 #define CPUF_RUNNING 0x04 /* CPU is running */ 150 #define CPUF_PAUSED 0x08 /* CPU is paused */ 151 #define CPUF_USERPMAP 0x20 /* CPU has a user pmap activated */ 152 #endif 153 154 }; 155 156 #ifdef MULTIPROCESSOR 157 #define CPU_INFO_ITERATOR int 158 #define CPU_INFO_FOREACH(cii, ci) \ 159 cii = 0, ci = cpu_infos[0]; cii < ncpu && (ci = cpu_infos[cii]) != NULL; cii++ 160 #else 161 #define CPU_INFO_ITERATOR int __unused 162 #define CPU_INFO_FOREACH(cii, ci) \ 163 ci = &cpu_info_store; ci != NULL; ci = NULL 164 #endif 165 166 #endif /* !_LOCORE */ 167 #endif /* _KERNEL */ 168 169 /* 170 * CTL_MACHDEP definitions. 171 */ 172 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 173 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 174 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 175 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 176 #define CPU_LMMI 5 /* Loongson multimedia instructions */ 177 178 /* 179 * Platform can override, but note this breaks userland compatibility 180 * with other mips platforms. 181 */ 182 #ifndef CPU_MAXID 183 #define CPU_MAXID 5 /* number of valid machdep ids */ 184 #endif 185 186 #ifdef _KERNEL 187 #if defined(_MODULAR) || defined(_LKM) || defined(_STANDALONE) 188 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 189 #if !defined(__mips_n32) && !defined(__mips_n64) 190 #define MIPS1 1 191 #endif 192 #define MIPS3 1 193 #define MIPS4 1 194 #if !defined(__mips_n32) && !defined(__mips_n64) 195 #define MIPS32 1 196 #define MIPS32R2 1 197 #endif 198 #define MIPS64 1 199 #define MIPS64R2 1 200 #endif 201 202 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 203 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified 204 #endif 205 206 /* Shortcut for MIPS3 or above defined */ 207 #if defined(MIPS3) || defined(MIPS4) \ 208 || defined(MIPS32) || defined(MIPS32R2) \ 209 || defined(MIPS64) || defined(MIPS64R2) 210 211 #define MIPS3_PLUS 1 212 #define __HAVE_CPU_COUNTER 213 #else 214 #undef MIPS3_PLUS 215 #endif 216 217 /* 218 * Macros to find the CPU architecture we're on at run-time, 219 * or if possible, at compile-time. 220 */ 221 222 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 223 #define CPU_ARCH_MIPS1 (1 << 0) 224 #define CPU_ARCH_MIPS2 (1 << 1) 225 #define CPU_ARCH_MIPS3 (1 << 2) 226 #define CPU_ARCH_MIPS4 (1 << 3) 227 #define CPU_ARCH_MIPS5 (1 << 4) 228 #define CPU_ARCH_MIPS32 (1 << 5) 229 #define CPU_ARCH_MIPS64 (1 << 6) 230 #define CPU_ARCH_MIPS32R2 (1 << 7) 231 #define CPU_ARCH_MIPS64R2 (1 << 8) 232 233 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 234 // MIPS_CURLWP moved to <mips/regdef.h> 235 #define MIPS_CURLWP_QUOTED "$24" 236 #define MIPS_CURLWP_LABEL _L_T8 237 #define MIPS_CURLWP_REG _R_T8 238 239 #ifndef _LOCORE 240 241 extern struct cpu_info cpu_info_store; 242 #ifdef MULTIPROCESSOR 243 extern struct cpu_info *cpuid_infos[]; 244 #endif 245 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 246 247 #define curlwp mips_curlwp 248 #define curcpu() lwp_getcpu(curlwp) 249 #define curpcb ((struct pcb *)lwp_getpcb(curlwp)) 250 #ifdef MULTIPROCESSOR 251 #define cpu_number() (curcpu()->ci_index) 252 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 253 #else 254 #define cpu_number() (0) 255 #define CPU_IS_PRIMARY(ci) (true) 256 #endif 257 258 /* XXX simonb 259 * Should the following be in a cpu_info type structure? 260 * And how many of these are per-cpu vs. per-system? (Ie, 261 * we can assume that all cpus have the same mmu-type, but 262 * maybe not that all cpus run at the same clock speed. 263 * Some SGI's apparently support R12k and R14k in the same 264 * box.) 265 */ 266 struct mips_options { 267 const struct pridtab *mips_cpu; 268 269 u_int mips_cpu_arch; 270 u_int mips_cpu_mhz; /* CPU speed in MHz, estimated by mc_cpuspeed(). */ 271 u_int mips_cpu_flags; 272 u_int mips_num_tlb_entries; 273 mips_prid_t mips_cpu_id; 274 mips_prid_t mips_fpu_id; 275 bool mips_has_r4k_mmu; 276 bool mips_has_llsc; 277 u_int mips3_pg_shift; 278 u_int mips3_pg_cached; 279 u_int mips3_cca_devmem; 280 #ifdef MIPS3_PLUS 281 #ifdef _LP64 282 uint64_t mips3_xkphys_cached; 283 #endif 284 uint64_t mips3_tlb_vpn_mask; 285 uint64_t mips3_tlb_pfn_mask; 286 uint32_t mips3_tlb_pg_mask; 287 #endif 288 }; 289 extern struct mips_options mips_options; 290 291 #define CPU_MIPS_R4K_MMU 0x0001 292 #define CPU_MIPS_NO_LLSC 0x0002 293 #define CPU_MIPS_CAUSE_IV 0x0004 294 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 295 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 296 #define CPU_MIPS_CACHED_CCA_SHIFT 4 297 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 298 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 299 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 300 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 301 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 302 #define CPU_MIPS_NO_LLADDR 0x1000 303 #define CPU_MIPS_HAVE_MxCR 0x2000 /* have mfcr, mtcr insns */ 304 #define CPU_MIPS_LOONGSON2 0x4000 305 #define MIPS_NOT_SUPP 0x8000 306 #define CPU_MIPS_HAVE_DSP 0x10000 307 308 #endif /* !_LOCORE */ 309 310 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE) 311 312 #if defined(MIPS1) 313 314 # define CPUISMIPS3 0 315 # define CPUIS64BITS 0 316 # define CPUISMIPS32 0 317 # define CPUISMIPS32R2 0 318 # define CPUISMIPS64 0 319 # define CPUISMIPS64R2 0 320 # define CPUISMIPSNN 0 321 # define MIPS_HAS_R4K_MMU 0 322 # define MIPS_HAS_CLOCK 0 323 # define MIPS_HAS_LLSC 0 324 # define MIPS_HAS_LLADDR 0 325 # define MIPS_HAS_DSP 0 326 # define MIPS_HAS_LMMI 0 327 328 #elif defined(MIPS3) || defined(MIPS4) 329 330 # define CPUISMIPS3 1 331 # define CPUIS64BITS 1 332 # define CPUISMIPS32 0 333 # define CPUISMIPS32R2 0 334 # define CPUISMIPS64 0 335 # define CPUISMIPS64R2 0 336 # define CPUISMIPSNN 0 337 # define MIPS_HAS_R4K_MMU 1 338 # define MIPS_HAS_CLOCK 1 339 # if defined(_LOCORE) 340 # if !defined(MIPS3_4100) 341 # define MIPS_HAS_LLSC 1 342 # else 343 # define MIPS_HAS_LLSC 0 344 # endif 345 # else /* _LOCORE */ 346 # define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 347 # endif /* _LOCORE */ 348 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 349 # define MIPS_HAS_DSP 0 350 # if defined(MIPS3_LOONGSON2) 351 # define MIPS_HAS_LMMI ((mips_options.mips_cpu_flags & CPU_MIPS_LOONGSON2) != 0) 352 # else 353 # define MIPS_HAS_LMMI 0 354 # endif 355 #elif defined(MIPS32) 356 357 # define CPUISMIPS3 1 358 # define CPUIS64BITS 0 359 # define CPUISMIPS32 1 360 # define CPUISMIPS32R2 0 361 # define CPUISMIPS64 0 362 # define CPUISMIPS64R2 0 363 # define CPUISMIPSNN 1 364 # define MIPS_HAS_R4K_MMU 1 365 # define MIPS_HAS_CLOCK 1 366 # define MIPS_HAS_LLSC 1 367 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 368 # define MIPS_HAS_DSP 0 369 # define MIPS_HAS_LMMI 0 370 371 #elif defined(MIPS32R2) 372 373 # define CPUISMIPS3 1 374 # define CPUIS64BITS 0 375 # define CPUISMIPS32 0 376 # define CPUISMIPS32R2 1 377 # define CPUISMIPS64 0 378 # define CPUISMIPS64R2 0 379 # define CPUISMIPSNN 1 380 # define MIPS_HAS_R4K_MMU 1 381 # define MIPS_HAS_CLOCK 1 382 # define MIPS_HAS_LLSC 1 383 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 384 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 385 # define MIPS_HAS_LMMI 0 386 387 #elif defined(MIPS64) 388 389 # define CPUISMIPS3 1 390 # define CPUIS64BITS 1 391 # define CPUISMIPS32 0 392 # define CPUISMIPS32R2 0 393 # define CPUISMIPS64 1 394 # define CPUISMIPS64R2 0 395 # define CPUISMIPSNN 1 396 # define MIPS_HAS_R4K_MMU 1 397 # define MIPS_HAS_CLOCK 1 398 # define MIPS_HAS_LLSC 1 399 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 400 # define MIPS_HAS_DSP 0 401 # define MIPS_HAS_LMMI 0 402 403 #elif defined(MIPS64R2) 404 405 # define CPUISMIPS3 1 406 # define CPUIS64BITS 1 407 # define CPUISMIPS32 0 408 # define CPUISMIPS32R2 0 409 # define CPUISMIPS64 0 410 # define CPUISMIPS64R2 1 411 # define CPUISMIPSNN 1 412 # define MIPS_HAS_R4K_MMU 1 413 # define MIPS_HAS_CLOCK 1 414 # define MIPS_HAS_LLSC 1 415 # define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 416 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 417 # define MIPS_HAS_LMMI 0 418 419 #endif 420 421 #else /* run-time test */ 422 423 #ifndef _LOCORE 424 425 #define MIPS_HAS_R4K_MMU (mips_options.mips_has_r4k_mmu) 426 #define MIPS_HAS_LLSC (mips_options.mips_has_llsc) 427 #define MIPS_HAS_LLADDR ((mips_options.mips_cpu_flags & CPU_MIPS_NO_LLADDR) == 0) 428 # define MIPS_HAS_DSP (mips_options.mips_cpu_flags & CPU_MIPS_HAVE_DSP) 429 430 /* This test is ... rather bogus */ 431 #define CPUISMIPS3 ((mips_options.mips_cpu_arch & \ 432 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 433 434 /* And these aren't much better while the previous test exists as is... */ 435 #define CPUISMIPS4 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS4) != 0) 436 #define CPUISMIPS5 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS5) != 0) 437 #define CPUISMIPS32 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32) != 0) 438 #define CPUISMIPS32R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS32R2) != 0) 439 #define CPUISMIPS64 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64) != 0) 440 #define CPUISMIPS64R2 ((mips_options.mips_cpu_arch & CPU_ARCH_MIPS64R2) != 0) 441 #define CPUISMIPSNN ((mips_options.mips_cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS32R2 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 442 #define CPUIS64BITS ((mips_options.mips_cpu_arch & \ 443 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64 | CPU_ARCH_MIPS64R2)) != 0) 444 445 #define MIPS_HAS_CLOCK (mips_options.mips_cpu_arch >= CPU_ARCH_MIPS3) 446 447 #else /* !_LOCORE */ 448 449 #define MIPS_HAS_LLSC 0 450 451 #endif /* !_LOCORE */ 452 453 #endif /* run-time test */ 454 455 #ifndef _LOCORE 456 457 /* 458 * definitions of cpu-dependent requirements 459 * referenced in generic code 460 */ 461 462 /* 463 * Send an inter-processor interupt to each other CPU (excludes curcpu()) 464 */ 465 void cpu_broadcast_ipi(int); 466 467 /* 468 * Send an inter-processor interupt to CPUs in kcpuset (excludes curcpu()) 469 */ 470 void cpu_multicast_ipi(const kcpuset_t *, int); 471 472 /* 473 * Send an inter-processor interupt to another CPU. 474 */ 475 int cpu_send_ipi(struct cpu_info *, int); 476 477 /* 478 * cpu_intr(ppl, pc, status); (most state needed by clockframe) 479 */ 480 void cpu_intr(int, vaddr_t, uint32_t); 481 482 /* 483 * Arguments to hardclock and gatherstats encapsulate the previous 484 * machine state in an opaque clockframe. 485 */ 486 struct clockframe { 487 vaddr_t pc; /* program counter at time of interrupt */ 488 uint32_t sr; /* status register at time of interrupt */ 489 bool intr; /* interrupted a interrupt */ 490 }; 491 492 /* 493 * A port must provde CLKF_USERMODE() for use in machine-independent code. 494 * These differ on r4000 and r3000 systems; provide them in the 495 * port-dependent file that includes this one, using the macros below. 496 */ 497 498 /* mips1 versions */ 499 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 500 501 /* mips3 versions */ 502 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 503 504 #define CLKF_PC(framep) ((framep)->pc) 505 #define CLKF_INTR(framep) ((framep)->intr) 506 507 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 508 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 509 #endif 510 511 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 512 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 513 #endif 514 515 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 516 #define CLKF_USERMODE(framep) \ 517 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 518 #endif 519 520 /* 521 * Misc prototypes and variable declarations. 522 */ 523 #define LWP_PC(l) cpu_lwp_pc(l) 524 525 struct proc; 526 struct lwp; 527 struct pcb; 528 struct reg; 529 530 /* 531 * Preempt the current process if in interrupt from user mode, 532 * or after the current trap/syscall if in system mode. 533 */ 534 void cpu_need_resched(struct cpu_info *, int); 535 /* 536 * Notify the current lwp (l) that it has a signal pending, 537 * process as soon as possible. 538 */ 539 void cpu_signotify(struct lwp *); 540 541 /* 542 * Give a profiling tick to the current process when the user profiling 543 * buffer pages are invalid. On the MIPS, request an ast to send us 544 * through trap, marking the proc as needing a profiling tick. 545 */ 546 void cpu_need_proftick(struct lwp *); 547 void cpu_set_curpri(int); 548 549 extern int mips_poolpage_vmfreelist; /* freelist to allocate poolpages */ 550 551 struct cpu_info * 552 cpu_info_alloc(struct pmap_tlb_info *, cpuid_t, cpuid_t, cpuid_t, 553 cpuid_t); 554 void cpu_attach_common(device_t, struct cpu_info *); 555 void cpu_startup_common(void); 556 #ifdef _LP64 557 void cpu_vmspace_exec(struct lwp *, vaddr_t, vaddr_t); 558 #endif 559 560 #ifdef MULTIPROCESSOR 561 void cpu_hatch(struct cpu_info *ci); 562 void cpu_trampoline(void); 563 void cpu_boot_secondary_processors(void); 564 void cpu_halt(void); 565 void cpu_halt_others(void); 566 void cpu_pause(struct reg *); 567 void cpu_pause_others(void); 568 void cpu_resume(cpuid_t); 569 void cpu_resume_others(void); 570 bool cpu_is_paused(cpuid_t); 571 void cpu_debug_dump(void); 572 573 extern kcpuset_t *cpus_running; 574 extern kcpuset_t *cpus_hatched; 575 extern kcpuset_t *cpus_paused; 576 extern kcpuset_t *cpus_resumed; 577 extern kcpuset_t *cpus_halted; 578 #endif 579 580 /* copy.S */ 581 int32_t kfetch_32(volatile uint32_t *, uint32_t); 582 int8_t ufetch_int8(void *); 583 int16_t ufetch_int16(void *); 584 int32_t ufetch_int32(void *); 585 uint8_t ufetch_uint8(void *); 586 uint16_t ufetch_uint16(void *); 587 uint32_t ufetch_uint32(void *); 588 int8_t ufetch_int8_intrsafe(void *); 589 int16_t ufetch_int16_intrsafe(void *); 590 int32_t ufetch_int32_intrsafe(void *); 591 uint8_t ufetch_uint8_intrsafe(void *); 592 uint16_t ufetch_uint16_intrsafe(void *); 593 uint32_t ufetch_uint32_intrsafe(void *); 594 #ifdef _LP64 595 int64_t ufetch_int64(void *); 596 uint64_t ufetch_uint64(void *); 597 int64_t ufetch_int64_intrsafe(void *); 598 uint64_t ufetch_uint64_intrsafe(void *); 599 #endif 600 char ufetch_char(void *); 601 short ufetch_short(void *); 602 int ufetch_int(void *); 603 long ufetch_long(void *); 604 char ufetch_char_intrsafe(void *); 605 short ufetch_short_intrsafe(void *); 606 int ufetch_int_intrsafe(void *); 607 long ufetch_long_intrsafe(void *); 608 609 u_char ufetch_uchar(void *); 610 u_short ufetch_ushort(void *); 611 u_int ufetch_uint(void *); 612 u_long ufetch_ulong(void *); 613 u_char ufetch_uchar_intrsafe(void *); 614 u_short ufetch_ushort_intrsafe(void *); 615 u_int ufetch_uint_intrsafe(void *); 616 u_long ufetch_ulong_intrsafe(void *); 617 void *ufetch_ptr(void *); 618 619 int ustore_int8(void *, int8_t); 620 int ustore_int16(void *, int16_t); 621 int ustore_int32(void *, int32_t); 622 int ustore_uint8(void *, uint8_t); 623 int ustore_uint16(void *, uint16_t); 624 int ustore_uint32(void *, uint32_t); 625 int ustore_int8_intrsafe(void *, int8_t); 626 int ustore_int16_intrsafe(void *, int16_t); 627 int ustore_int32_intrsafe(void *, int32_t); 628 int ustore_uint8_intrsafe(void *, uint8_t); 629 int ustore_uint16_intrsafe(void *, uint16_t); 630 int ustore_uint32_intrsafe(void *, uint32_t); 631 #ifdef _LP64 632 int ustore_int64(void *, int64_t); 633 int ustore_uint64(void *, uint64_t); 634 int ustore_int64_intrsafe(void *, int64_t); 635 int ustore_uint64_intrsafe(void *, uint64_t); 636 #endif 637 int ustore_char(void *, char); 638 int ustore_char_intrsafe(void *, char); 639 int ustore_short(void *, short); 640 int ustore_short_intrsafe(void *, short); 641 int ustore_int(void *, int); 642 int ustore_int_intrsafe(void *, int); 643 int ustore_long(void *, long); 644 int ustore_long_intrsafe(void *, long); 645 int ustore_uchar(void *, u_char); 646 int ustore_uchar_intrsafe(void *, u_char); 647 int ustore_ushort(void *, u_short); 648 int ustore_ushort_intrsafe(void *, u_short); 649 int ustore_uint(void *, u_int); 650 int ustore_uint_intrsafe(void *, u_int); 651 int ustore_ulong(void *, u_long); 652 int ustore_ulong_intrsafe(void *, u_long); 653 int ustore_ptr(void *, void *); 654 int ustore_ptr_intrsafe(void *, void *); 655 656 int ustore_uint32_isync(void *, uint32_t); 657 658 /* trap.c */ 659 void netintr(void); 660 int kdbpeek(vaddr_t); 661 662 /* mips_dsp.c */ 663 void dsp_init(void); 664 void dsp_discard(void); 665 void dsp_load(void); 666 void dsp_save(void); 667 bool dsp_used_p(void); 668 extern const pcu_ops_t mips_dsp_ops; 669 670 /* mips_fpu.c */ 671 void fpu_init(void); 672 void fpu_discard(void); 673 void fpu_load(void); 674 void fpu_save(void); 675 bool fpu_used_p(void); 676 extern const pcu_ops_t mips_fpu_ops; 677 678 /* mips_machdep.c */ 679 void dumpsys(void); 680 int savectx(struct pcb *); 681 void cpu_identify(device_t); 682 683 /* locore*.S */ 684 int badaddr(void *, size_t); 685 int badaddr64(uint64_t, size_t); 686 687 /* vm_machdep.c */ 688 void * cpu_uarea_alloc(bool); 689 bool cpu_uarea_free(void *); 690 void cpu_proc_fork(struct proc *, struct proc *); 691 vaddr_t cpu_lwp_pc(struct lwp *); 692 int ioaccess(vaddr_t, paddr_t, vsize_t); 693 int iounaccess(vaddr_t, vsize_t); 694 695 #endif /* ! _LOCORE */ 696 #endif /* _KERNEL */ 697 #endif /* _CPU_H_ */ 698