1 /* $NetBSD: cpu.h,v 1.87 2007/12/04 02:43:48 he Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 50 #if defined(_KERNEL_OPT) 51 #include "opt_lockdebug.h" 52 #endif 53 54 struct cpu_info { 55 struct cpu_data ci_data; /* MI per-cpu data */ 56 struct cpu_info *ci_next; /* Next CPU in list */ 57 cpuid_t ci_cpuid; /* Machine-level identifier */ 58 u_long ci_cpu_freq; /* CPU frequency */ 59 u_long ci_cycles_per_hz; /* CPU freq / hz */ 60 u_long ci_divisor_delay; /* for delay/DELAY */ 61 u_long ci_divisor_recip; /* scaled reciprocal of previous; 62 see below */ 63 struct lwp *ci_curlwp; /* currently running lwp */ 64 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 65 int ci_want_resched; /* user preemption pending */ 66 int ci_mtx_count; /* negative count of held mutexes */ 67 int ci_mtx_oldspl; /* saved SPL value */ 68 int ci_idepth; /* hardware interrupt depth */ 69 }; 70 71 #define CPU_INFO_ITERATOR int 72 #define CPU_INFO_FOREACH(cii, ci) \ 73 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 74 75 /* 76 * To implement a more accurate microtime using the CP0 COUNT register 77 * we need to divide that register by the number of cycles per MHz. 78 * But... 79 * 80 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 81 * and MULTU are only 12 clocks on the same CPU. 82 * 83 * The strategy we use is to calculate the reciprical of cycles per MHz, 84 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 85 * HI register and have the results of the division. 86 */ 87 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 88 do { \ 89 KASSERT((cpu)->ci_divisor_delay != 0); \ 90 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 91 } while (0) 92 93 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 94 __asm volatile("multu %1,%2 ; mfhi %0" \ 95 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 96 97 #endif /* !_LOCORE */ 98 #endif /* _KERNEL */ 99 100 /* 101 * CTL_MACHDEP definitions. 102 */ 103 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 104 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 105 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 106 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 107 108 /* 109 * Platform can override, but note this breaks userland compatibility 110 * with other mips platforms. 111 */ 112 #ifndef CPU_MAXID 113 #define CPU_MAXID 5 /* number of valid machdep ids */ 114 115 #define CTL_MACHDEP_NAMES { \ 116 { 0, 0 }, \ 117 { "console_device", CTLTYPE_STRUCT }, \ 118 { "booted_kernel", CTLTYPE_STRING }, \ 119 { "root_device", CTLTYPE_STRING }, \ 120 { "llsc", CTLTYPE_INT }, \ 121 } 122 #endif 123 124 #ifdef _KERNEL 125 #if defined(_LKM) || defined(_STANDALONE) 126 /* Assume all CPU architectures are valid for LKM's and standlone progs */ 127 #define MIPS1 1 128 #define MIPS3 1 129 #define MIPS4 1 130 #define MIPS32 1 131 #define MIPS64 1 132 #endif 133 134 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 135 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 136 #endif 137 138 /* Shortcut for MIPS3 or above defined */ 139 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 140 #define MIPS3_PLUS 1 141 #else 142 #undef MIPS3_PLUS 143 #endif 144 145 /* 146 * Macros to find the CPU architecture we're on at run-time, 147 * or if possible, at compile-time. 148 */ 149 150 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 151 #define CPU_ARCH_MIPS1 (1 << 0) 152 #define CPU_ARCH_MIPS2 (1 << 1) 153 #define CPU_ARCH_MIPS3 (1 << 2) 154 #define CPU_ARCH_MIPS4 (1 << 3) 155 #define CPU_ARCH_MIPS5 (1 << 4) 156 #define CPU_ARCH_MIPS32 (1 << 5) 157 #define CPU_ARCH_MIPS64 (1 << 6) 158 159 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 160 #define MIPS_CURLWP $23 161 #define MIPS_CURLWP_QUOTED "$23" 162 #define MIPS_CURLWP_CARD 23 163 #define MIPS_CURLWP_FRAME(x) FRAME_S7(x) 164 165 #ifndef _LOCORE 166 167 extern struct cpu_info cpu_info_store; 168 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 169 170 #define curlwp mips_curlwp 171 #define curcpu() (curlwp->l_cpu) 172 #define curpcb ((struct pcb *)curlwp->l_addr) 173 #define fpcurlwp (curcpu()->ci_fpcurlwp) 174 #define cpu_number() (0) 175 #define cpu_proc_fork(p1, p2) 176 177 /* XXX simonb 178 * Should the following be in a cpu_info type structure? 179 * And how many of these are per-cpu vs. per-system? (Ie, 180 * we can assume that all cpus have the same mmu-type, but 181 * maybe not that all cpus run at the same clock speed. 182 * Some SGI's apparently support R12k and R14k in the same 183 * box.) 184 */ 185 extern int cpu_arch; 186 extern int mips_cpu_flags; 187 extern int mips_has_r4k_mmu; 188 extern int mips_has_llsc; 189 extern int mips3_pg_cached; 190 extern u_int mips3_pg_shift; 191 192 #define CPU_MIPS_R4K_MMU 0x0001 193 #define CPU_MIPS_NO_LLSC 0x0002 194 #define CPU_MIPS_CAUSE_IV 0x0004 195 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 196 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 197 #define CPU_MIPS_CACHED_CCA_SHIFT 4 198 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 199 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 200 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 201 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 202 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 203 #define MIPS_NOT_SUPP 0x8000 204 205 #endif /* !_LOCORE */ 206 207 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 208 209 #if defined(MIPS1) 210 211 # define CPUISMIPS3 0 212 # define CPUIS64BITS 0 213 # define CPUISMIPS32 0 214 # define CPUISMIPS64 0 215 # define CPUISMIPSNN 0 216 # define MIPS_HAS_R4K_MMU 0 217 # define MIPS_HAS_CLOCK 0 218 # define MIPS_HAS_LLSC 0 219 220 #elif defined(MIPS3) || defined(MIPS4) 221 222 # define CPUISMIPS3 1 223 # define CPUIS64BITS 1 224 # define CPUISMIPS32 0 225 # define CPUISMIPS64 0 226 # define CPUISMIPSNN 0 227 # define MIPS_HAS_R4K_MMU 1 228 # define MIPS_HAS_CLOCK 1 229 # if defined(_LOCORE) 230 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 231 # define MIPS_HAS_LLSC 1 232 # else 233 # define MIPS_HAS_LLSC 0 234 # endif 235 # else /* _LOCORE */ 236 # define MIPS_HAS_LLSC (mips_has_llsc) 237 # endif /* _LOCORE */ 238 239 #elif defined(MIPS32) 240 241 # define CPUISMIPS3 1 242 # define CPUIS64BITS 0 243 # define CPUISMIPS32 1 244 # define CPUISMIPS64 0 245 # define CPUISMIPSNN 1 246 # define MIPS_HAS_R4K_MMU 1 247 # define MIPS_HAS_CLOCK 1 248 # define MIPS_HAS_LLSC 1 249 250 #elif defined(MIPS64) 251 252 # define CPUISMIPS3 1 253 # define CPUIS64BITS 1 254 # define CPUISMIPS32 0 255 # define CPUISMIPS64 1 256 # define CPUISMIPSNN 1 257 # define MIPS_HAS_R4K_MMU 1 258 # define MIPS_HAS_CLOCK 1 259 # define MIPS_HAS_LLSC 1 260 261 #endif 262 263 #else /* run-time test */ 264 265 #ifndef _LOCORE 266 267 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 268 #define MIPS_HAS_LLSC (mips_has_llsc) 269 270 /* This test is ... rather bogus */ 271 #define CPUISMIPS3 ((cpu_arch & \ 272 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 273 274 /* And these aren't much better while the previous test exists as is... */ 275 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 276 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 277 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 278 #define CPUIS64BITS ((cpu_arch & \ 279 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 280 281 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 282 283 #else /* !_LOCORE */ 284 285 #define MIPS_HAS_LLSC 0 286 287 #endif /* !_LOCORE */ 288 289 #endif /* run-time test */ 290 291 #ifndef _LOCORE 292 293 /* 294 * definitions of cpu-dependent requirements 295 * referenced in generic code 296 */ 297 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 298 299 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 300 301 /* 302 * Arguments to hardclock and gatherstats encapsulate the previous 303 * machine state in an opaque clockframe. 304 */ 305 struct clockframe { 306 int pc; /* program counter at time of interrupt */ 307 int sr; /* status register at time of interrupt */ 308 int ppl; /* previous priority level at time of interrupt */ 309 }; 310 311 /* 312 * A port must provde CLKF_USERMODE() for use in machine-independent code. 313 * These differ on r4000 and r3000 systems; provide them in the 314 * port-dependent file that includes this one, using the macros below. 315 */ 316 317 /* mips1 versions */ 318 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 319 320 /* mips3 versions */ 321 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 322 323 #define CLKF_PC(framep) ((framep)->pc) 324 #define CLKF_INTR(framep) (0) 325 326 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 327 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 328 #endif 329 330 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 331 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 332 #endif 333 334 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 335 #define CLKF_USERMODE(framep) \ 336 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 337 #endif 338 339 /* 340 * This is used during profiling to integrate system time. It can safely 341 * assume that the process is resident. 342 */ 343 #define PROC_PC(p) \ 344 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 345 346 /* 347 * Preempt the current process if in interrupt from user mode, 348 * or after the current trap/syscall if in system mode. 349 */ 350 void cpu_need_resched(struct cpu_info *, int); 351 352 /* 353 * Give a profiling tick to the current process when the user profiling 354 * buffer pages are invalid. On the MIPS, request an ast to send us 355 * through trap, marking the proc as needing a profiling tick. 356 */ 357 #define cpu_need_proftick(l) \ 358 do { \ 359 (l)->l_pflag |= LP_OWEUPC; \ 360 aston(l); \ 361 } while (/*CONSTCOND*/0) 362 363 /* 364 * Notify the current lwp (l) that it has a signal pending, 365 * process as soon as possible. 366 */ 367 #define cpu_signotify(l) aston(l) 368 369 #define aston(l) ((l)->l_md.md_astpending = 1) 370 371 /* 372 * Misc prototypes and variable declarations. 373 */ 374 struct lwp; 375 struct user; 376 377 extern struct segtab *segbase; /* current segtab base */ 378 379 /* trap.c */ 380 void netintr(void); 381 int kdbpeek(vaddr_t); 382 383 /* mips_machdep.c */ 384 void dumpsys(void); 385 int savectx(struct user *); 386 void mips_init_msgbuf(void); 387 void savefpregs(struct lwp *); 388 void loadfpregs(struct lwp *); 389 390 /* locore*.S */ 391 int badaddr(void *, size_t); 392 int badaddr64(uint64_t, size_t); 393 394 /* mips_machdep.c */ 395 void cpu_identify(void); 396 void mips_vector_init(void); 397 398 #endif /* ! _LOCORE */ 399 #endif /* _KERNEL */ 400 #endif /* _CPU_H_ */ 401