1 /* $NetBSD: cpu.h,v 1.85 2007/10/19 11:41:27 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/cpu_data.h> 49 50 #if defined(_KERNEL_OPT) 51 #include "opt_lockdebug.h" 52 #endif 53 54 struct cpu_info { 55 struct cpu_data ci_data; /* MI per-cpu data */ 56 struct cpu_info *ci_next; /* Next CPU in list */ 57 cpuid_t ci_cpuid; /* Machine-level identifier */ 58 u_long ci_cpu_freq; /* CPU frequency */ 59 u_long ci_cycles_per_hz; /* CPU freq / hz */ 60 u_long ci_divisor_delay; /* for delay/DELAY */ 61 u_long ci_divisor_recip; /* scaled reciprocal of previous; 62 see below */ 63 struct lwp *ci_curlwp; /* currently running lwp */ 64 struct lwp *ci_fpcurlwp; /* the current FPU owner */ 65 int ci_want_resched; /* user preemption pending */ 66 int ci_mtx_count; /* negative count of held mutexes */ 67 int ci_mtx_oldspl; /* saved SPL value */ 68 }; 69 70 #define CPU_INFO_ITERATOR int 71 #define CPU_INFO_FOREACH(cii, ci) \ 72 (void)(cii), ci = &cpu_info_store; ci != NULL; ci = ci->ci_next 73 74 /* 75 * To implement a more accurate microtime using the CP0 COUNT register 76 * we need to divide that register by the number of cycles per MHz. 77 * But... 78 * 79 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 80 * and MULTU are only 12 clocks on the same CPU. 81 * 82 * The strategy we use is to calculate the reciprical of cycles per MHz, 83 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 84 * HI register and have the results of the division. 85 */ 86 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 87 do { \ 88 KASSERT((cpu)->ci_divisor_delay != 0); \ 89 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 90 } while (0) 91 92 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 93 __asm volatile("multu %1,%2 ; mfhi %0" \ 94 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 95 96 #endif /* !_LOCORE */ 97 #endif /* _KERNEL */ 98 99 /* 100 * CTL_MACHDEP definitions. 101 */ 102 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 103 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 104 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 105 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 106 107 /* 108 * Platform can override, but note this breaks userland compatibility 109 * with other mips platforms. 110 */ 111 #ifndef CPU_MAXID 112 #define CPU_MAXID 5 /* number of valid machdep ids */ 113 114 #define CTL_MACHDEP_NAMES { \ 115 { 0, 0 }, \ 116 { "console_device", CTLTYPE_STRUCT }, \ 117 { "booted_kernel", CTLTYPE_STRING }, \ 118 { "root_device", CTLTYPE_STRING }, \ 119 { "llsc", CTLTYPE_INT }, \ 120 } 121 #endif 122 123 #ifdef _KERNEL 124 #ifdef _LKM 125 /* Assume all CPU architectures are valid for LKM's */ 126 #define MIPS1 1 127 #define MIPS3 1 128 #define MIPS4 1 129 #define MIPS32 1 130 #define MIPS64 1 131 #endif 132 133 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 134 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 135 #endif 136 137 /* Shortcut for MIPS3 or above defined */ 138 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 139 #define MIPS3_PLUS 1 140 #else 141 #undef MIPS3_PLUS 142 #endif 143 144 /* 145 * Macros to find the CPU architecture we're on at run-time, 146 * or if possible, at compile-time. 147 */ 148 149 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 150 #define CPU_ARCH_MIPS1 (1 << 0) 151 #define CPU_ARCH_MIPS2 (1 << 1) 152 #define CPU_ARCH_MIPS3 (1 << 2) 153 #define CPU_ARCH_MIPS4 (1 << 3) 154 #define CPU_ARCH_MIPS5 (1 << 4) 155 #define CPU_ARCH_MIPS32 (1 << 5) 156 #define CPU_ARCH_MIPS64 (1 << 6) 157 158 /* Note: must be kept in sync with -ffixed-?? Makefile.mips. */ 159 #define MIPS_CURLWP $23 160 #define MIPS_CURLWP_QUOTED "$23" 161 #define MIPS_CURLWP_CARD 23 162 #define MIPS_CURLWP_FRAME(x) FRAME_S7(x) 163 164 #ifndef _LOCORE 165 166 extern struct cpu_info cpu_info_store; 167 register struct lwp *mips_curlwp asm(MIPS_CURLWP_QUOTED); 168 169 #define curlwp mips_curlwp 170 #define curcpu() (curlwp->l_cpu) 171 #define curpcb ((struct pcb *)curlwp->l_addr) 172 #define fpcurlwp (curcpu()->ci_fpcurlwp) 173 #define cpu_number() (0) 174 #define cpu_proc_fork(p1, p2) 175 176 /* XXX simonb 177 * Should the following be in a cpu_info type structure? 178 * And how many of these are per-cpu vs. per-system? (Ie, 179 * we can assume that all cpus have the same mmu-type, but 180 * maybe not that all cpus run at the same clock speed. 181 * Some SGI's apparently support R12k and R14k in the same 182 * box.) 183 */ 184 extern int cpu_arch; 185 extern int mips_cpu_flags; 186 extern int mips_has_r4k_mmu; 187 extern int mips_has_llsc; 188 extern int mips3_pg_cached; 189 extern u_int mips3_pg_shift; 190 191 #define CPU_MIPS_R4K_MMU 0x0001 192 #define CPU_MIPS_NO_LLSC 0x0002 193 #define CPU_MIPS_CAUSE_IV 0x0004 194 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 195 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 196 #define CPU_MIPS_CACHED_CCA_SHIFT 4 197 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 198 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 199 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 200 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 201 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 202 #define MIPS_NOT_SUPP 0x8000 203 204 #endif /* !_LOCORE */ 205 206 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1) || defined(_LOCORE) 207 208 #if defined(MIPS1) 209 210 # define CPUISMIPS3 0 211 # define CPUIS64BITS 0 212 # define CPUISMIPS32 0 213 # define CPUISMIPS64 0 214 # define CPUISMIPSNN 0 215 # define MIPS_HAS_R4K_MMU 0 216 # define MIPS_HAS_CLOCK 0 217 # define MIPS_HAS_LLSC 0 218 219 #elif defined(MIPS3) || defined(MIPS4) 220 221 # define CPUISMIPS3 1 222 # define CPUIS64BITS 1 223 # define CPUISMIPS32 0 224 # define CPUISMIPS64 0 225 # define CPUISMIPSNN 0 226 # define MIPS_HAS_R4K_MMU 1 227 # define MIPS_HAS_CLOCK 1 228 # if defined(_LOCORE) 229 # if !defined(MIPS3_5900) && !defined(MIPS3_4100) 230 # define MIPS_HAS_LLSC 1 231 # else 232 # define MIPS_HAS_LLSC 0 233 # endif 234 # else /* _LOCORE */ 235 # define MIPS_HAS_LLSC (mips_has_llsc) 236 # endif /* _LOCORE */ 237 238 #elif defined(MIPS32) 239 240 # define CPUISMIPS3 1 241 # define CPUIS64BITS 0 242 # define CPUISMIPS32 1 243 # define CPUISMIPS64 0 244 # define CPUISMIPSNN 1 245 # define MIPS_HAS_R4K_MMU 1 246 # define MIPS_HAS_CLOCK 1 247 # define MIPS_HAS_LLSC 1 248 249 #elif defined(MIPS64) 250 251 # define CPUISMIPS3 1 252 # define CPUIS64BITS 1 253 # define CPUISMIPS32 0 254 # define CPUISMIPS64 1 255 # define CPUISMIPSNN 1 256 # define MIPS_HAS_R4K_MMU 1 257 # define MIPS_HAS_CLOCK 1 258 # define MIPS_HAS_LLSC 1 259 260 #endif 261 262 #else /* run-time test */ 263 264 #ifndef _LOCORE 265 266 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 267 #define MIPS_HAS_LLSC (mips_has_llsc) 268 269 /* This test is ... rather bogus */ 270 #define CPUISMIPS3 ((cpu_arch & \ 271 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 272 273 /* And these aren't much better while the previous test exists as is... */ 274 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 275 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 276 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 277 #define CPUIS64BITS ((cpu_arch & \ 278 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 279 280 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 281 282 #else /* !_LOCORE */ 283 284 #define MIPS_HAS_LLSC 0 285 286 #endif /* !_LOCORE */ 287 288 #endif /* run-time test */ 289 290 #ifndef _LOCORE 291 292 /* 293 * definitions of cpu-dependent requirements 294 * referenced in generic code 295 */ 296 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 297 298 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 299 300 /* 301 * Arguments to hardclock and gatherstats encapsulate the previous 302 * machine state in an opaque clockframe. 303 */ 304 struct clockframe { 305 int pc; /* program counter at time of interrupt */ 306 int sr; /* status register at time of interrupt */ 307 int ppl; /* previous priority level at time of interrupt */ 308 }; 309 310 /* 311 * A port must provde CLKF_USERMODE() for use in machine-independent code. 312 * These differ on r4000 and r3000 systems; provide them in the 313 * port-dependent file that includes this one, using the macros below. 314 */ 315 316 /* mips1 versions */ 317 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 318 319 /* mips3 versions */ 320 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 321 322 #define CLKF_PC(framep) ((framep)->pc) 323 #define CLKF_INTR(framep) (0) 324 325 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 326 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 327 #endif 328 329 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 330 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 331 #endif 332 333 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 334 #define CLKF_USERMODE(framep) \ 335 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 336 #endif 337 338 /* 339 * This is used during profiling to integrate system time. It can safely 340 * assume that the process is resident. 341 */ 342 #define PROC_PC(p) \ 343 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 344 345 /* 346 * Preempt the current process if in interrupt from user mode, 347 * or after the current trap/syscall if in system mode. 348 */ 349 void cpu_need_resched(struct cpu_info *, int); 350 351 /* 352 * Give a profiling tick to the current process when the user profiling 353 * buffer pages are invalid. On the MIPS, request an ast to send us 354 * through trap, marking the proc as needing a profiling tick. 355 */ 356 #define cpu_need_proftick(l) \ 357 do { \ 358 (l)->l_pflag |= LP_OWEUPC; \ 359 aston(l); \ 360 } while (/*CONSTCOND*/0) 361 362 /* 363 * Notify the current lwp (l) that it has a signal pending, 364 * process as soon as possible. 365 */ 366 #define cpu_signotify(l) aston(l) 367 368 #define aston(l) ((l)->l_md.md_astpending = 1) 369 370 /* 371 * Misc prototypes and variable declarations. 372 */ 373 struct lwp; 374 struct user; 375 376 extern struct segtab *segbase; /* current segtab base */ 377 378 /* trap.c */ 379 void netintr(void); 380 int kdbpeek(vaddr_t); 381 382 /* mips_machdep.c */ 383 void dumpsys(void); 384 int savectx(struct user *); 385 void mips_init_msgbuf(void); 386 void savefpregs(struct lwp *); 387 void loadfpregs(struct lwp *); 388 389 /* locore*.S */ 390 int badaddr(void *, size_t); 391 int badaddr64(uint64_t, size_t); 392 393 /* mips_machdep.c */ 394 void cpu_identify(void); 395 void mips_vector_init(void); 396 397 #endif /* ! _LOCORE */ 398 #endif /* _KERNEL */ 399 #endif /* _CPU_H_ */ 400