1 /* $NetBSD: cpu.h,v 1.72 2004/01/04 11:33:30 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 8.4 (Berkeley) 1/4/94 35 */ 36 37 #ifndef _CPU_H_ 38 #define _CPU_H_ 39 40 #include <mips/cpuregs.h> 41 42 /* 43 * Exported definitions unique to NetBSD/mips cpu support. 44 */ 45 46 #ifdef _KERNEL 47 #ifndef _LOCORE 48 #include <sys/sched.h> 49 50 #if defined(_KERNEL_OPT) 51 #include "opt_lockdebug.h" 52 #endif 53 54 struct cpu_info { 55 struct schedstate_percpu ci_schedstate; /* scheduler state */ 56 u_long ci_cpu_freq; /* CPU frequency */ 57 u_long ci_cycles_per_hz; /* CPU freq / hz */ 58 u_long ci_divisor_delay; /* for delay/DELAY */ 59 u_long ci_divisor_recip; /* scaled reciprocal of previous; 60 see below */ 61 #if defined(DIAGNOSTIC) || defined(LOCKDEBUG) 62 u_long ci_spin_locks; /* # of spin locks held */ 63 u_long ci_simple_locks; /* # of simple locks held */ 64 #endif 65 }; 66 67 /* 68 * To implement a more accurate microtime using the CP0 COUNT register 69 * we need to divide that register by the number of cycles per MHz. 70 * But... 71 * 72 * DIV and DIVU are expensive on MIPS (eg 75 clocks on the R4000). MULT 73 * and MULTU are only 12 clocks on the same CPU. 74 * 75 * The strategy we use is to calculate the reciprical of cycles per MHz, 76 * scaled by 1<<32. Then we can simply issue a MULTU and pluck of the 77 * HI register and have the results of the division. 78 */ 79 #define MIPS_SET_CI_RECIPRICAL(cpu) \ 80 do { \ 81 KASSERT((cpu)->ci_divisor_delay != 0); \ 82 (cpu)->ci_divisor_recip = 0x100000000ULL / (cpu)->ci_divisor_delay; \ 83 } while (0) 84 85 #define MIPS_COUNT_TO_MHZ(cpu, count, res) \ 86 asm volatile("multu %1,%2 ; mfhi %0" \ 87 : "=r"((res)) : "r"((count)), "r"((cpu)->ci_divisor_recip)) 88 89 #endif /* !_LOCORE */ 90 #endif /* _KERNEL */ 91 92 /* 93 * CTL_MACHDEP definitions. 94 */ 95 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 96 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 97 #define CPU_ROOT_DEVICE 3 /* string: root device name */ 98 #define CPU_LLSC 4 /* OS/CPU supports LL/SC instruction */ 99 100 /* 101 * Platform can override, but note this breaks userland compatibility 102 * with other mips platforms. 103 */ 104 #ifndef CPU_MAXID 105 #define CPU_MAXID 5 /* number of valid machdep ids */ 106 107 #define CTL_MACHDEP_NAMES { \ 108 { 0, 0 }, \ 109 { "console_device", CTLTYPE_STRUCT }, \ 110 { "booted_kernel", CTLTYPE_STRING }, \ 111 { "root_device", CTLTYPE_STRING }, \ 112 { "llsc", CTLTYPE_INT }, \ 113 } 114 #endif 115 116 #ifdef _KERNEL 117 #ifndef _LOCORE 118 extern struct cpu_info cpu_info_store; 119 120 #define curcpu() (&cpu_info_store) 121 #define cpu_number() (0) 122 #define cpu_proc_fork(p1, p2) 123 #endif /* !_LOCORE */ 124 125 /* 126 * Macros to find the CPU architecture we're on at run-time, 127 * or if possible, at compile-time. 128 */ 129 130 #define CPU_ARCH_MIPSx 0 /* XXX unknown */ 131 #define CPU_ARCH_MIPS1 (1 << 0) 132 #define CPU_ARCH_MIPS2 (1 << 1) 133 #define CPU_ARCH_MIPS3 (1 << 2) 134 #define CPU_ARCH_MIPS4 (1 << 3) 135 #define CPU_ARCH_MIPS5 (1 << 4) 136 #define CPU_ARCH_MIPS32 (1 << 5) 137 #define CPU_ARCH_MIPS64 (1 << 6) 138 139 #ifndef _LOCORE 140 /* XXX simonb 141 * Should the following be in a cpu_info type structure? 142 * And how many of these are per-cpu vs. per-system? (Ie, 143 * we can assume that all cpus have the same mmu-type, but 144 * maybe not that all cpus run at the same clock speed. 145 * Some SGI's apparently support R12k and R14k in the same 146 * box.) 147 */ 148 extern int cpu_arch; 149 extern int mips_cpu_flags; 150 extern int mips_has_r4k_mmu; 151 extern int mips_has_llsc; 152 extern int mips3_pg_cached; 153 154 #define CPU_MIPS_R4K_MMU 0x0001 155 #define CPU_MIPS_NO_LLSC 0x0002 156 #define CPU_MIPS_CAUSE_IV 0x0004 157 #define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */ 158 #define CPU_MIPS_CACHED_CCA_MASK 0x0070 159 #define CPU_MIPS_CACHED_CCA_SHIFT 4 160 #define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */ 161 #define CPU_MIPS_USE_WAIT 0x0100 /* Use "wait"-based cpu_idle() */ 162 #define CPU_MIPS_NO_WAIT 0x0200 /* Inverse of previous, for mips32/64 */ 163 #define CPU_MIPS_D_CACHE_COHERENT 0x0400 /* D-cache is fully coherent */ 164 #define CPU_MIPS_I_D_CACHE_COHERENT 0x0800 /* I-cache funcs don't need to flush the D-cache */ 165 #define MIPS_NOT_SUPP 0x8000 166 167 #ifdef _LKM 168 /* Assume all CPU architectures are valid for LKM's */ 169 #define MIPS1 1 170 #define MIPS3 1 171 #define MIPS4 1 172 #define MIPS32 1 173 #define MIPS64 1 174 #endif 175 176 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 0 177 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32 or MIPS64 must be specified 178 #endif 179 180 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64) == 1 181 #ifdef MIPS1 182 # define CPUISMIPS3 0 183 # define CPUIS64BITS 0 184 # define CPUISMIPS32 0 185 # define CPUISMIPS64 0 186 # define CPUISMIPSNN 0 187 # define MIPS_HAS_R4K_MMU 0 188 # define MIPS_HAS_CLOCK 0 189 # define MIPS_HAS_LLSC 0 190 #endif /* MIPS1 */ 191 192 #if defined(MIPS3) || defined(MIPS4) 193 # define CPUISMIPS3 1 194 # define CPUIS64BITS 1 195 # define CPUISMIPS32 0 196 # define CPUISMIPS64 0 197 # define CPUISMIPSNN 0 198 # define MIPS_HAS_R4K_MMU 1 199 # define MIPS_HAS_CLOCK 1 200 # define MIPS_HAS_LLSC (mips_has_llsc) 201 #endif /* MIPS3 || MIPS4 */ 202 203 #ifdef MIPS32 204 # define CPUISMIPS3 1 205 # define CPUIS64BITS 0 206 # define CPUISMIPS32 1 207 # define CPUISMIPS64 0 208 # define CPUISMIPSNN 1 209 # define MIPS_HAS_R4K_MMU 1 210 # define MIPS_HAS_CLOCK 1 211 # define MIPS_HAS_LLSC 1 212 #endif /* MIPS32 */ 213 214 #ifdef MIPS64 215 # define CPUISMIPS3 1 216 # define CPUIS64BITS 1 217 # define CPUISMIPS32 0 218 # define CPUISMIPS64 1 219 # define CPUISMIPSNN 1 220 # define MIPS_HAS_R4K_MMU 1 221 # define MIPS_HAS_CLOCK 1 222 # define MIPS_HAS_LLSC 1 223 #endif /* MIPS64 */ 224 225 #else /* run-time test */ 226 227 #define MIPS_HAS_R4K_MMU (mips_has_r4k_mmu) 228 #define MIPS_HAS_LLSC (mips_has_llsc) 229 230 /* This test is ... rather bogus */ 231 #define CPUISMIPS3 ((cpu_arch & \ 232 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 233 234 /* And these aren't much better while the previous test exists as is... */ 235 #define CPUISMIPS32 ((cpu_arch & CPU_ARCH_MIPS32) != 0) 236 #define CPUISMIPS64 ((cpu_arch & CPU_ARCH_MIPS64) != 0) 237 #define CPUISMIPSNN ((cpu_arch & (CPU_ARCH_MIPS32 | CPU_ARCH_MIPS64)) != 0) 238 #define CPUIS64BITS ((cpu_arch & \ 239 (CPU_ARCH_MIPS3 | CPU_ARCH_MIPS4 | CPU_ARCH_MIPS64)) != 0) 240 241 #define MIPS_HAS_CLOCK (cpu_arch >= CPU_ARCH_MIPS3) 242 #endif /* run-time test */ 243 244 /* Shortcut for MIPS3 or above defined */ 245 #if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64) 246 #define MIPS3_PLUS 1 247 #else 248 #undef MIPS3_PLUS 249 #endif 250 251 252 /* 253 * definitions of cpu-dependent requirements 254 * referenced in generic code 255 */ 256 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 257 258 void cpu_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t); 259 260 /* 261 * Arguments to hardclock and gatherstats encapsulate the previous 262 * machine state in an opaque clockframe. 263 */ 264 struct clockframe { 265 int pc; /* program counter at time of interrupt */ 266 int sr; /* status register at time of interrupt */ 267 int ppl; /* previous priority level at time of interrupt */ 268 }; 269 270 /* 271 * A port must provde CLKF_USERMODE() and CLKF_BASEPRI() for use 272 * in machine-independent code. These differ on r4000 and r3000 systems; 273 * provide them in the port-dependent file that includes this one, using 274 * the macros below. 275 */ 276 277 /* mips1 versions */ 278 #define MIPS1_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KU_PREV) 279 #define MIPS1_CLKF_BASEPRI(framep) \ 280 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_ENA_PREV)) == 0) 281 282 /* mips3 versions */ 283 #define MIPS3_CLKF_USERMODE(framep) ((framep)->sr & MIPS_SR_KSU_USER) 284 #define MIPS3_CLKF_BASEPRI(framep) \ 285 ((~(framep)->sr & (MIPS_INT_MASK | MIPS_SR_INT_IE)) == 0) 286 287 #ifdef IPL_ICU_MASK 288 #define ICU_CLKF_BASEPRI(framep) ((framep)->ppl == 0) 289 #endif 290 291 #define CLKF_PC(framep) ((framep)->pc) 292 #define CLKF_INTR(framep) (0) 293 294 #if defined(MIPS3_PLUS) && !defined(MIPS1) /* XXX bogus! */ 295 #define CLKF_USERMODE(framep) MIPS3_CLKF_USERMODE(framep) 296 #define CLKF_BASEPRI(framep) MIPS3_CLKF_BASEPRI(framep) 297 #endif 298 299 #if !defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 300 #define CLKF_USERMODE(framep) MIPS1_CLKF_USERMODE(framep) 301 #define CLKF_BASEPRI(framep) MIPS1_CLKF_BASEPRI(framep) 302 #endif 303 304 #ifdef IPL_ICU_MASK 305 #undef CLKF_BASEPRI 306 #define CLKF_BASEPRI(framep) ICU_CLKF_BASEPRI(framep) 307 #endif 308 309 #if defined(MIPS3_PLUS) && defined(MIPS1) /* XXX bogus! */ 310 #define CLKF_USERMODE(framep) \ 311 ((CPUISMIPS3) ? MIPS3_CLKF_USERMODE(framep): MIPS1_CLKF_USERMODE(framep)) 312 #define CLKF_BASEPRI(framep) \ 313 ((CPUISMIPS3) ? MIPS3_CLKF_BASEPRI(framep): MIPS1_CLKF_BASEPRI(framep)) 314 #endif 315 316 /* 317 * This is used during profiling to integrate system time. It can safely 318 * assume that the process is resident. 319 */ 320 #define PROC_PC(p) \ 321 (((struct frame *)(p)->p_md.md_regs)->f_regs[37]) /* XXX PC */ 322 323 /* 324 * Preempt the current process if in interrupt from user mode, 325 * or after the current trap/syscall if in system mode. 326 */ 327 #define need_resched(ci) \ 328 do { \ 329 want_resched = 1; \ 330 if (curproc != NULL) \ 331 aston(curproc); \ 332 } while (/*CONSTCOND*/0) 333 334 /* 335 * Give a profiling tick to the current process when the user profiling 336 * buffer pages are invalid. On the MIPS, request an ast to send us 337 * through trap, marking the proc as needing a profiling tick. 338 */ 339 #define need_proftick(p) \ 340 do { \ 341 (p)->p_flag |= P_OWEUPC; \ 342 aston(p); \ 343 } while (/*CONSTCOND*/0) 344 345 /* 346 * Notify the current process (p) that it has a signal pending, 347 * process as soon as possible. 348 */ 349 #define signotify(p) aston(p) 350 351 #define aston(p) ((p)->p_md.md_astpending = 1) 352 353 extern int want_resched; /* resched() was called */ 354 355 /* 356 * Misc prototypes and variable declarations. 357 */ 358 struct lwp; 359 struct user; 360 361 extern struct lwp *fpcurlwp; /* the current FPU owner */ 362 extern struct pcb *curpcb; /* the current running pcb */ 363 extern struct segtab *segbase; /* current segtab base */ 364 365 /* trap.c */ 366 void netintr(void); 367 int kdbpeek(vaddr_t); 368 369 /* mips_machdep.c */ 370 void dumpsys(void); 371 int savectx(struct user *); 372 void mips_init_msgbuf(void); 373 void savefpregs(struct lwp *); 374 void loadfpregs(struct lwp *); 375 376 /* locore*.S */ 377 int badaddr(void *, size_t); 378 int badaddr64(uint64_t, size_t); 379 380 /* mips_machdep.c */ 381 void cpu_identify(void); 382 void mips_vector_init(void); 383 384 #endif /* ! _LOCORE */ 385 #endif /* _KERNEL */ 386 #endif /* _CPU_H_ */ 387