xref: /netbsd-src/sys/arch/mips/include/cache_r5k.h (revision 23c8222edbfb0f0932d88a8351d3a0cf817dfb9e)
1 /*	$NetBSD: cache_r5k.h,v 1.1 2003/03/08 04:43:26 rafal Exp $	*/
2 
3 /*
4  * Copyright 2001 Wasabi Systems, Inc.
5  * All rights reserved.
6  *
7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  * 3. All advertising materials mentioning features or use of this software
18  *    must display the following acknowledgement:
19  *	This product includes software developed for the NetBSD Project by
20  *	Wasabi Systems, Inc.
21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22  *    or promote products derived from this software without specific prior
23  *    written permission.
24  *
25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35  * POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 #if defined(_KERNEL) && !defined(_LOCORE)
39 
40 void	r5k_icache_sync_all_32(void);
41 void	r5k_icache_sync_range_32(vaddr_t, vsize_t);
42 void	r5k_icache_sync_range_index_32(vaddr_t, vsize_t);
43 
44 void	r5k_pdcache_wbinv_all_16(void);
45 void	r5k_pdcache_wbinv_all_32(void);
46 void	r4600v1_pdcache_wbinv_range_32(vaddr_t, vsize_t);
47 void	r4600v2_pdcache_wbinv_range_32(vaddr_t, vsize_t);
48 void	vr4131v1_pdcache_wbinv_range_16(vaddr_t, vsize_t);
49 void	r5k_pdcache_wbinv_range_16(vaddr_t, vsize_t);
50 void	r5k_pdcache_wbinv_range_32(vaddr_t, vsize_t);
51 void	r5k_pdcache_wbinv_range_index_16(vaddr_t, vsize_t);
52 void	r5k_pdcache_wbinv_range_index_32(vaddr_t, vsize_t);
53 
54 void	r4600v1_pdcache_inv_range_32(vaddr_t, vsize_t);
55 void	r4600v2_pdcache_inv_range_32(vaddr_t, vsize_t);
56 void	r5k_pdcache_inv_range_16(vaddr_t, vsize_t);
57 void	r5k_pdcache_inv_range_32(vaddr_t, vsize_t);
58 void	r4600v1_pdcache_wb_range_32(vaddr_t, vsize_t);
59 void	r4600v2_pdcache_wb_range_32(vaddr_t, vsize_t);
60 void	r5k_pdcache_wb_range_16(vaddr_t, vsize_t);
61 void	r5k_pdcache_wb_range_32(vaddr_t, vsize_t);
62 
63 void	r5k_enable_sdcache(void);
64 
65 void	r5k_sdcache_wbinv_all(void);
66 void	r5k_sdcache_wbinv_range(vaddr_t, vsize_t);
67 void	r5k_sdcache_wbinv_rangeall(vaddr_t, vsize_t);
68 void	r5k_sdcache_inv_range(vaddr_t, vsize_t);
69 void	r5k_sdcache_wb_range(vaddr_t, vsize_t);
70 
71 #endif /* _KERNEL && !_LOCORE */
72