1 /*- 2 * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #define __INTR_PRIVATE 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(0, "$NetBSD"); 33 34 #include "locators.h" 35 #include "cpunode.h" 36 #include "opt_multiprocessor.h" 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/lwp.h> 42 #include <sys/cpu.h> 43 #include <sys/atomic.h> 44 #include <sys/wdog.h> 45 46 #include <uvm/uvm.h> 47 48 #include <dev/sysmon/sysmonvar.h> 49 50 #include <mips/cache.h> 51 #include <mips/mips_opcode.h> 52 #include <mips/mips3_clock.h> 53 54 #include <mips/cavium/octeonvar.h> 55 #include <mips/cavium/dev/octeon_ciureg.h> 56 #include <mips/cavium/dev/octeon_corereg.h> 57 58 struct cpunode_attach_args { 59 const char *cnaa_name; 60 int cnaa_cpunum; 61 }; 62 63 struct cpunode_softc { 64 device_t sc_dev; 65 device_t sc_wdog_dev; 66 uint64_t sc_fuse; 67 }; 68 69 static int cpunode_mainbus_match(device_t, cfdata_t, void *); 70 static void cpunode_mainbus_attach(device_t, device_t, void *); 71 72 static int cpu_cpunode_match(device_t, cfdata_t, void *); 73 static void cpu_cpunode_attach(device_t, device_t, void *); 74 75 CFATTACH_DECL_NEW(cpunode, sizeof(struct cpunode_softc), 76 cpunode_mainbus_match, cpunode_mainbus_attach, NULL, NULL); 77 78 CFATTACH_DECL_NEW(cpu_cpunode, 0, 79 cpu_cpunode_match, cpu_cpunode_attach, NULL, NULL); 80 81 kcpuset_t *cpus_booted; 82 83 void octeon_reset_vector(void); 84 85 static int 86 cpunode_mainbus_print(void *aux, const char *pnp) 87 { 88 struct cpunode_attach_args * const cnaa = aux; 89 90 if (pnp) 91 aprint_normal("%s", pnp); 92 93 if (cnaa->cnaa_cpunum != CPUNODECF_CORE_DEFAULT) 94 aprint_normal(" core %d", cnaa->cnaa_cpunum); 95 96 return UNCONF; 97 } 98 99 int 100 cpunode_mainbus_match(device_t parent, cfdata_t cf, void *aux) 101 { 102 103 return 1; 104 } 105 106 void 107 cpunode_mainbus_attach(device_t parent, device_t self, void *aux) 108 { 109 struct cpunode_softc * const sc = device_private(self); 110 int cpunum = 0; 111 112 sc->sc_dev = self; 113 sc->sc_fuse = octeon_xkphys_read_8(CIU_FUSE); 114 115 aprint_naive(": %u core%s\n", 116 popcount32((uint32_t)sc->sc_fuse), 117 sc->sc_fuse == 1 ? "" : "s"); 118 119 aprint_normal(": %u core%s", 120 popcount32((uint32_t)sc->sc_fuse), 121 sc->sc_fuse == 1 ? "" : "s"); 122 const uint64_t cvmctl = mips_cp0_cvmctl_read(); 123 aprint_normal(", %scrypto", (cvmctl & CP0_CVMCTL_NOCRYPTO) ? "no " : ""); 124 aprint_normal((cvmctl & CP0_CVMCTL_KASUMI) ? "+kasumi" : ""); 125 aprint_normal(", %s64bit-mul", (cvmctl & CP0_CVMCTL_NOMUL) ? "no " : ""); 126 if (cvmctl & CP0_CVMCTL_REPUN) 127 aprint_normal(", unaligned-access ok"); 128 #ifdef MULTIPROCESSOR 129 uint32_t booted[1]; 130 kcpuset_export_u32(cpus_booted, booted, sizeof(booted)); 131 aprint_normal(", booted %#" PRIx32, booted[0]); 132 #endif 133 aprint_normal("\n"); 134 135 for (uint64_t fuse = sc->sc_fuse; fuse != 0; fuse >>= 1, cpunum++) { 136 struct cpunode_attach_args cnaa = { 137 .cnaa_name = "cpu", 138 .cnaa_cpunum = cpunum, 139 }; 140 config_found(self, &cnaa, cpunode_mainbus_print); 141 } 142 #if NWDOG > 0 143 struct cpunode_attach_args cnaa = { 144 .cnaa_name = "wdog", 145 .cnaa_cpunum = CPUNODECF_CORE_DEFAULT, 146 }; 147 config_found(self, &cnaa, cpunode_mainbus_print); 148 #endif 149 } 150 151 int 152 cpu_cpunode_match(device_t parent, cfdata_t cf, void *aux) 153 { 154 struct cpunode_attach_args * const cnaa = aux; 155 const int cpunum = cf->cf_loc[CPUNODECF_CORE]; 156 157 return strcmp(cnaa->cnaa_name, cf->cf_name) == 0 158 && (cpunum == CPUNODECF_CORE_DEFAULT || cpunum == cnaa->cnaa_cpunum); 159 } 160 161 #if defined(MULTIPROCESSOR) 162 static bool 163 octeon_fixup_cpu_info_references(int32_t load_addr, uint32_t new_insns[2], 164 void *arg) 165 { 166 struct cpu_info * const ci = arg; 167 168 atomic_or_ulong(&curcpu()->ci_flags, CPUF_PRESENT); 169 170 KASSERT(MIPS_KSEG0_P(load_addr)); 171 #ifdef MULTIPROCESSOR 172 KASSERT(!CPU_IS_PRIMARY(curcpu())); 173 #endif 174 load_addr += (intptr_t)ci - (intptr_t)&cpu_info_store; 175 176 KASSERT((intptr_t)ci <= load_addr); 177 KASSERT(load_addr < (intptr_t)(ci + 1)); 178 179 KASSERT(INSN_LUI_P(new_insns[0])); 180 KASSERT(INSN_LOAD_P(new_insns[1]) || INSN_STORE_P(new_insns[1])); 181 182 /* 183 * Use the lui and load/store instruction as a prototype and 184 * make it refer to cpu1_info_store instead of cpu_info_store. 185 */ 186 new_insns[0] &= __BITS(31,16); 187 new_insns[1] &= __BITS(31,16); 188 new_insns[0] |= (uint16_t)((load_addr + 0x8000) >> 16); 189 new_insns[1] |= (uint16_t)load_addr; 190 #ifdef DEBUG_VERBOSE 191 printf("%s: %08x: insn#1 %08x: lui r%u, %d\n", 192 __func__, (int32_t)load_addr, new_insns[0], 193 (new_insns[0] >> 16) & 31, 194 (int16_t)new_insns[0]); 195 printf("%s: %08x: insn#2 %08x: %c%c r%u, %d(r%u)\n", 196 __func__, (int32_t)load_addr, new_insns[0], 197 INSN_LOAD_P(new_insns[1]) ? 'l' : 's', 198 INSN_LW_P(new_insns[1]) ? 'w' : 'd', 199 (new_insns[0] >> 16) & 31, 200 (int16_t)new_insns[1], 201 (new_insns[0] >> 21) & 31); 202 #endif 203 return true; 204 } 205 206 static void 207 octeon_cpu_init(struct cpu_info *ci) 208 { 209 bool ok __diagused; 210 211 // First thing is setup the execption vectors for this cpu. 212 mips64r2_vector_init(&mips_splsw); 213 214 // Next rewrite those exceptions to use this cpu's cpu_info. 215 ok = mips_fixup_exceptions(octeon_fixup_cpu_info_references, ci); 216 KASSERT(ok); 217 218 (void) splhigh(); // make sure interrupts are masked 219 220 KASSERT((mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM) == ci->ci_cpuid); 221 KASSERT(curcpu() == ci); 222 KASSERT(ci->ci_cpl == IPL_HIGH); 223 KASSERT((mips_cp0_status_read() & MIPS_INT_MASK) == 0); 224 } 225 226 static void 227 octeon_cpu_run(struct cpu_info *ci) 228 { 229 octeon_intr_init(ci); 230 231 mips3_initclocks(); 232 KASSERTMSG(ci->ci_cpl == IPL_NONE, "cpl %d", ci->ci_cpl); 233 KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); 234 235 aprint_normal("%s: ", device_xname(ci->ci_dev)); 236 cpu_identify(ci->ci_dev); 237 } 238 #endif /* MULTIPROCESSOR */ 239 240 static void 241 cpu_cpunode_attach_common(device_t self, struct cpu_info *ci) 242 { 243 struct cpu_softc * const cpu __diagused = ci->ci_softc; 244 245 ci->ci_dev = self; 246 self->dv_private = ci; 247 248 KASSERTMSG(cpu != NULL, "ci %p index %d", ci, cpu_index(ci)); 249 250 #if NWDOG > 0 || defined(DDB) 251 void **nmi_vector = (void *)MIPS_PHYS_TO_KSEG0(0x800 + 32*ci->ci_cpuid); 252 *nmi_vector = octeon_reset_vector; 253 254 struct vm_page * const pg = PMAP_ALLOC_POOLPAGE(UVM_PGA_ZERO); 255 KASSERT(pg != NULL); 256 const vaddr_t kva = PMAP_MAP_POOLPAGE(VM_PAGE_TO_PHYS(pg)); 257 KASSERT(kva != 0); 258 ci->ci_nmi_stack = (void *)(kva + PAGE_SIZE - sizeof(struct kernframe)); 259 #endif 260 261 #ifdef WDOG 262 cpu->cpu_wdog_sih = softint_establish(SOFTINT_CLOCK|SOFTINT_MPSAFE, 263 wdog_cpunode_poke, cpu); 264 KASSERT(cpu->cpu_wdog_sih != NULL); 265 #endif 266 267 aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n", 268 ci->ci_cpu_freq / 1000000, 269 (ci->ci_cpu_freq % 1000000) / 10000, 270 ci->ci_cycles_per_hz, ci->ci_divisor_delay); 271 272 if (CPU_IS_PRIMARY(ci)) { 273 aprint_normal("%s: ", device_xname(self)); 274 cpu_identify(self); 275 } 276 cpu_attach_common(self, ci); 277 #ifdef MULTIPROCESSOR 278 KASSERT(cpuid_infos[ci->ci_cpuid] == ci); 279 #endif 280 } 281 282 void 283 cpu_cpunode_attach(device_t parent, device_t self, void *aux) 284 { 285 struct cpunode_attach_args * const cnaa = aux; 286 const int cpunum = cnaa->cnaa_cpunum; 287 288 if (cpunum == 0) { 289 cpu_cpunode_attach_common(self, curcpu()); 290 #ifdef MULTIPROCESSOR 291 mips_locoresw.lsw_cpu_init = octeon_cpu_init; 292 mips_locoresw.lsw_cpu_run = octeon_cpu_run; 293 #endif 294 return; 295 } 296 #ifdef MULTIPROCESSOR 297 KASSERTMSG(cpunum == 1, "cpunum %d", cpunum); 298 if (!kcpuset_isset(cpus_booted, cpunum)) { 299 aprint_naive(" disabled\n"); 300 aprint_normal(" disabled (unresponsive)\n"); 301 return; 302 } 303 struct cpu_info * const ci = cpu_info_alloc(NULL, cpunum, 0, cpunum, 0); 304 305 ci->ci_softc = &octeon_cpu1_softc; 306 ci->ci_softc->cpu_ci = ci; 307 308 cpu_cpunode_attach_common(self, ci); 309 310 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 311 for (int i = 0; i < 100 && !kcpuset_isset(cpus_hatched, cpunum); i++) { 312 delay(10000); 313 } 314 if (!kcpuset_isset(cpus_hatched, cpunum)) { 315 #ifdef DDB 316 aprint_verbose_dev(self, "hatch failed ci=%p flags=%#lx\n", ci, ci->ci_flags); 317 cpu_Debugger(); 318 #endif 319 panic("%s failed to hatch: ci=%p flags=%#lx", 320 cpu_name(ci), ci, ci->ci_flags); 321 } 322 #else 323 aprint_naive(": disabled\n"); 324 aprint_normal(": disabled (uniprocessor kernel)\n"); 325 #endif 326 } 327 328 #if NWDOG > 0 329 struct wdog_softc { 330 struct sysmon_wdog sc_smw; 331 device_t sc_dev; 332 u_int sc_wdog_period; 333 bool sc_wdog_armed; 334 }; 335 336 #ifndef OCTEON_WDOG_PERIOD_DEFAULT 337 #define OCTEON_WDOG_PERIOD_DEFAULT 4 338 #endif 339 340 static int wdog_cpunode_match(device_t, cfdata_t, void *); 341 static void wdog_cpunode_attach(device_t, device_t, void *); 342 343 CFATTACH_DECL_NEW(wdog_cpunode, sizeof(struct wdog_softc), 344 wdog_cpunode_match, wdog_cpunode_attach, NULL, NULL); 345 346 static int 347 wdog_cpunode_setmode(struct sysmon_wdog *smw) 348 { 349 struct wdog_softc * const sc = smw->smw_cookie; 350 351 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 352 if (sc->sc_wdog_armed) { 353 CPU_INFO_ITERATOR cii; 354 struct cpu_info *ci; 355 for (CPU_INFO_FOREACH(cii, ci)) { 356 struct cpu_softc * const cpu = ci->ci_softc; 357 uint64_t wdog = mips3_ld(cpu->cpu_wdog); 358 wdog &= ~CIU_WDOGX_MODE; 359 mips3_sd(cpu->cpu_pp_poke, wdog); 360 aprint_verbose_dev(sc->sc_dev, 361 "%s: disable wdog=%#"PRIx64"\n", 362 cpu_name(ci), wdog); 363 mips3_sd(cpu->cpu_wdog, wdog); 364 mips3_sd(cpu->cpu_pp_poke, wdog); 365 } 366 sc->sc_wdog_armed = false; 367 } 368 } else if (!sc->sc_wdog_armed) { 369 kpreempt_disable(); 370 struct cpu_info *ci = curcpu(); 371 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 372 smw->smw_period = OCTEON_WDOG_PERIOD_DEFAULT; 373 } 374 uint64_t wdog_len = smw->smw_period * ci->ci_cpu_freq; 375 // 376 // This wdog is a 24-bit counter that decrements every 256 377 // cycles. This is then a 32-bit counter so as long wdog_len 378 // doesn't overflow a 32-bit value, we are fine. We write the 379 // 16-bits of the 32-bit period. 380 if ((wdog_len >> 32) != 0) { 381 kpreempt_enable(); 382 return EINVAL; 383 } 384 sc->sc_wdog_period = smw->smw_period; 385 CPU_INFO_ITERATOR cii; 386 for (CPU_INFO_FOREACH(cii, ci)) { 387 struct cpu_softc * const cpu = ci->ci_softc; 388 uint64_t wdog = mips3_ld(cpu->cpu_wdog); 389 wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN); 390 wdog |= __SHIFTIN(3, CIU_WDOGX_MODE); 391 wdog |= __SHIFTIN(wdog_len >> 16, CIU_WDOGX_LEN); 392 aprint_verbose_dev(sc->sc_dev, 393 "%s: enable wdog=%#"PRIx64" (%#"PRIx64")\n", 394 cpu_name(ci), wdog, wdog_len); 395 mips3_sd(cpu->cpu_wdog, wdog); 396 } 397 sc->sc_wdog_armed = true; 398 kpreempt_enable(); 399 } 400 return 0; 401 } 402 403 static void 404 wdog_cpunode_poke(void *arg) 405 { 406 struct cpu_softc *cpu = arg; 407 mips3_sd(cpu->cpu_pp_poke, 0); 408 } 409 410 static int 411 wdog_cpunode_tickle(struct sysmon_wdog *smw) 412 { 413 wdog_cpunode_poke(curcpu()->ci_softc); 414 #ifdef MULTIPROCESSOR 415 // We need to send IPIs to the other CPUs to poke their wdog. 416 cpu_send_ipi(NULL, IPI_WDOG); 417 #endif 418 return 0; 419 } 420 421 int 422 wdog_cpunode_match(device_t parent, cfdata_t cf, void *aux) 423 { 424 struct cpunode_softc * const sc = device_private(parent); 425 struct cpunode_attach_args * const cnaa = aux; 426 const int cpunum = cf->cf_loc[CPUNODECF_CORE]; 427 428 return sc->sc_wdog_dev == NULL 429 && strcmp(cnaa->cnaa_name, cf->cf_name) == 0 430 && cpunum == CPUNODECF_CORE_DEFAULT; 431 } 432 433 void 434 wdog_cpunode_attach(device_t parent, device_t self, void *aux) 435 { 436 struct cpunode_softc * const psc = device_private(parent); 437 struct wdog_softc * const sc = device_private(self); 438 cfdata_t const cf = device_cfdata(self); 439 440 psc->sc_wdog_dev = self; 441 442 sc->sc_dev = self; 443 sc->sc_smw.smw_name = device_xname(self); 444 sc->sc_smw.smw_cookie = sc; 445 sc->sc_smw.smw_setmode = wdog_cpunode_setmode; 446 sc->sc_smw.smw_tickle = wdog_cpunode_tickle; 447 sc->sc_smw.smw_period = OCTEON_WDOG_PERIOD_DEFAULT; 448 sc->sc_wdog_period = sc->sc_smw.smw_period; 449 450 /* 451 * We need one softint per cpu. It's to tickle the softints on 452 * other CPUs. 453 */ 454 CPU_INFO_ITERATOR cii; 455 struct cpu_info *ci; 456 for (CPU_INFO_FOREACH(cii, ci)) { 457 } 458 459 aprint_normal(": default period is %u second%s\n", 460 sc->sc_wdog_period, sc->sc_wdog_period == 1 ? "" : "s"); 461 462 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 463 aprint_error_dev(self, "unable to register with sysmon\n"); 464 return; 465 } 466 467 if (cf->cf_flags & 1) { 468 int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE, 469 sc->sc_wdog_period); 470 if (error) 471 aprint_error_dev(self, 472 "failed to start kernel tickler: %d\n", error); 473 } 474 } 475 #endif /* NWDOG > 0 */ 476