1 /*- 2 * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #define __INTR_PRIVATE 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(0, "$NetBSD"); 33 34 #include "locators.h" 35 #include "cpunode.h" 36 #include "opt_multiprocessor.h" 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/lwp.h> 42 #include <sys/cpu.h> 43 #include <sys/atomic.h> 44 #include <sys/wdog.h> 45 46 #include <uvm/uvm.h> 47 48 #include <dev/sysmon/sysmonvar.h> 49 50 #include <mips/cache.h> 51 #include <mips/mips_opcode.h> 52 #include <mips/mips3_clock.h> 53 54 #include <mips/cavium/octeonvar.h> 55 #include <mips/cavium/dev/octeon_ciureg.h> 56 #include <mips/cavium/dev/octeon_corereg.h> 57 58 struct cpunode_attach_args { 59 const char *cnaa_name; 60 int cnaa_cpunum; 61 }; 62 63 struct cpunode_softc { 64 device_t sc_dev; 65 device_t sc_wdog_dev; 66 uint64_t sc_fuse; 67 }; 68 69 static int cpunode_mainbus_match(device_t, cfdata_t, void *); 70 static void cpunode_mainbus_attach(device_t, device_t, void *); 71 72 static int cpu_cpunode_match(device_t, cfdata_t, void *); 73 static void cpu_cpunode_attach(device_t, device_t, void *); 74 75 CFATTACH_DECL_NEW(cpunode, sizeof(struct cpunode_softc), 76 cpunode_mainbus_match, cpunode_mainbus_attach, NULL, NULL); 77 78 CFATTACH_DECL_NEW(cpu_cpunode, 0, 79 cpu_cpunode_match, cpu_cpunode_attach, NULL, NULL); 80 81 kcpuset_t *cpus_booted; 82 83 void octeon_reset_vector(void); 84 85 static void wdog_cpunode_poke(void *arg); 86 87 static int 88 cpunode_mainbus_print(void *aux, const char *pnp) 89 { 90 struct cpunode_attach_args * const cnaa = aux; 91 92 if (pnp) 93 aprint_normal("%s", pnp); 94 95 if (cnaa->cnaa_cpunum != CPUNODECF_CORE_DEFAULT) 96 aprint_normal(" core %d", cnaa->cnaa_cpunum); 97 98 return UNCONF; 99 } 100 101 int 102 cpunode_mainbus_match(device_t parent, cfdata_t cf, void *aux) 103 { 104 105 return 1; 106 } 107 108 void 109 cpunode_mainbus_attach(device_t parent, device_t self, void *aux) 110 { 111 struct cpunode_softc * const sc = device_private(self); 112 int cpunum = 0; 113 114 sc->sc_dev = self; 115 sc->sc_fuse = octeon_xkphys_read_8(CIU_FUSE); 116 117 aprint_naive(": %u core%s\n", 118 popcount32((uint32_t)sc->sc_fuse), 119 sc->sc_fuse == 1 ? "" : "s"); 120 121 aprint_normal(": %u core%s", 122 popcount32((uint32_t)sc->sc_fuse), 123 sc->sc_fuse == 1 ? "" : "s"); 124 const uint64_t cvmctl = mips_cp0_cvmctl_read(); 125 aprint_normal(", %scrypto", (cvmctl & CP0_CVMCTL_NOCRYPTO) ? "no " : ""); 126 aprint_normal((cvmctl & CP0_CVMCTL_KASUMI) ? "+kasumi" : ""); 127 aprint_normal(", %s64bit-mul", (cvmctl & CP0_CVMCTL_NOMUL) ? "no " : ""); 128 if (cvmctl & CP0_CVMCTL_REPUN) 129 aprint_normal(", unaligned-access ok"); 130 #ifdef MULTIPROCESSOR 131 uint32_t booted[1]; 132 kcpuset_export_u32(cpus_booted, booted, sizeof(booted)); 133 aprint_normal(", booted %#" PRIx32, booted[0]); 134 #endif 135 aprint_normal("\n"); 136 137 for (uint64_t fuse = sc->sc_fuse; fuse != 0; fuse >>= 1, cpunum++) { 138 struct cpunode_attach_args cnaa = { 139 .cnaa_name = "cpu", 140 .cnaa_cpunum = cpunum, 141 }; 142 config_found(self, &cnaa, cpunode_mainbus_print); 143 } 144 #if NWDOG > 0 145 struct cpunode_attach_args cnaa = { 146 .cnaa_name = "wdog", 147 .cnaa_cpunum = CPUNODECF_CORE_DEFAULT, 148 }; 149 config_found(self, &cnaa, cpunode_mainbus_print); 150 #endif 151 } 152 153 int 154 cpu_cpunode_match(device_t parent, cfdata_t cf, void *aux) 155 { 156 struct cpunode_attach_args * const cnaa = aux; 157 const int cpunum = cf->cf_loc[CPUNODECF_CORE]; 158 159 return strcmp(cnaa->cnaa_name, cf->cf_name) == 0 160 && (cpunum == CPUNODECF_CORE_DEFAULT || cpunum == cnaa->cnaa_cpunum); 161 } 162 163 #if defined(MULTIPROCESSOR) 164 static bool 165 octeon_fixup_cpu_info_references(int32_t load_addr, uint32_t new_insns[2], 166 void *arg) 167 { 168 struct cpu_info * const ci = arg; 169 170 atomic_or_ulong(&curcpu()->ci_flags, CPUF_PRESENT); 171 172 KASSERT(MIPS_KSEG0_P(load_addr)); 173 #ifdef MULTIPROCESSOR 174 KASSERT(!CPU_IS_PRIMARY(curcpu())); 175 #endif 176 load_addr += (intptr_t)ci - (intptr_t)&cpu_info_store; 177 178 KASSERT((intptr_t)ci <= load_addr); 179 KASSERT(load_addr < (intptr_t)(ci + 1)); 180 181 KASSERT(INSN_LUI_P(new_insns[0])); 182 KASSERT(INSN_LOAD_P(new_insns[1]) || INSN_STORE_P(new_insns[1])); 183 184 /* 185 * Use the lui and load/store instruction as a prototype and 186 * make it refer to cpu1_info_store instead of cpu_info_store. 187 */ 188 new_insns[0] &= __BITS(31,16); 189 new_insns[1] &= __BITS(31,16); 190 new_insns[0] |= (uint16_t)((load_addr + 0x8000) >> 16); 191 new_insns[1] |= (uint16_t)load_addr; 192 #ifdef DEBUG_VERBOSE 193 printf("%s: %08x: insn#1 %08x: lui r%u, %d\n", 194 __func__, load_addr, new_insns[0], 195 (new_insns[0] >> 16) & 31, 196 (int16_t)new_insns[0]); 197 printf("%s: %08x: insn#2 %08x: %c%c r%u, %d(r%u)\n", 198 __func__, load_addr, new_insns[1], 199 INSN_LOAD_P(new_insns[1]) ? 'l' : 's', 200 INSN_LW_P(new_insns[1]) ? 'w' : 'd', 201 (new_insns[1] >> 16) & 31, 202 (int16_t)new_insns[1], 203 (new_insns[1] >> 21) & 31); 204 #endif 205 return true; 206 } 207 208 static void 209 octeon_cpu_init(struct cpu_info *ci) 210 { 211 bool ok __diagused; 212 213 // First thing is setup the execption vectors for this cpu. 214 mips64r2_vector_init(&mips_splsw); 215 216 // Next rewrite those exceptions to use this cpu's cpu_info. 217 ok = mips_fixup_exceptions(octeon_fixup_cpu_info_references, ci); 218 KASSERT(ok); 219 220 (void) splhigh(); // make sure interrupts are masked 221 222 KASSERT((mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM) == ci->ci_cpuid); 223 KASSERT(curcpu() == ci); 224 KASSERT(ci->ci_cpl == IPL_HIGH); 225 KASSERT((mips_cp0_status_read() & MIPS_INT_MASK) == 0); 226 } 227 228 static void 229 octeon_cpu_run(struct cpu_info *ci) 230 { 231 octeon_intr_init(ci); 232 233 mips3_initclocks(); 234 KASSERTMSG(ci->ci_cpl == IPL_NONE, "cpl %d", ci->ci_cpl); 235 KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); 236 237 aprint_normal("%s: ", device_xname(ci->ci_dev)); 238 cpu_identify(ci->ci_dev); 239 } 240 #endif /* MULTIPROCESSOR */ 241 242 static void 243 cpu_cpunode_attach_common(device_t self, struct cpu_info *ci) 244 { 245 struct cpu_softc * const cpu __diagused = ci->ci_softc; 246 247 ci->ci_dev = self; 248 self->dv_private = ci; 249 250 KASSERTMSG(cpu != NULL, "ci %p index %d", ci, cpu_index(ci)); 251 252 #if NWDOG > 0 || defined(DDB) 253 void **nmi_vector = (void *)MIPS_PHYS_TO_KSEG0(0x800 + 32*ci->ci_cpuid); 254 *nmi_vector = octeon_reset_vector; 255 256 struct vm_page * const pg = PMAP_ALLOC_POOLPAGE(UVM_PGA_ZERO); 257 KASSERT(pg != NULL); 258 const vaddr_t kva = PMAP_MAP_POOLPAGE(VM_PAGE_TO_PHYS(pg)); 259 KASSERT(kva != 0); 260 ci->ci_nmi_stack = (void *)(kva + PAGE_SIZE - sizeof(struct kernframe)); 261 #endif 262 263 #if NWDOG > 0 264 cpu->cpu_wdog_sih = softint_establish(SOFTINT_CLOCK|SOFTINT_MPSAFE, 265 wdog_cpunode_poke, cpu); 266 KASSERT(cpu->cpu_wdog_sih != NULL); 267 #endif 268 269 aprint_normal(": %lu.%02luMHz (hz cycles = %lu, delay divisor = %lu)\n", 270 ci->ci_cpu_freq / 1000000, 271 (ci->ci_cpu_freq % 1000000) / 10000, 272 ci->ci_cycles_per_hz, ci->ci_divisor_delay); 273 274 if (CPU_IS_PRIMARY(ci)) { 275 aprint_normal("%s: ", device_xname(self)); 276 cpu_identify(self); 277 } 278 cpu_attach_common(self, ci); 279 #ifdef MULTIPROCESSOR 280 KASSERT(cpuid_infos[ci->ci_cpuid] == ci); 281 #endif 282 } 283 284 void 285 cpu_cpunode_attach(device_t parent, device_t self, void *aux) 286 { 287 struct cpunode_attach_args * const cnaa = aux; 288 const int cpunum = cnaa->cnaa_cpunum; 289 290 if (cpunum == 0) { 291 cpu_cpunode_attach_common(self, curcpu()); 292 #ifdef MULTIPROCESSOR 293 mips_locoresw.lsw_cpu_init = octeon_cpu_init; 294 mips_locoresw.lsw_cpu_run = octeon_cpu_run; 295 #endif 296 return; 297 } 298 #ifdef MULTIPROCESSOR 299 KASSERTMSG(cpunum == 1, "cpunum %d", cpunum); 300 if (!kcpuset_isset(cpus_booted, cpunum)) { 301 aprint_naive(" disabled\n"); 302 aprint_normal(" disabled (unresponsive)\n"); 303 return; 304 } 305 struct cpu_info * const ci = cpu_info_alloc(NULL, cpunum, 0, cpunum, 0); 306 307 ci->ci_softc = &octeon_cpu1_softc; 308 ci->ci_softc->cpu_ci = ci; 309 310 cpu_cpunode_attach_common(self, ci); 311 312 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 313 for (int i = 0; i < 100 && !kcpuset_isset(cpus_hatched, cpunum); i++) { 314 delay(10000); 315 } 316 if (!kcpuset_isset(cpus_hatched, cpunum)) { 317 #ifdef DDB 318 aprint_verbose_dev(self, "hatch failed ci=%p flags=%#lx\n", ci, ci->ci_flags); 319 cpu_Debugger(); 320 #endif 321 panic("%s failed to hatch: ci=%p flags=%#lx", 322 cpu_name(ci), ci, ci->ci_flags); 323 } 324 #else 325 aprint_naive(": disabled\n"); 326 aprint_normal(": disabled (uniprocessor kernel)\n"); 327 #endif 328 } 329 330 #if NWDOG > 0 331 struct wdog_softc { 332 struct sysmon_wdog sc_smw; 333 device_t sc_dev; 334 u_int sc_wdog_period; 335 bool sc_wdog_armed; 336 }; 337 338 #ifndef OCTEON_WDOG_PERIOD_DEFAULT 339 #define OCTEON_WDOG_PERIOD_DEFAULT 4 340 #endif 341 342 static int wdog_cpunode_match(device_t, cfdata_t, void *); 343 static void wdog_cpunode_attach(device_t, device_t, void *); 344 345 CFATTACH_DECL_NEW(wdog_cpunode, sizeof(struct wdog_softc), 346 wdog_cpunode_match, wdog_cpunode_attach, NULL, NULL); 347 348 static int 349 wdog_cpunode_setmode(struct sysmon_wdog *smw) 350 { 351 struct wdog_softc * const sc = smw->smw_cookie; 352 353 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 354 if (sc->sc_wdog_armed) { 355 CPU_INFO_ITERATOR cii; 356 struct cpu_info *ci; 357 for (CPU_INFO_FOREACH(cii, ci)) { 358 struct cpu_softc * const cpu = ci->ci_softc; 359 uint64_t wdog = mips3_ld(cpu->cpu_wdog); 360 wdog &= ~CIU_WDOGX_MODE; 361 mips3_sd(cpu->cpu_pp_poke, wdog); 362 aprint_verbose_dev(sc->sc_dev, 363 "%s: disable wdog=%#"PRIx64"\n", 364 cpu_name(ci), wdog); 365 mips3_sd(cpu->cpu_wdog, wdog); 366 mips3_sd(cpu->cpu_pp_poke, wdog); 367 } 368 sc->sc_wdog_armed = false; 369 } 370 } else if (!sc->sc_wdog_armed) { 371 kpreempt_disable(); 372 struct cpu_info *ci = curcpu(); 373 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 374 smw->smw_period = OCTEON_WDOG_PERIOD_DEFAULT; 375 } 376 uint64_t wdog_len = smw->smw_period * ci->ci_cpu_freq; 377 // 378 // This wdog is a 24-bit counter that decrements every 256 379 // cycles. This is then a 32-bit counter so as long wdog_len 380 // doesn't overflow a 32-bit value, we are fine. We write the 381 // 16-bits of the 32-bit period. 382 if ((wdog_len >> 32) != 0) { 383 kpreempt_enable(); 384 return EINVAL; 385 } 386 sc->sc_wdog_period = smw->smw_period; 387 CPU_INFO_ITERATOR cii; 388 for (CPU_INFO_FOREACH(cii, ci)) { 389 struct cpu_softc * const cpu = ci->ci_softc; 390 uint64_t wdog = mips3_ld(cpu->cpu_wdog); 391 wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN); 392 wdog |= __SHIFTIN(3, CIU_WDOGX_MODE); 393 wdog |= __SHIFTIN(wdog_len >> 16, CIU_WDOGX_LEN); 394 aprint_verbose_dev(sc->sc_dev, 395 "%s: enable wdog=%#"PRIx64" (%#"PRIx64")\n", 396 cpu_name(ci), wdog, wdog_len); 397 mips3_sd(cpu->cpu_wdog, wdog); 398 } 399 sc->sc_wdog_armed = true; 400 kpreempt_enable(); 401 } 402 return 0; 403 } 404 405 static void 406 wdog_cpunode_poke(void *arg) 407 { 408 struct cpu_softc *cpu = arg; 409 mips3_sd(cpu->cpu_pp_poke, 0); 410 } 411 412 static int 413 wdog_cpunode_tickle(struct sysmon_wdog *smw) 414 { 415 wdog_cpunode_poke(curcpu()->ci_softc); 416 #ifdef MULTIPROCESSOR 417 // We need to send IPIs to the other CPUs to poke their wdog. 418 cpu_send_ipi(NULL, IPI_WDOG); 419 #endif 420 return 0; 421 } 422 423 int 424 wdog_cpunode_match(device_t parent, cfdata_t cf, void *aux) 425 { 426 struct cpunode_softc * const sc = device_private(parent); 427 struct cpunode_attach_args * const cnaa = aux; 428 const int cpunum = cf->cf_loc[CPUNODECF_CORE]; 429 430 return sc->sc_wdog_dev == NULL 431 && strcmp(cnaa->cnaa_name, cf->cf_name) == 0 432 && cpunum == CPUNODECF_CORE_DEFAULT; 433 } 434 435 void 436 wdog_cpunode_attach(device_t parent, device_t self, void *aux) 437 { 438 struct cpunode_softc * const psc = device_private(parent); 439 struct wdog_softc * const sc = device_private(self); 440 cfdata_t const cf = device_cfdata(self); 441 442 psc->sc_wdog_dev = self; 443 444 sc->sc_dev = self; 445 sc->sc_smw.smw_name = device_xname(self); 446 sc->sc_smw.smw_cookie = sc; 447 sc->sc_smw.smw_setmode = wdog_cpunode_setmode; 448 sc->sc_smw.smw_tickle = wdog_cpunode_tickle; 449 sc->sc_smw.smw_period = OCTEON_WDOG_PERIOD_DEFAULT; 450 sc->sc_wdog_period = sc->sc_smw.smw_period; 451 452 /* 453 * We need one softint per cpu. It's to tickle the softints on 454 * other CPUs. 455 */ 456 CPU_INFO_ITERATOR cii; 457 struct cpu_info *ci; 458 for (CPU_INFO_FOREACH(cii, ci)) { 459 } 460 461 aprint_normal(": default period is %u second%s\n", 462 sc->sc_wdog_period, sc->sc_wdog_period == 1 ? "" : "s"); 463 464 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 465 aprint_error_dev(self, "unable to register with sysmon\n"); 466 return; 467 } 468 469 if (cf->cf_flags & 1) { 470 int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE, 471 sc->sc_wdog_period); 472 if (error) 473 aprint_error_dev(self, 474 "failed to start kernel tickler: %d\n", error); 475 } 476 } 477 #endif /* NWDOG > 0 */ 478