1 /*- 2 * Copyright (c) 2014 The NetBSD Foundation, Inc. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to The NetBSD Foundation 6 * by Matt Thomas of 3am Software Foundry. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 #define __INTR_PRIVATE 30 #include <sys/cdefs.h> 31 32 __KERNEL_RCSID(0, "$NetBSD: octeon_cpunode.c,v 1.14 2020/07/17 21:59:30 jmcneill Exp $"); 33 34 #include "locators.h" 35 #include "cpunode.h" 36 #include "opt_multiprocessor.h" 37 #include "opt_ddb.h" 38 39 #include <sys/param.h> 40 #include <sys/device.h> 41 #include <sys/lwp.h> 42 #include <sys/cpu.h> 43 #include <sys/atomic.h> 44 #include <sys/wdog.h> 45 46 #include <uvm/uvm.h> 47 48 #include <dev/sysmon/sysmonvar.h> 49 50 #include <mips/cache.h> 51 #include <mips/mips_opcode.h> 52 #include <mips/mips3_clock.h> 53 54 #include <mips/cavium/octeonvar.h> 55 #include <mips/cavium/dev/octeon_ciureg.h> 56 #include <mips/cavium/dev/octeon_corereg.h> 57 58 extern struct cpu_softc octeon_cpu_softc[]; 59 60 struct cpunode_attach_args { 61 const char *cnaa_name; 62 int cnaa_cpunum; 63 }; 64 65 struct cpunode_softc { 66 device_t sc_dev; 67 device_t sc_wdog_dev; 68 }; 69 70 static int cpunode_mainbus_match(device_t, cfdata_t, void *); 71 static void cpunode_mainbus_attach(device_t, device_t, void *); 72 73 static int cpu_cpunode_match(device_t, cfdata_t, void *); 74 static void cpu_cpunode_attach(device_t, device_t, void *); 75 76 CFATTACH_DECL_NEW(cpunode, sizeof(struct cpunode_softc), 77 cpunode_mainbus_match, cpunode_mainbus_attach, NULL, NULL); 78 79 CFATTACH_DECL_NEW(cpu_cpunode, 0, 80 cpu_cpunode_match, cpu_cpunode_attach, NULL, NULL); 81 82 kcpuset_t *cpus_booted; 83 84 static void wdog_cpunode_poke(void *arg); 85 86 static int 87 cpunode_mainbus_print(void *aux, const char *pnp) 88 { 89 struct cpunode_attach_args * const cnaa = aux; 90 91 if (pnp) 92 aprint_normal("%s", pnp); 93 94 if (cnaa->cnaa_cpunum != CPUNODECF_CORE_DEFAULT) 95 aprint_normal(" core %d", cnaa->cnaa_cpunum); 96 97 return UNCONF; 98 } 99 100 int 101 cpunode_mainbus_match(device_t parent, cfdata_t cf, void *aux) 102 { 103 104 return 1; 105 } 106 107 void 108 cpunode_mainbus_attach(device_t parent, device_t self, void *aux) 109 { 110 struct cpunode_softc * const sc = device_private(self); 111 const uint64_t fuse = octeon_xkphys_read_8(CIU_FUSE); 112 int cpunum = 0; 113 114 sc->sc_dev = self; 115 116 aprint_naive(": %u core%s\n", popcount64(fuse), fuse == 1 ? "" : "s"); 117 aprint_normal(": %u core%s", popcount64(fuse), fuse == 1 ? "" : "s"); 118 119 const uint64_t cvmctl = mips_cp0_cvmctl_read(); 120 aprint_normal(", %scrypto", (cvmctl & CP0_CVMCTL_NOCRYPTO) ? "no " : ""); 121 aprint_normal((cvmctl & CP0_CVMCTL_KASUMI) ? "+kasumi" : ""); 122 aprint_normal(", %s64bit-mul", (cvmctl & CP0_CVMCTL_NOMUL) ? "no " : ""); 123 if (cvmctl & CP0_CVMCTL_REPUN) 124 aprint_normal(", unaligned-access ok"); 125 #ifdef MULTIPROCESSOR 126 uint32_t booted[1]; 127 kcpuset_export_u32(cpus_booted, booted, sizeof(booted)); 128 aprint_normal(", booted %#" PRIx32, booted[0]); 129 #endif 130 aprint_normal("\n"); 131 132 for (uint64_t f = fuse; f != 0; f >>= 1, cpunum++) { 133 struct cpunode_attach_args cnaa = { 134 .cnaa_name = "cpu", 135 .cnaa_cpunum = cpunum, 136 }; 137 config_found(self, &cnaa, cpunode_mainbus_print); 138 } 139 #if NWDOG > 0 140 struct cpunode_attach_args cnaa = { 141 .cnaa_name = "wdog", 142 .cnaa_cpunum = CPUNODECF_CORE_DEFAULT, 143 }; 144 config_found(self, &cnaa, cpunode_mainbus_print); 145 #endif 146 } 147 148 int 149 cpu_cpunode_match(device_t parent, cfdata_t cf, void *aux) 150 { 151 struct cpunode_attach_args * const cnaa = aux; 152 const int cpunum = cf->cf_loc[CPUNODECF_CORE]; 153 154 return strcmp(cnaa->cnaa_name, cf->cf_name) == 0 155 && (cpunum == CPUNODECF_CORE_DEFAULT || cpunum == cnaa->cnaa_cpunum); 156 } 157 158 #if defined(MULTIPROCESSOR) 159 static bool 160 octeon_fixup_cpu_info_references(int32_t load_addr, uint32_t new_insns[2], 161 void *arg) 162 { 163 struct cpu_info * const ci = arg; 164 165 atomic_or_ulong(&curcpu()->ci_flags, CPUF_PRESENT); 166 167 KASSERT(MIPS_KSEG0_P(load_addr)); 168 #ifdef MULTIPROCESSOR 169 KASSERT(!CPU_IS_PRIMARY(curcpu())); 170 #endif 171 load_addr += (intptr_t)ci - (intptr_t)&cpu_info_store; 172 173 KASSERT((intptr_t)ci <= load_addr); 174 KASSERT(load_addr < (intptr_t)(ci + 1)); 175 176 KASSERT(INSN_LUI_P(new_insns[0])); 177 KASSERT(INSN_LOAD_P(new_insns[1]) || INSN_STORE_P(new_insns[1])); 178 179 /* 180 * Use the lui and load/store instruction as a prototype and 181 * make it refer to cpu1_info_store instead of cpu_info_store. 182 */ 183 new_insns[0] &= __BITS(31,16); 184 new_insns[1] &= __BITS(31,16); 185 new_insns[0] |= (uint16_t)((load_addr + 0x8000) >> 16); 186 new_insns[1] |= (uint16_t)load_addr; 187 #ifdef DEBUG_VERBOSE 188 printf("%s: %08x: insn#1 %08x: lui r%u, %d\n", 189 __func__, load_addr, new_insns[0], 190 (new_insns[0] >> 16) & 31, 191 (int16_t)new_insns[0]); 192 printf("%s: %08x: insn#2 %08x: %c%c r%u, %d(r%u)\n", 193 __func__, load_addr, new_insns[1], 194 INSN_LOAD_P(new_insns[1]) ? 'l' : 's', 195 INSN_LW_P(new_insns[1]) ? 'w' : 'd', 196 (new_insns[1] >> 16) & 31, 197 (int16_t)new_insns[1], 198 (new_insns[1] >> 21) & 31); 199 #endif 200 return true; 201 } 202 203 static void 204 octeon_cpu_init(struct cpu_info *ci) 205 { 206 bool ok __diagused; 207 208 // First thing is setup the execption vectors for this cpu. 209 mips64r2_vector_init(&mips_splsw); 210 211 // Next rewrite those exceptions to use this cpu's cpu_info. 212 ok = mips_fixup_exceptions(octeon_fixup_cpu_info_references, ci); 213 KASSERT(ok); 214 215 (void) splhigh(); // make sure interrupts are masked 216 217 KASSERT((mipsNN_cp0_ebase_read() & MIPS_EBASE_CPUNUM) == ci->ci_cpuid); 218 KASSERT(curcpu() == ci); 219 KASSERT(ci->ci_cpl == IPL_HIGH); 220 KASSERT((mips_cp0_status_read() & MIPS_INT_MASK) == 0); 221 } 222 223 static void 224 octeon_cpu_run(struct cpu_info *ci) 225 { 226 octeon_intr_init(ci); 227 228 mips3_initclocks(); 229 KASSERTMSG(ci->ci_cpl == IPL_NONE, "cpl %d", ci->ci_cpl); 230 KASSERT(mips_cp0_status_read() & MIPS_SR_INT_IE); 231 232 aprint_normal("%s: ", device_xname(ci->ci_dev)); 233 cpu_identify(ci->ci_dev); 234 } 235 #endif /* MULTIPROCESSOR */ 236 237 static void 238 cpu_cpunode_attach_common(device_t self, struct cpu_info *ci) 239 { 240 struct cpu_softc * const cpu __diagused = ci->ci_softc; 241 242 ci->ci_dev = self; 243 self->dv_private = ci; 244 245 KASSERTMSG(cpu != NULL, "ci %p index %d", ci, cpu_index(ci)); 246 247 #if NWDOG > 0 || defined(DDB) 248 /* XXXXXX __mips_n32 and MIPS_PHYS_TO_XKPHYS_CACHED needed here?????? */ 249 void **nmi_vector = (void *)MIPS_PHYS_TO_KSEG0(0x800 + 32*ci->ci_cpuid); 250 *nmi_vector = octeon_reset_vector; 251 252 struct vm_page * const pg = PMAP_ALLOC_POOLPAGE(UVM_PGA_ZERO); 253 KASSERT(pg != NULL); 254 const vaddr_t kva = PMAP_MAP_POOLPAGE(VM_PAGE_TO_PHYS(pg)); 255 KASSERT(kva != 0); 256 ci->ci_nmi_stack = (void *)(kva + PAGE_SIZE - sizeof(struct kernframe)); 257 #endif 258 259 #if NWDOG > 0 260 cpu->cpu_wdog_sih = softint_establish(SOFTINT_CLOCK|SOFTINT_MPSAFE, 261 wdog_cpunode_poke, cpu); 262 KASSERT(cpu->cpu_wdog_sih != NULL); 263 #endif 264 265 aprint_normal(": %lu.%02luMHz\n", 266 (ci->ci_cpu_freq + 5000) / 1000000, 267 ((ci->ci_cpu_freq + 5000) % 1000000) / 10000); 268 aprint_debug_dev(self, "hz cycles = %lu, delay divisor = %lu\n", 269 ci->ci_cycles_per_hz, ci->ci_divisor_delay); 270 271 if (CPU_IS_PRIMARY(ci)) { 272 aprint_normal("%s: ", device_xname(self)); 273 cpu_identify(self); 274 } 275 cpu_attach_common(self, ci); 276 #ifdef MULTIPROCESSOR 277 KASSERT(cpuid_infos[ci->ci_cpuid] == ci); 278 #endif 279 } 280 281 void 282 cpu_cpunode_attach(device_t parent, device_t self, void *aux) 283 { 284 struct cpunode_attach_args * const cnaa = aux; 285 const int cpunum = cnaa->cnaa_cpunum; 286 287 if (cpunum == 0) { 288 cpu_cpunode_attach_common(self, curcpu()); 289 #ifdef MULTIPROCESSOR 290 mips_locoresw.lsw_cpu_init = octeon_cpu_init; 291 mips_locoresw.lsw_cpu_run = octeon_cpu_run; 292 #endif 293 return; 294 } 295 #ifdef MULTIPROCESSOR 296 if (!kcpuset_isset(cpus_booted, cpunum)) { 297 aprint_naive(" disabled\n"); 298 aprint_normal(" disabled (unresponsive)\n"); 299 return; 300 } 301 struct cpu_info * const ci = cpu_info_alloc(NULL, cpunum, 0, cpunum, 0); 302 303 ci->ci_softc = &octeon_cpu_softc[cpunum]; 304 ci->ci_softc->cpu_ci = ci; 305 306 cpu_cpunode_attach_common(self, ci); 307 308 KASSERT(ci->ci_data.cpu_idlelwp != NULL); 309 for (int i = 0; i < 100 && !kcpuset_isset(cpus_hatched, cpunum); i++) { 310 delay(10000); 311 } 312 if (!kcpuset_isset(cpus_hatched, cpunum)) { 313 #ifdef DDB 314 aprint_verbose_dev(self, "hatch failed ci=%p flags=%#lx\n", ci, ci->ci_flags); 315 cpu_Debugger(); 316 #endif 317 panic("%s failed to hatch: ci=%p flags=%#lx", 318 cpu_name(ci), ci, ci->ci_flags); 319 } 320 #else 321 aprint_naive(": disabled\n"); 322 aprint_normal(": disabled (uniprocessor kernel)\n"); 323 #endif 324 } 325 326 #if NWDOG > 0 327 struct wdog_softc { 328 struct sysmon_wdog sc_smw; 329 device_t sc_dev; 330 u_int sc_wdog_period; 331 bool sc_wdog_armed; 332 }; 333 334 #ifndef OCTEON_WDOG_PERIOD_DEFAULT 335 #define OCTEON_WDOG_PERIOD_DEFAULT 4 336 #endif 337 338 static int wdog_cpunode_match(device_t, cfdata_t, void *); 339 static void wdog_cpunode_attach(device_t, device_t, void *); 340 341 CFATTACH_DECL_NEW(wdog_cpunode, sizeof(struct wdog_softc), 342 wdog_cpunode_match, wdog_cpunode_attach, NULL, NULL); 343 344 static int 345 wdog_cpunode_setmode(struct sysmon_wdog *smw) 346 { 347 struct wdog_softc * const sc = smw->smw_cookie; 348 349 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 350 if (sc->sc_wdog_armed) { 351 CPU_INFO_ITERATOR cii; 352 struct cpu_info *ci; 353 for (CPU_INFO_FOREACH(cii, ci)) { 354 struct cpu_softc * const cpu = ci->ci_softc; 355 uint64_t wdog = mips3_ld(cpu->cpu_wdog); 356 wdog &= ~CIU_WDOGX_MODE; 357 mips3_sd(cpu->cpu_pp_poke, wdog); 358 aprint_verbose_dev(sc->sc_dev, 359 "%s: disable wdog=%#"PRIx64"\n", 360 cpu_name(ci), wdog); 361 mips3_sd(cpu->cpu_wdog, wdog); 362 mips3_sd(cpu->cpu_pp_poke, wdog); 363 } 364 sc->sc_wdog_armed = false; 365 } 366 } else if (!sc->sc_wdog_armed) { 367 kpreempt_disable(); 368 struct cpu_info *ci = curcpu(); 369 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 370 smw->smw_period = OCTEON_WDOG_PERIOD_DEFAULT; 371 } 372 uint64_t wdog_len = smw->smw_period * ci->ci_cpu_freq; 373 // 374 // This wdog is a 24-bit counter that decrements every 256 375 // cycles. This is then a 32-bit counter so as long wdog_len 376 // doesn't overflow a 32-bit value, we are fine. We write the 377 // 16-bits of the 32-bit period. 378 if ((wdog_len >> 32) != 0) { 379 kpreempt_enable(); 380 return EINVAL; 381 } 382 sc->sc_wdog_period = smw->smw_period; 383 CPU_INFO_ITERATOR cii; 384 for (CPU_INFO_FOREACH(cii, ci)) { 385 struct cpu_softc * const cpu = ci->ci_softc; 386 uint64_t wdog = mips3_ld(cpu->cpu_wdog); 387 wdog &= ~(CIU_WDOGX_MODE|CIU_WDOGX_LEN); 388 wdog |= __SHIFTIN(3, CIU_WDOGX_MODE); 389 wdog |= __SHIFTIN(wdog_len >> 16, CIU_WDOGX_LEN); 390 aprint_verbose_dev(sc->sc_dev, 391 "%s: enable wdog=%#"PRIx64" (%#"PRIx64")\n", 392 cpu_name(ci), wdog, wdog_len); 393 mips3_sd(cpu->cpu_wdog, wdog); 394 } 395 sc->sc_wdog_armed = true; 396 kpreempt_enable(); 397 } 398 return 0; 399 } 400 401 static void 402 wdog_cpunode_poke(void *arg) 403 { 404 struct cpu_softc *cpu = arg; 405 mips3_sd(cpu->cpu_pp_poke, 0); 406 } 407 408 static int 409 wdog_cpunode_tickle(struct sysmon_wdog *smw) 410 { 411 wdog_cpunode_poke(curcpu()->ci_softc); 412 #ifdef MULTIPROCESSOR 413 // We need to send IPIs to the other CPUs to poke their wdog. 414 cpu_send_ipi(NULL, IPI_WDOG); 415 #endif 416 return 0; 417 } 418 419 int 420 wdog_cpunode_match(device_t parent, cfdata_t cf, void *aux) 421 { 422 struct cpunode_softc * const sc = device_private(parent); 423 struct cpunode_attach_args * const cnaa = aux; 424 const int cpunum = cf->cf_loc[CPUNODECF_CORE]; 425 426 return sc->sc_wdog_dev == NULL 427 && strcmp(cnaa->cnaa_name, cf->cf_name) == 0 428 && cpunum == CPUNODECF_CORE_DEFAULT; 429 } 430 431 void 432 wdog_cpunode_attach(device_t parent, device_t self, void *aux) 433 { 434 struct cpunode_softc * const psc = device_private(parent); 435 struct wdog_softc * const sc = device_private(self); 436 cfdata_t const cf = device_cfdata(self); 437 438 psc->sc_wdog_dev = self; 439 440 sc->sc_dev = self; 441 sc->sc_smw.smw_name = device_xname(self); 442 sc->sc_smw.smw_cookie = sc; 443 sc->sc_smw.smw_setmode = wdog_cpunode_setmode; 444 sc->sc_smw.smw_tickle = wdog_cpunode_tickle; 445 sc->sc_smw.smw_period = OCTEON_WDOG_PERIOD_DEFAULT; 446 sc->sc_wdog_period = sc->sc_smw.smw_period; 447 448 /* 449 * We need one softint per cpu. It's to tickle the softints on 450 * other CPUs. 451 */ 452 #if 0 /* XXX unused? */ 453 CPU_INFO_ITERATOR cii; 454 struct cpu_info *ci; 455 for (CPU_INFO_FOREACH(cii, ci)) { 456 } 457 #endif 458 459 aprint_normal(": default period is %u second%s\n", 460 sc->sc_wdog_period, sc->sc_wdog_period == 1 ? "" : "s"); 461 462 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 463 aprint_error_dev(self, "unable to register with sysmon\n"); 464 return; 465 } 466 467 if (cf->cf_flags & 1) { 468 int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE, 469 sc->sc_wdog_period); 470 if (error) 471 aprint_error_dev(self, 472 "failed to start kernel tickler: %d\n", error); 473 } 474 } 475 #endif /* NWDOG > 0 */ 476