xref: /netbsd-src/sys/arch/mips/cavium/dev/octeon_pko.c (revision 181254a7b1bdde6873432bffef2d2decc4b5c22f)
1 /*	$NetBSD: octeon_pko.c,v 1.5 2020/06/23 05:15:33 simonb Exp $	*/
2 
3 /*
4  * Copyright (c) 2007 Internet Initiative Japan, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: octeon_pko.c,v 1.5 2020/06/23 05:15:33 simonb Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <mips/locore.h>
36 #include <mips/cavium/octeonvar.h>
37 #include <mips/cavium/dev/octeon_faureg.h>
38 #include <mips/cavium/dev/octeon_fpareg.h>
39 #include <mips/cavium/dev/octeon_fpavar.h>
40 #include <mips/cavium/dev/octeon_pkoreg.h>
41 #include <mips/cavium/dev/octeon_pkovar.h>
42 
43 static inline void	octpko_op_store(uint64_t, uint64_t);
44 
45 #define	_PKO_RD8(sc, off) \
46 	bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
47 #define	_PKO_WR8(sc, off, v) \
48 	bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
49 
50 /* ----- gloal functions */
51 
52 /* XXX */
53 void
54 octpko_init(struct octpko_attach_args *aa, struct octpko_softc **rsc)
55 {
56 	struct octpko_softc *sc;
57 	int status;
58 
59 	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
60 	if (sc == NULL)
61 		panic("can't allocate memory: %s", __func__);
62 
63 	sc->sc_port = aa->aa_port;
64 	sc->sc_regt = aa->aa_regt;
65 	sc->sc_cmdptr = aa->aa_cmdptr;
66 	sc->sc_cmd_buf_pool = aa->aa_cmd_buf_pool;
67 	sc->sc_cmd_buf_size = aa->aa_cmd_buf_size;
68 
69 	status = bus_space_map(sc->sc_regt, PKO_BASE, PKO_SIZE, 0,
70 	    &sc->sc_regh);
71 	if (status != 0)
72 		panic("can't map %s space", "pko register");
73 
74 	*rsc = sc;
75 }
76 
77 int
78 octpko_enable(struct octpko_softc *sc)
79 {
80 	uint64_t reg_flags;
81 
82 	reg_flags = _PKO_RD8(sc, PKO_REG_FLAGS_OFFSET);
83 	/* PKO_REG_FLAGS_RESET=0 */
84 	/* PKO_REG_FLAGS_STORE_BE=0 */
85 	SET(reg_flags, PKO_REG_FLAGS_ENA_DWB);
86 	SET(reg_flags, PKO_REG_FLAGS_ENA_PKO);
87 	/* XXX */
88 	OCTEON_SYNCW;
89 	_PKO_WR8(sc, PKO_REG_FLAGS_OFFSET, reg_flags);
90 
91 	return 0;
92 }
93 
94 void
95 octpko_config(struct octpko_softc *sc)
96 {
97 	uint64_t reg_cmd_buf = 0;
98 
99 	SET(reg_cmd_buf, __SHIFTIN(sc->sc_cmd_buf_pool, PKO_REG_CMD_BUF_POOL));
100 	SET(reg_cmd_buf, __SHIFTIN(sc->sc_cmd_buf_size, PKO_REG_CMD_BUF_SIZE));
101 	_PKO_WR8(sc, PKO_REG_CMD_BUF_OFFSET, reg_cmd_buf);
102 }
103 
104 int
105 octpko_port_enable(struct octpko_softc *sc, int enable)
106 {
107 	uint64_t reg_read_idx;
108 	uint64_t mem_queue_qos;
109 
110 	reg_read_idx = 0;
111 	SET(reg_read_idx, sc->sc_port & PKO_REG_READ_IDX_IDX);
112 
113 	/* XXX assume one queue maped one port */
114 	/* Enable packet output by enabling all queues for this port */
115 	mem_queue_qos = 0;
116 	SET(mem_queue_qos, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_QOS_PID));
117 	SET(mem_queue_qos, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_QOS_QID));
118 	SET(mem_queue_qos, enable ? PKO_MEM_QUEUE_QOS_QOS_MASK : 0);
119 
120 	_PKO_WR8(sc, PKO_REG_READ_IDX_OFFSET, reg_read_idx);
121 	_PKO_WR8(sc, PKO_MEM_QUEUE_QOS_OFFSET, mem_queue_qos);
122 
123 	return 0;
124 }
125 
126 static int pko_queue_map_init[32];
127 
128 int
129 octpko_port_config(struct octpko_softc *sc)
130 {
131 	paddr_t buf_ptr = 0;
132 	uint64_t mem_queue_ptrs;
133 
134 	KASSERT(sc->sc_port < 32);
135 
136 	buf_ptr = octfpa_load(FPA_COMMAND_BUFFER_POOL);
137 	if (buf_ptr == 0)
138 		return 1;
139 
140 	KASSERT(buf_ptr != 0);
141 
142 	/* assume one queue maped one port */
143 	mem_queue_ptrs = 0;
144 	SET(mem_queue_ptrs, PKO_MEM_QUEUE_PTRS_TAIL);
145 	SET(mem_queue_ptrs, __SHIFTIN(0, PKO_MEM_QUEUE_PTRS_IDX));
146 	SET(mem_queue_ptrs, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_PTRS_PID));
147 	SET(mem_queue_ptrs, __SHIFTIN(sc->sc_port, PKO_MEM_QUEUE_PTRS_QID));
148 	SET(mem_queue_ptrs, __SHIFTIN(0xff, PKO_MEM_QUEUE_PTRS_QOS_MASK));
149 	SET(mem_queue_ptrs, __SHIFTIN(buf_ptr, PKO_MEM_QUEUE_PTRS_BUF_PTR));
150 	OCTEON_SYNCW;
151 	_PKO_WR8(sc, PKO_MEM_QUEUE_PTRS_OFFSET, mem_queue_ptrs);
152 
153 	/*
154 	 * Set initial command buffer address and index
155 	 * for queue.
156 	 */
157 	sc->sc_cmdptr->cmdptr = (uint64_t)buf_ptr;
158 	sc->sc_cmdptr->cmdptr_idx = 0;
159 
160 	pko_queue_map_init[sc->sc_port] = 1;
161 
162 	return 0;
163 }
164