1 /* $NetBSD: octeon_pcmreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * PCM/TDM Registers 31 */ 32 33 #ifndef _OCTEON_PCMREG_H_ 34 #define _OCTEON_PCMREG_H_ 35 36 /* ---- register addresses */ 37 38 #define PCM_CLK0_CFG 0x0001070000010000ULL 39 #define PCM_CLK0_GEN 0x0001070000010008ULL 40 #define PCM0_TDM_CFG 0x0001070000010010ULL 41 #define PCM0_DMA_CFG 0x0001070000010018ULL 42 #define PCM0_INT_ENA 0x0001070000010020ULL 43 #define PCM0_INT_SUM 0x0001070000010028ULL 44 #define PCM0_TDM_DBG 0x0001070000010030ULL 45 #define PCM_CLK0_DBG 0x0001070000010038ULL 46 #define PCM0_TXSTART 0x0001070000010040ULL 47 #define PCM0_TXCNT 0x0001070000010048ULL 48 #define PCM0_TXADDR 0x0001070000010050ULL 49 #define PCM0_RXSTART 0x0001070000010058ULL 50 #define PCM0_RXCNT 0x0001070000010060ULL 51 #define PCM0_RXADDR 0x0001070000010068ULL 52 #define PCM0_TXMSK0 0x0001070000010080ULL 53 #define PCM0_TXMSK1 0x0001070000010088ULL 54 #define PCM0_TXMSK2 0x0001070000010090ULL 55 #define PCM0_TXMSK3 0x0001070000010098ULL 56 #define PCM0_TXMSK4 0x00010700000100a0ULL 57 #define PCM0_TXMSK5 0x00010700000100a8ULL 58 #define PCM0_TXMSK6 0x00010700000100b0ULL 59 #define PCM0_TXMSK7 0x00010700000100b8ULL 60 #define PCM0_RXMSK0 0x00010700000100c0ULL 61 #define PCM0_RXMSK1 0x00010700000100c8ULL 62 #define PCM0_RXMSK2 0x00010700000100d0ULL 63 #define PCM0_RXMSK3 0x00010700000100d8ULL 64 #define PCM0_RXMSK4 0x00010700000100e0ULL 65 #define PCM0_RXMSK5 0x00010700000100e8ULL 66 #define PCM0_RXMSK6 0x00010700000100f0ULL 67 #define PCM0_RXMSK7 0x00010700000100f8ULL 68 69 /* ---- register bits */ 70 71 /* XXX */ 72 73 /* ---- bus_space */ 74 75 #define PCM_BASE_0 0x0001070000010000ULL 76 #define PCM_BASE_1 0x0001070000014000ULL 77 #define PCM_BASE_2 0x0001070000018000ULL 78 #define PCM_BASE_3 0x000107000001c000ULL 79 #define PCM_SIZE 0x0100 80 81 #define PCM_CLKN_CFG_OFFSET 0x0000 82 #define PCM_CLKN_GEN_OFFSET 0x0008 83 #define PCMN_TDM_CFG_OFFSET 0x0010 84 #define PCMN_DMA_CFG_OFFSET 0x0018 85 #define PCMN_INT_ENA_OFFSET 0x0020 86 #define PCMN_INT_SUM_OFFSET 0x0028 87 #define PCMN_TDM_DBG_OFFSET 0x0030 88 #define PCM_CLKN_DBG_OFFSET 0x0038 89 #define PCMN_TXSTART_OFFSET 0x0040 90 #define PCMN_TXCNT_OFFSET 0x0048 91 #define PCMN_TXADDR_OFFSET 0x0050 92 #define PCMN_RXSTART_OFFSET 0x0058 93 #define PCMN_RXCNT_OFFSET 0x0060 94 #define PCMN_RXADDR_OFFSET 0x0068 95 #define PCMN_TXMSK0_OFFSET 0x0080 96 #define PCMN_TXMSK1_OFFSET 0x0088 97 #define PCMN_TXMSK2_OFFSET 0x0090 98 #define PCMN_TXMSK3_OFFSET 0x0098 99 #define PCMN_TXMSK4_OFFSET 0x00a0 100 #define PCMN_TXMSK5_OFFSET 0x00a8 101 #define PCMN_TXMSK6_OFFSET 0x00b0 102 #define PCMN_TXMSK7_OFFSET 0x00b8 103 #define PCMN_RXMSK0_OFFSET 0x00c0 104 #define PCMN_RXMSK1_OFFSET 0x00c8 105 #define PCMN_RXMSK2_OFFSET 0x00d0 106 #define PCMN_RXMSK3_OFFSET 0x00d8 107 #define PCMN_RXMSK4_OFFSET 0x00e0 108 #define PCMN_RXMSK5_OFFSET 0x00e8 109 #define PCMN_RXMSK6_OFFSET 0x00f0 110 #define PCMN_RXMSK7_OFFSET 0x00f8 111 112 #endif /* _OCTEON_PCMREG_H_ */ 113