xref: /netbsd-src/sys/arch/mips/cavium/dev/octeon_ipd.c (revision e7ac2a8b5bd66fa2e050809de09a075c36a7014d)
1 /*	$NetBSD: octeon_ipd.c,v 1.7 2020/06/23 05:15:33 simonb Exp $	*/
2 
3 /*
4  * Copyright (c) 2007 Internet Initiative Japan, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: octeon_ipd.c,v 1.7 2020/06/23 05:15:33 simonb Exp $");
31 
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/mbuf.h>
36 #include <mips/locore.h>
37 #include <mips/cavium/octeonvar.h>
38 #include <mips/cavium/dev/octeon_ciureg.h>
39 #include <mips/cavium/dev/octeon_fpareg.h>
40 #include <mips/cavium/dev/octeon_fpavar.h>
41 #include <mips/cavium/dev/octeon_pipreg.h>
42 #include <mips/cavium/dev/octeon_ipdreg.h>
43 #include <mips/cavium/dev/octeon_ipdvar.h>
44 
45 #include <netinet/in.h>
46 #include <netinet/in_systm.h>
47 #include <netinet/ip.h>
48 
49 #define IP_OFFSET(data, word2) \
50 	((uintptr_t)(data) + (uintptr_t)__SHIFTOUT(word2, PIP_WQE_WORD2_IP_OFFSET))
51 
52 /* XXX */
53 void
54 octipd_init(struct octipd_attach_args *aa, struct octipd_softc **rsc)
55 {
56 	struct octipd_softc *sc;
57 	int status;
58 
59 	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
60 	if (sc == NULL)
61 		panic("can't allocate memory: %s", __func__);
62 
63 	sc->sc_port = aa->aa_port;
64 	sc->sc_regt = aa->aa_regt;
65 	sc->sc_first_mbuff_skip = aa->aa_first_mbuff_skip;
66 	sc->sc_not_first_mbuff_skip = aa->aa_not_first_mbuff_skip;
67 
68 	status = bus_space_map(sc->sc_regt, IPD_BASE, IPD_SIZE, 0,
69 	    &sc->sc_regh);
70 	if (status != 0)
71 		panic("can't map %s space", "ipd register");
72 
73 	*rsc = sc;
74 }
75 
76 #define	_IPD_RD8(sc, off) \
77 	bus_space_read_8((sc)->sc_regt, (sc)->sc_regh, (off))
78 #define	_IPD_WR8(sc, off, v) \
79 	bus_space_write_8((sc)->sc_regt, (sc)->sc_regh, (off), (v))
80 
81 int
82 octipd_enable(struct octipd_softc *sc)
83 {
84 	uint64_t ctl_status;
85 
86 	ctl_status = _IPD_RD8(sc, IPD_CTL_STATUS_OFFSET);
87 	SET(ctl_status, IPD_CTL_STATUS_IPD_EN);
88 	_IPD_WR8(sc, IPD_CTL_STATUS_OFFSET, ctl_status);
89 
90 	return 0;
91 }
92 
93 int
94 octipd_config(struct octipd_softc *sc)
95 {
96 	uint64_t first_mbuff_skip;
97 	uint64_t not_first_mbuff_skip;
98 	uint64_t packet_mbuff_size;
99 	uint64_t first_next_ptr_back;
100 	uint64_t second_next_ptr_back;
101 	uint64_t sqe_fpa_queue;
102 	uint64_t ctl_status;
103 
104 	/* XXX XXX XXX */
105 	first_mbuff_skip = 0;
106 	SET(first_mbuff_skip, (sc->sc_first_mbuff_skip / 8) & IPD_1ST_MBUFF_SKIP_SZ);
107 	_IPD_WR8(sc, IPD_1ST_MBUFF_SKIP_OFFSET, first_mbuff_skip);
108 	/* XXX XXX XXX */
109 
110 	/* XXX XXX XXX */
111 	not_first_mbuff_skip = 0;
112 	SET(not_first_mbuff_skip, (sc->sc_not_first_mbuff_skip / 8) &
113 	    IPD_NOT_1ST_MBUFF_SKIP_SZ);
114 	_IPD_WR8(sc, IPD_NOT_1ST_MBUFF_SKIP_OFFSET, not_first_mbuff_skip);
115 	/* XXX XXX XXX */
116 
117 	packet_mbuff_size = 0;
118 	SET(packet_mbuff_size, (FPA_RECV_PKT_POOL_SIZE / 8) &
119 	    IPD_PACKET_MBUFF_SIZE_MB_SIZE);
120 	_IPD_WR8(sc, IPD_PACKET_MBUFF_SIZE_OFFSET, packet_mbuff_size);
121 
122 	first_next_ptr_back = 0;
123 	SET(first_next_ptr_back, (sc->sc_first_mbuff_skip / 128) & IPD_1ST_NEXT_PTR_BACK_BACK);
124 	_IPD_WR8(sc, IPD_1ST_NEXT_PTR_BACK_OFFSET, first_next_ptr_back);
125 
126 	second_next_ptr_back = 0;
127 	SET(second_next_ptr_back, (sc->sc_not_first_mbuff_skip / 128) &
128 	    IPD_2ND_NEXT_PTR_BACK_BACK);
129 	_IPD_WR8(sc, IPD_2ND_NEXT_PTR_BACK_OFFSET, second_next_ptr_back);
130 
131 	sqe_fpa_queue = 0;
132 	SET(sqe_fpa_queue, FPA_WQE_POOL & IPD_WQE_FPA_QUEUE_WQE_QUE);
133 	_IPD_WR8(sc, IPD_WQE_FPA_QUEUE_OFFSET, sqe_fpa_queue);
134 
135 	ctl_status = _IPD_RD8(sc, IPD_CTL_STATUS_OFFSET);
136 	CLR(ctl_status, IPD_CTL_STATUS_OPC_MODE);
137 	SET(ctl_status,
138 	    __SHIFTIN(IPD_CTL_STATUS_OPC_MODE_ALL, IPD_CTL_STATUS_OPC_MODE));
139 	SET(ctl_status, IPD_CTL_STATUS_PBP_EN);
140 
141 	/*
142 	* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
143 	*          from SDK
144 	* SET(ctl_status, IPD_CTL_STATUS_LEN_M8);
145         * XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
146 	*/
147 
148 	_IPD_WR8(sc, IPD_CTL_STATUS_OFFSET, ctl_status);
149 
150 	return 0;
151 }
152 
153 /*
154  * octeon work queue entry offload
155  * L3 error & L4 error
156  */
157 void
158 octipd_offload(uint64_t word2, void *data, int *rcflags)
159 {
160 	int cflags;
161 
162 	if (ISSET(word2, PIP_WQE_WORD2_IP_NI))
163 		return;
164 
165 	cflags = 0;
166 
167 	if (!ISSET(word2, PIP_WQE_WORD2_IP_V6))
168 		SET(cflags, M_CSUM_IPv4);
169 
170 	if (ISSET(word2, PIP_WQE_WORD2_IP_TU)) {
171 		SET(cflags,
172 		    !ISSET(word2, PIP_WQE_WORD2_IP_V6) ?
173 		    (M_CSUM_TCPv4 | M_CSUM_UDPv4) :
174 		    (M_CSUM_TCPv6 | M_CSUM_UDPv6));
175 	}
176 
177 	/* check L3 (IP) error */
178 	if (ISSET(word2, PIP_WQE_WORD2_IP_IE)) {
179 		struct ip *ip;
180 
181 		switch (word2 & PIP_WQE_WORD2_IP_OPECODE) {
182 		case IPD_WQE_L3_V4_CSUM_ERR:
183 			/* CN31XX Pass 1.1 Errata */
184 			ip = (struct ip *)(IP_OFFSET(data, word2));
185 			if (ip->ip_hl == 5)
186 				SET(cflags, M_CSUM_IPv4_BAD);
187 			break;
188 		default:
189 			break;
190 		}
191 	}
192 
193 	/* check L4 (UDP / TCP) error */
194 	if (ISSET(word2, PIP_WQE_WORD2_IP_LE)) {
195 		switch (word2 & PIP_WQE_WORD2_IP_OPECODE) {
196 		case IPD_WQE_L4_CSUM_ERR:
197 			SET(cflags, M_CSUM_TCP_UDP_BAD);
198 			break;
199 		default:
200 			break;
201 		}
202 	}
203 
204 	*rcflags = cflags;
205 }
206 
207 void
208 octipd_sub_port_fcs(struct octipd_softc *sc, int enable)
209 {
210 	uint64_t sub_port_fcs;
211 
212 	sub_port_fcs = _IPD_RD8(sc, IPD_SUB_PORT_FCS_OFFSET);
213 	if (enable == 0)
214 		CLR(sub_port_fcs, __BIT(sc->sc_port));
215 	else
216 		SET(sub_port_fcs, __BIT(sc->sc_port));
217 	_IPD_WR8(sc, IPD_SUB_PORT_FCS_OFFSET, sub_port_fcs);
218 }
219