1 /* $NetBSD: octeon_corereg.h,v 1.2 2015/06/01 22:55:12 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Internet Initiative Japan, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #ifndef _OCTEON_COREREG_H_ 30 #define _OCTEON_COREREG_H_ 31 32 /* 33 * Core Coprocessor 0 Privileged Registers. 34 */ 35 36 #ifdef _LOCORE 37 #define CP0_INDEX $0 /* Index Register */ 38 #define CP0_RANDOM $1 /* Random Register */ 39 #define CP0_ENTRYLO0 $2 /* EntryLo0 Registers */ 40 #define CP0_ENTRYLO1 $3 /* EntryLo1 Registers */ 41 #define CP0_CONTEXT $4 /* Context Register */ 42 #define CP0_PAGEMASK $5 /* PageMask Register */ 43 #define CP0_PAGEGRAIN $5, 1 /* PageGrain Register */ 44 #define CP0_WIRED $6 /* Wired Register */ 45 #define CP0_HWRENA $7 /* HWREna Register */ 46 #define CP0_BADVADDR $8 /* BadVAddr Register */ 47 #define CP0_COUNT $9 /* Count Register */ 48 #define CP0_ENTRYHI $10 /* EntryHi Register */ 49 #define CP0_COMPARE $11 /* Compare Register */ 50 #define CP0_STATUS $12 /* Status Register */ 51 #define CP0_INTCTL $12, 1 /* IntCtl Register */ 52 #define CP0_SRSCTL $12, 2 /* SRSCtl Register */ 53 #define CP0_CAUSE $13 /* Cause Register */ 54 #define CP0_EPC $14 /* Exception Program Counter */ 55 #define CP0_PRID $15 /* PRId Register */ 56 #define CP0_EBASE $15, 1 /* EBase Register */ 57 #define CP0_CONFIG $16 /* Config Register */ 58 #define CP0_CONFIG1 $16, 1 /* Config1 Register */ 59 #define CP0_CONFIG2 $16, 2 /* Config2 Register */ 60 #define CP0_CONFIG3 $16, 3 /* Config3 Register */ 61 #define CP0_WATCHLO $18 /* WatchLo Register */ 62 #define CP0_WATCHLO1 $18, 1 63 #define CP0_WATCHHI $19 /* WatchHi Register */ 64 #define CP0_WATCHHI1 $19, 1 65 #define CP0_XCONTEXT $20 /* XContext Register */ 66 #define CP0_DEBUG $23 /* Debug Register */ 67 #define CP0_DPC $24 /* Debug Exception Program Counter Register */ 68 #define CP0_PCCTL $25 /* Performance Counter Control Register */ 69 #define CP0_PCCTL1 $25, 2 70 #define CP0_PCCNT $25, 1 /* Performance Counter Counter Register */ 71 #define CP0_PCCNT1 $25, 3 72 #define CP0_ERROREPC $30 /* ErrorEPC */ 73 #define CP0_DESAVE $31 /* DESAVE Register */ 74 #define CP0_CACHEERRI $27 /* CacheErr (Icache) */ 75 #define CP0_CACHEERRD $27, 1 /* CacheErr (Dcache) */ 76 #define CP0_TAGLOI $28 /* TagLo Register (Icache) */ 77 #define CP0_TAGLOD $28, 2 /* TagLo Register (Dcache) */ 78 #define CP0_DATALOI $28, 1 /* DataLo Register (Icache) */ 79 #define CP0_DATALOD $28, 3 /* DataLo Register (Dcache) */ 80 #define CP0_TAGHI $29, 2 /* TagHi Register */ 81 #define CP0_DATAHII $29, 1 /* DataHi Register (Icache) */ 82 #define CP0_DATAHID $29, 3 /* DataHi Register (Dcache) */ 83 #define CP0_CVMCTL $9, 7 /* CvmCtl Register */ 84 #define CP0_CVMMEMCTL $11, 7 /* CvmMemCtl Register */ 85 #define CP0_CVMCNT $9, 6 /* CvmCount Register */ 86 #define CP0_MCD $22 /* Multi-Core Debug Register */ 87 #endif 88 89 /* ---- register bits */ 90 91 /* Index Register */ 92 93 #define CP0_INDEX_P UINT32_C(0x80000000) 94 #define CP0_INDEX_XXX_30_5 0x7fffffe0 95 #define CP0_INDEX_INDEX 0x0000001f 96 97 /* Random Register */ 98 99 #define CP0_RANDOM_XXX_31_5 0xffffffe0 100 #define CP0_RANDOM_RANDOM 0x0000001f 101 102 /* EntryLo0, EntryLo1 Registers */ 103 104 #define CP0_ENTRYLON_FILL UINT64_C(0xfffff80000000000) 105 #define CP0_ENTRYLON_PFNX UINT64_C(0x000007ffc0000000) 106 #define CP0_ENTRYLON_PFN UINT64_C(0x000000003fffffc0) 107 #define CP0_ENTRYLON_C UINT64_C(0x0000000000000038) 108 #define CP0_ENTRYLON_D UINT64_C(0x0000000000000004) 109 #define CP0_ENTRYLON_V UINT64_C(0x0000000000000002) 110 #define CP0_ENTRYLON_G UINT64_C(0x0000000000000001) 111 112 /* Context Register */ 113 114 #define CP0_CONTEXT_PTEBASE UINT64_C(0xffffffffff800000) 115 #define CP0_CONTEXT_BADVPN2 UINT64_C(0x00000000007ffff0) 116 #define CP0_CONTEXT_XXX_3_0 UINT64_C(0x000000000000000f) 117 118 /* PageMask Register */ 119 120 #define CP0_PAGEMASK_XXX_31_29 UINT64_C(0xe000000000000000) 121 #define CP0_PAGEMASK_MASK UINT64_C(0x1fffffffffffe000) 122 #define CP0_PAGEMASK_MASKX UINT64_C(0x0000000000001800) 123 #define CP0_PAGEMASK_XXX_10_0 UINT64_C(0x0000000000000fff) 124 125 /* PageGrain Register */ 126 127 #define CP0_PAGEGRAIN_ASE 0xc0000000 128 #define CP0_PAGEGRAIN_ELPA UINT32_C(0x20000000) 129 #define CP0_PAGEGRAIN_ESP UINT32_C(0x10000000) 130 #define CP0_PAGEGRAIN_XXX_27_13 0x0fffe000 131 #define CP0_PAGEGRAIN_XXX_7_0 0x000000ff 132 133 /* Wired Register */ 134 135 #define CP0_WIRED_XXX_31_5 UINT64_C(0xffffffffffffffe0) 136 #define CP0_WIRED_WIRED UINT64_C(0x000000000000001f) 137 138 /* HWREna Register */ 139 140 #define CP0_HWRENA_MASKX 0xc0000000 141 #define CP0_HWRENA_XXX_29_4 0x3ffffff0 142 #define CP0_HWRENA_MASK 0x0000000f 143 144 /* BadVAddr Register */ 145 146 /* Count Register */ 147 148 /* EntryHi Register */ 149 150 #define CP0_ENTRYHI_R UINT64_C(0xc000000000000000) 151 #define CP0_ENTRYHI_FILL UINT64_C(0x3ffe000000000000) 152 #define CP0_ENTRYHI_VPN2 UINT64_C(0x0001ffffffffe000) 153 #define CP0_ENTRYHI_VPN2X UINT64_C(0x0000000000001800) 154 #define CP0_ENTRYHI_XXX_10_8 UINT64_C(0x0000000000000700) 155 #define CP0_ENTRYHI_ASID UINT64_C(0x00000000000000ff) 156 157 /* Compare Register */ 158 159 /* Status Register */ 160 161 #define CP0_STATUS_CU3 UINT32_C(0x80000000) 162 #define CP0_STATUS_CU2 UINT32_C(0x40000000) 163 #define CP0_STATUS_CU1 UINT32_C(0x20000000) 164 #define CP0_STATUS_CU0 UINT32_C(0x10000000) 165 #define CP0_STATUS_RP UINT32_C(0x08000000) 166 #define CP0_STATUS_FR UINT32_C(0x04000000) 167 #define CP0_STATUS_RE UINT32_C(0x02000000) 168 #define CP0_STATUS_MX UINT32_C(0x01000000) 169 #define CP0_STATUS_PX UINT32_C(0x00800000) 170 #define CP0_STATUS_BEV UINT32_C(0x00400000) 171 #define CP0_STATUS_TS UINT32_C(0x00200000) 172 #define CP0_STATUS_SR UINT32_C(0x00100000) 173 #define CP0_STATUS_NMI UINT32_C(0x00080000) 174 #define CP0_STATUS_XXX_18_16 0x00070000 175 #define CP0_STATUS_IM_7_4 0x0000fc00 176 #define CP0_STATUS_IM_1_0 0x00000300 177 #define CP0_STATUS_KX UINT32_C(0x00000080) 178 #define CP0_STATUS_SX UINT32_C(0x00000040) 179 #define CP0_STATUS_UX UINT32_C(0x00000020) 180 #define CP0_STATUS_KSU 0x00000018 181 #define CP0_STATUS_ERL UINT32_C(0x00000004) 182 #define CP0_STATUS_EXL UINT32_C(0x00000002) 183 #define CP0_STATUS_IE UINT32_C(0x00000001) 184 185 /* IntCtl Register */ 186 187 #define CP0_INTCTL_IPTI 0xe0000000 188 #define CP0_INTCTL_IPPCI 0x1c000000 189 #define CP0_INTCTL_XXX_25_10 0x03fffc00 190 #define CP0_INTCTL_VS 0x000003e0 191 #define CP0_INTCTL_XXX_4_0 0x0000001f 192 193 /* SRSCtl Register */ 194 195 #define CP0_SRSCTL_XXX_31_30 0xc0000000 196 #define CP0_SRSCTL_HSS 0x3c000000 197 #define CP0_SRSCTL_XXX_25_22 0x03c00000 198 #define CP0_SRSCTL_EICSS 0x003c0000 199 #define CP0_SRSCTL_XXX_17_16 0x00030000 200 #define CP0_SRSCTL_ESS 0x0000f000 201 #define CP0_SRSCTL_XXX_11_10 0x00000c00 202 #define CP0_SRSCTL_EXL 0x000003c0 203 #define CP0_SRSCTL_XXX_5_4 0x00000030 204 #define CP0_SRSCTL_CSS 0x0000000f 205 206 /* Cause Register */ 207 208 #define CP0_CAUSE_BD UINT32_C(0x80000000) 209 #define CP0_CAUSE_TI UINT32_C(0x40000000) 210 #define CP0_CAUSE_CE 0x30000000 211 #define CP0_CAUSE_DC UINT32_C(0x08000000) 212 #define CP0_CAUSE_PCI UINT32_C(0x04000000) 213 #define CP0_CAUSE_XXX_25_24 0x03000000 214 #define CP0_CAUSE_IV UINT32_C(0x00800000) 215 #define CP0_CAUSE_WP UINT32_C(0x00400000) 216 #define CP0_CAUSE_XXX_21_16 0x003f0000 217 #define CP0_CAUSE_IP_7_4 0x0000f000 218 #define CP0_CAUSE_IP_3_2 0x00000c00 219 #define CP0_CAUSE_IP_1_0 0x00000300 220 #define CP0_CAUSE_XXX_7 UINT32_C(0x00000080) 221 #define CP0_CAUSE_EXCCODE 0x0000007c 222 #define CP0_CAUSE_XXX_1_0 0x00000003 223 224 /* Exception Program Counter */ 225 226 /* PRId Register */ 227 228 #define CP0_PRID_COMPANY_OPTIONS 0xff000000 229 #define CP0_PRID_COMPANY_ID 0x00ff0000 230 #define CP0_PRID_PROCESSOR_ID 0x0000ff00 231 #define CP0_PRID_REVISION 0x000000ff 232 233 /* EBase Register */ 234 235 #define CP0_EBASE_ALWAYS UINT32_C(0x80000000) 236 #define CP0_EBASE_XXX_30 UINT32_C(0x40000000) 237 #define CP0_EBASE_EXCEPTION_BASE 0x3ffff000 238 #define CP0_EBASE_XXX_11_10 0x00000c00 239 #define CP0_EBASE_CPU_NUM 0x000003ff 240 241 /* Config Register */ 242 243 #define CP0_CONFIG_M UINT32_C(0x80000000) 244 #define CP0_CONFIG_IMPL 0x7fff0000 245 #define CP0_CONFIG_BE UINT32_C(0x00008000) 246 #define CP0_CONFIG_AT 0x00006000 247 #define CP0_CONFIG_AR 0x00001c00 248 #define CP0_CONFIG_MT 0x00000380 249 #define CP0_CONFIG_XXX_6_4 0x00000070 250 #define CP0_CONFIG_VI UINT32_C(0x00000008) 251 #define CP0_CONFIG_KO 0x00000007 252 253 /* Config1 Register */ 254 255 #define CP0_CONFIG1_M UINT32_C(0x10000000) 256 #define CP0_CONFIG1_MMUSIZE_1 0x7e000000 257 #define CP0_CONFIG1_IS 0x01c00000 258 #define CP0_CONFIG1_IL 0x00380000 259 #define CP0_CONFIG1_IA 0x00070000 260 #define CP0_CONFIG1_DS 0x0000e000 261 #define CP0_CONFIG1_DL 0x00001c00 262 #define CP0_CONFIG1_DA 0x00000380 263 #define CP0_CONFIG1_C2 UINT32_C(0x00000040) 264 #define CP0_CONFIG1_MD UINT32_C(0x00000020) 265 #define CP0_CONFIG1_PC UINT32_C(0x00000010) 266 #define CP0_CONFIG1_WR UINT32_C(0x00000008) 267 #define CP0_CONFIG1_CA UINT32_C(0x00000004) 268 #define CP0_CONFIG1_EP UINT32_C(0x00000002) 269 #define CP0_CONFIG1_FP UINT32_C(0x00000001) 270 271 /* Config2 Register */ 272 273 #define CP0_CONFIG2_M UINT32_C(0x80000000) 274 #define CP0_CONFIG2_TU 0x70000000 275 #define CP0_CONFIG2_TS 0x0f000000 276 #define CP0_CONFIG2_TL 0x00f00000 277 #define CP0_CONFIG2_TA 0x000f0000 278 #define CP0_CONFIG2_SU 0x0000f000 279 #define CP0_CONFIG2_SS 0x00000f00 280 #define CP0_CONFIG2_SL 0x000000f0 281 #define CP0_CONFIG2_SA 0x0000000f 282 283 /* Config3 Register */ 284 285 #define CP0_CONFIG3_M UINT32_C(0x80000000) 286 #define CP0_CONFIG3_XXX_30_8 0x7fffff00 287 #define CP0_CONFIG3_LPA UINT32_C(0x00000080) 288 #define CP0_CONFIG3_VEIC UINT32_C(0x00000040) 289 #define CP0_CONFIG3_VINT UINT32_C(0x00000020) 290 #define CP0_CONFIG3_SP UINT32_C(0x00000010) 291 #define CP0_CONFIG3_XXX_3_2 0x0000000c 292 #define CP0_CONFIG3_SM UINT32_C(0x00000002) 293 #define CP0_CONFIG3_TL UINT32_C(0x00000001) 294 295 /* WatchLo Register */ 296 297 #define CP0_WATCHLO_VADDR UINT64_C(0xfffffffffffffff8) 298 #define CP0_WATCHLO_I UINT64_C(0x0000000000000004) 299 #define CP0_WATCHLO_R UINT64_C(0x0000000000000002) 300 #define CP0_WATCHLO_W UINT64_C(0x0000000000000001) 301 302 /* WatchHi Register */ 303 304 #define CP0_WATCHHI_M UINT32_C(0x80000000) 305 #define CP0_WATCHHI_G UINT32_C(0x40000000) 306 #define CP0_WATCHHI_XXX_29_24 0x3f000000 307 #define CP0_WATCHHI_ASID 0x00ff0000 308 #define CP0_WATCHHI_XXX_15_12 0x0000f000 309 #define CP0_WATCHHI_MASK 0x00000ff8 310 #define CP0_WATCHHI_I UINT32_C(0x00000004) 311 #define CP0_WATCHHI_R UINT32_C(0x00000002) 312 #define CP0_WATCHHI_W UINT32_C(0x00000001) 313 314 /* XContext Register */ 315 316 #define CP0_XCONTEXT_PTEBASE UINT64_C(0xfffffc0000000000) 317 #define CP0_XCONTEXT_R UINT64_C(0x0000030000000000) 318 #define CP0_XCONTEXT_BADVPN2 UINT64_C(0x000000fffffffff0) 319 #define CP0_XCONTEXT_XXX_3_0 UINT64_C(0x000000000000000f) 320 321 /* Debug Register */ 322 323 #define CP0_DEBUG_DBD UINT32_C(0x80000000) 324 #define CP0_DEBUG_DM UINT32_C(0x40000000) 325 #define CP0_DEBUG_NODCR UINT32_C(0x20000000) 326 #define CP0_DEBUG_LSNM UINT32_C(0x10000000) 327 #define CP0_DEBUG_DOZE UINT32_C(0x08000000) 328 #define CP0_DEBUG_HALT UINT32_C(0x04000000) 329 #define CP0_DEBUG_COUNTDM UINT32_C(0x02000000) 330 #define CP0_DEBUG_IBUSEP UINT32_C(0x01000000) 331 #define CP0_DEBUG_MCHECKP UINT32_C(0x00800000) 332 #define CP0_DEBUG_CACHEEP UINT32_C(0x00400000) 333 #define CP0_DEBUG_DBUSEP UINT32_C(0x00200000) 334 #define CP0_DEBUG_IEXI UINT32_C(0x00100000) 335 #define CP0_DEBUG_DDBSIMPR UINT32_C(0x00080000) 336 #define CP0_DEBUG_DDBLIMPR UINT32_C(0x00040000) 337 #define CP0_DEBUG_EJTAG 0x00038000 338 #define CP0_DEBUG_DEXCCODE 0x00007c00 339 #define CP0_DEBUG_NOSST UINT32_C(0x00000200) 340 #define CP0_DEBUG_SST UINT32_C(0x00000100) 341 #define CP0_DEBUG_XXX_7_6 0x000000c0 342 #define CP0_DEBUG_DINT UINT32_C(0x00000020) 343 #define CP0_DEBUG_DIB UINT32_C(0x00000010) 344 #define CP0_DEBUG_DDBS UINT32_C(0x00000008) 345 #define CP0_DEBUG_DDBL UINT32_C(0x00000004) 346 #define CP0_DEBUG_DBP UINT32_C(0x00000002) 347 #define CP0_DEBUG_DSS UINT32_C(0x00000001) 348 349 /* Debug Exception Program Counter Register */ 350 351 /* Performance Counter Control Register */ 352 353 #define CP0_PCCTL_M UINT32_C(0x80000000) 354 #define CP0_PCCTL_W UINT32_C(0x40000000) 355 #define CP0_PCCTL_XXX_29_11 0x3ffff800 356 #define CP0_PCCTL_EVENT 0x000007e0 357 #define CP0_PCCTL_IE UINT32_C(0x00000010) 358 #define CP0_PCCTL_U UINT32_C(0x00000008) 359 #define CP0_PCCTL_S UINT32_C(0x00000004) 360 #define CP0_PCCTL_K UINT32_C(0x00000002) 361 #define CP0_PCCTL_EXL UINT32_C(0x00000001) 362 363 /* Performance Counter Counter Register */ 364 365 /* ErrorEPC */ 366 367 /* DESAVE Register */ 368 369 /* 370 * Cavium Networks-Specific Coprocessor 0 Register 371 */ 372 373 /* CacheErr (Icache) */ 374 375 #define CP0_CACHEERRI_XXX_63_55 UINT64_C(0xff80000000000000) 376 #define CP0_CACHEERRI_BADCOLF UINT64_C(0x007f000000000000) 377 #define CP0_CACHEERRI_XXX_47 UINT64_C(0x0000800000000000) 378 #define CP0_CACHEERRI_BADCOL UINT64_C(0x00007f0000000000) 379 #define CP0_CACHEERRI_XXX_39_37 UINT64_C(0x000000e000000000) 380 #define CP0_CACHEERRI_LRUFAIL UINT64_C(0x0000001000000000) 381 #define CP0_CACHEERRI_AESFAIL UINT64_C(0x0000000800000000) 382 #define CP0_CACHEERRI_HSHFAIL UINT64_C(0x0000000400000000) 383 #define CP0_CACHEERRI_BHTBROKE UINT64_C(0x0000000200000000) 384 #define CP0_CACHEERRI_ICBROKE UINT64_C(0x0000000100000000) 385 #define CP0_CACHEERRI_XXX_31_15 UINT64_C(0x00000000ffff8000) 386 #define CP0_CACHEERRI_QW UINT64_C(0x0000000000006000) 387 #define CP0_CACHEERRI_ROW UINT64_C(0x0000000000001800) 388 #define CP0_CACHEERRI_SET UINT64_C(0x00000000000007e0) 389 #define CP0_CACHEERRI_WAY UINT64_C(0x0000000000000018) 390 #define CP0_CACHEERRI_XXX_2_1 UINT64_C(0x0000000000000006) 391 #define CP0_CACHEERRI_DPERR UINT64_C(0x0000000000000001) 392 393 /* CacheErr (Dcache) */ 394 395 #define CP0_CACHEERRD_XXX_63_13 UINT64_C(0xffffffffffffe000) 396 #define CP0_CACHEERRD_SET UINT64_C(0x0000000000001f80) 397 #define CP0_CACHEERRD_VA63 UINT64_C(0x0000000000000078) 398 #define CP0_CACHEERRD_XXX_2_1 UINT64_C(0x0000000000000006) 399 #define CP0_CACHEERRD_PERR UINT64_C(0x0000000000000001) 400 401 /* TagLo Register (Icache) */ 402 403 #define CP0_TAGLOI_R UINT64_C(0xc000000000000000) 404 #define CP0_TAGLOI_XXX_61_60 UINT64_C(0x3000000000000000) 405 #define CP0_TAGLOI_ASID UINT64_C(0x0f00000000000000) 406 #define CP0_TAGLOI_XXX_51_49 UINT64_C(0x00f0000000000000) 407 #define CP0_TAGLOI_TAG UINT64_C(0x000fffffffffe000) 408 #define CP0_TAGLOI_INDEX UINT64_C(0x0000000000001f80) 409 #define CP0_TAGLOI_XXX_6_2 UINT64_C(0x000000000000007c) 410 #define CP0_TAGLOI_G UINT64_C(0x0000000000000002) 411 #define CP0_TAGLOI_VALID UINT64_C(0x0000000000000001) 412 413 /* TagLo Register (Dcache) */ 414 415 #define CP0_TAGLOD_R UINT64_C(0xc000000000000000) 416 #define CP0_TAGLOD_XXX_61_60 UINT64_C(0x3000000000000000) 417 #define CP0_TAGLOD_ASID UINT64_C(0x0f00000000000000) 418 #define CP0_TAGLOD_XXX_51_49 UINT64_C(0x00f0000000000000) 419 #define CP0_TAGLOD_TAG UINT64_C(0x000fffffffffff80) 420 #define CP0_TAGLOD_XXX_6_2 UINT64_C(0x000000000000007c) 421 #define CP0_TAGLOD_G UINT64_C(0x0000000000000002) 422 #define CP0_TAGLOD_VALID UINT64_C(0x0000000000000001) 423 424 /* DataLo Register (Icache) */ 425 426 /* DataLo Register (Dcache) */ 427 428 /* TagHi Register */ 429 430 #define CP0_TAGHI_XXX_63_36 UINT64_C(0xfffffff000000000) 431 #define CP0_TAGHI_PTAG UINT64_C(0x0000000fffffff80) 432 #define CP0_TAGHI_XXX_6_1 UINT64_C(0x000000000000007e) 433 #define CP0_TAGHI_VALID UINT64_C(0x0000000000000001) 434 435 /* DataHi Register (Icache) */ 436 437 #define CP0_DATAHII_XXX_63_8 UINT64_C(0xffffffffffffff00) 438 #define CP0_DATAHII_PAR UINT64_C(0x00000000000000ff) 439 440 /* DataHi Register (Dcache) */ 441 442 #define CP0_DATAHID_XXX_63_8 UINT64_C(0xffffffffffffff00) 443 #define CP0_DATAHID_PAR UINT64_C(0x00000000000000ff) 444 445 /* CvmCtl Register */ 446 447 #define CP0_CVMCTL_XXX_63_32 UINT64_C(0xffffffff00000000) 448 #define CP0_CVMCTL_FUSE_STARTBIT UINT64_C(0x0000000080000000) 449 #define CP0_CVMCTL_XXX_30 UINT64_C(0x0000000040000000) 450 #define CP0_CVMCTL_KASUMI UINT64_C(0x0000000020000000) 451 #define CP0_CVMCTL_NODFA_CP21 UINT64_C(0x0000000010000000) 452 #define CP0_CVMCTL_NOMUL UINT64_C(0x0000000008000000) 453 #define CP0_CVMCTL_NOCRYPTO UINT64_C(0x0000000004000000) 454 #define CP0_CVMCTL_RST_SHT UINT64_C(0x0000000002000000) 455 #define CP0_CVMCTL_BIST_DIS UINT64_C(0x0000000001000000) 456 #define CP0_CVMCTL_DISSETPRED UINT64_C(0x0000000000800000) 457 #define CP0_CVMCTL_DISJRPRED UINT64_C(0x0000000000400000) 458 #define CP0_CVMCTL_DISICACHE UINT64_C(0x0000000000200000) 459 #define CP0_CVMCTL_DISWAIT UINT64_C(0x0000000000100000) 460 #define CP0_CVMCTL_DEFET UINT64_C(0x0000000000080000) 461 #define CP0_CVMCTL_DISCO UINT64_C(0x0000000000040000) 462 #define CP0_CVMCTL_DISCE UINT64_C(0x0000000000020000) 463 #define CP0_CVMCTL_DDCLK UINT64_C(0x0000000000010000) 464 #define CP0_CVMCTL_DCICLK UINT64_C(0x0000000000008000) 465 #define CP0_CVMCTL_REPUN UINT64_C(0x0000000000004000) 466 #define CP0_CVMCTL_IPREF UINT64_C(0x0000000000002000) 467 #define CP0_CVMCTL_USEUN UINT64_C(0x0000000000001000) 468 #define CP0_CVMCTL_DISIOCACHE UINT64_C(0x0000000000000800) 469 #define CP0_CVMCTL_IRAND UINT64_C(0x0000000000000400) 470 #define CP0_CVMCTL_IPPCI UINT64_C(0x0000000000000380) 471 #define CP0_CVMCTL_IPTI UINT64_C(0x0000000000000070) 472 #define CP0_CVMCTL_XXX_3_2 UINT64_C(0x000000000000000c) 473 #define CP0_CVMCTL_LE UINT64_C(0x0000000000000002) 474 #define CP0_CVMCTL_USELY UINT64_C(0x0000000000000001) 475 476 #define CP0_CVMCTL_BITS \ 477 "\177" /* new format */ \ 478 "\020" /* hex display */ \ 479 "\020" /* %016x format */ \ 480 "b\x1f" "FUSE_STARTBIT\0" \ 481 "b\x1c" "NODFA_CP21\0" \ 482 "b\x1b" "NOMUL\0" \ 483 "b\x1a" "NOCRYPTO\0" \ 484 "b\x19" "RST_SHT\0" \ 485 "b\x18" "BIST_DIS\0" \ 486 "b\x17" "DISSETPRED\0" \ 487 "b\x16" "DISJRPRED\0" \ 488 "b\x15" "DISICACHE\0" \ 489 "b\x14" "DISWAIT\0" \ 490 "b\x13" "DEFET\0" \ 491 "b\x12" "DISCO\0" \ 492 "b\x11" "DISCE\0" \ 493 "b\x10" "DDCLK\0" \ 494 "b\x0f" "DCICLK\0" \ 495 "b\x0e" "REPUN\0" \ 496 "b\x0d" "IPREF\0" \ 497 "b\x0c" "USEUN\0" \ 498 "b\x0b" "DISIOCACHE\0" \ 499 "b\x0a" "IRAND\0" \ 500 "f\x07\x03" "IPPCI\0" \ 501 "f\x04\x03" "IPTI\0" \ 502 "b\x01" "LE\0" \ 503 "b\x00" "USELY\0" 504 505 /* CvmMemCtl Register */ 506 507 #define CP0_CVMMEMCTL_TLBBIST UINT64_C(0x8000000000000000) 508 #define CP0_CVMMEMCTL_L1CBIST UINT64_C(0x4000000000000000) 509 #define CP0_CVMMEMCTL_L1DBIST UINT64_C(0x2000000000000000) 510 #define CP0_CVMMEMCTL_DCMBIST UINT64_C(0x1000000000000000) 511 #define CP0_CVMMEMCTL_PTGBIST UINT64_C(0x0800000000000000) 512 #define CP0_CVMMEMCTL_WBFBIST UINT64_C(0x0400000000000000) 513 #define CP0_CVMMEMCTL_XXX_57_36 UINT64_C(0x03fffff000000000) 514 #define CP0_CVMMEMCTL_DISMARKWBLONGTO UINT64_C(0x0000000800000000) 515 #define CP0_CVMMEMCTL_DISMRGCLRWBTO UINT64_C(0x0000000400000000) 516 #define CP0_CVMMEMCTL_IOBDMASCRMSB UINT64_C(0x0000000300000000) 517 #define CP0_CVMMEMCTL_SYNCWSMARKED UINT64_C(0x0000000080000000) 518 #define CP0_CVMMEMCTL_DISSYNCWS UINT64_C(0x0000000040000000) 519 #define CP0_CVMMEMCTL_DISWBFST UINT64_C(0x0000000020000000) 520 #define CP0_CVMMEMCTL_XKMEMENAS UINT64_C(0x0000000010000000) 521 #define CP0_CVMMEMCTL_XKMEMENAU UINT64_C(0x0000000008000000) 522 #define CP0_CVMMEMCTL_XKIOENAS UINT64_C(0x0000000004000000) 523 #define CP0_CVMMEMCTL_XKIOENAU UINT64_C(0x0000000002000000) 524 #define CP0_CVMMEMCTL_ALLSYNCW UINT64_C(0x0000000001000000) 525 #define CP0_CVMMEMCTL_NOMERGE UINT64_C(0x0000000000800000) 526 #define CP0_CVMMEMCTL_DIDTTO UINT64_C(0x0000000000600000) 527 #define CP0_CVMMEMCTL_CSRCLKALWYS UINT64_C(0x0000000000100000) 528 #define CP0_CVMMEMCTL_MCLKALWYS UINT64_C(0x0000000000080000) 529 #define CP0_CVMMEMCTL_WBFLTIME UINT64_C(0x0000000000070000) 530 #define CP0_CVMMEMCTL_ISTRNOL2 UINT64_C(0x0000000000008000) 531 #define CP0_CVMMEMCTL_WBTHRESH UINT64_C(0x0000000000007800) 532 #define CP0_CVMMEMCTL_XXX_10_9 UINT64_C(0x0000000000000600) 533 #define CP0_CVMMEMCTL_CVMSEGENAK UINT64_C(0x0000000000000100) 534 #define CP0_CVMMEMCTL_CVMSEGENAS UINT64_C(0x0000000000000080) 535 #define CP0_CVMMEMCTL_CVMSEGENAU UINT64_C(0x0000000000000040) 536 #define CP0_CVMMEMCTL_LMEMSZ UINT64_C(0x000000000000003f) 537 538 #define CP0_CVMMEMCTL_BITS \ 539 "\177" /* new format */ \ 540 "\020" /* hex display */ \ 541 "\020" /* %016x format */ \ 542 "b\x3f" "TLBBIST\0" \ 543 "b\x3e" "L1CBIST\0" \ 544 "b\x3d" "L1DBIST\0" \ 545 "b\x3c" "DCMBIST\0" \ 546 "b\x3b" "PTGBIST\0" \ 547 "b\x3a" "WBFBIST\0" \ 548 "b\x23" "DISMARKWBLONGTO\0" \ 549 "b\x22" "DISMRGCLRWBTO\0" \ 550 "f\x20\x02" "IOBDMASCRMSB\0" \ 551 "b\x1f" "SYNCWSMARKED\0" \ 552 "b\x1e" "DISSYNCWS\0" \ 553 "b\x1d" "DISWBFST\0" \ 554 "b\x1c" "XKMEMENAS\0" \ 555 "b\x1b" "XKMEMENAU\0" \ 556 "b\x1a" "XKIOENAS\0" \ 557 "b\x19" "XKIOENAU\0" \ 558 "b\x18" "ALLSYNCW\0" \ 559 "b\x17" "NOMERGE\0" \ 560 "f\x15\x02" "DIDTTO\0" \ 561 "b\x14" "CSRCLKALWYS\0" \ 562 "b\x13" "MCLKALWYS\0" \ 563 "f\x10\x03" "WBFLTIME\0" \ 564 "b\x0f" "ISTRNOL2\0" \ 565 "f\x0b\x04" "WBTHRESH\0" \ 566 "b\x08" "CVMSEGENAK\0" \ 567 "b\x07" "CVMSEGENAS\0" \ 568 "b\x06" "CVMSEGENAU\0" \ 569 "f\x00\x06" "LMEMSZ\0" 570 571 /* CvmCount Register */ 572 573 /* Multi-Core Debug Register */ 574 575 #define CP0_MCD_XXX_63_17 UINT64_C(0xfffffffffffe0000) 576 #define CP0_MCD_DEXCC UINT64_C(0x0000000000010000) 577 #define CP0_MCD_CGSTP UINT64_C(0x0000000000008000) 578 #define CP0_MCD_CVGSTP UINT64_C(0x0000000000004000) 579 #define CP0_MCD_CVDM UINT64_C(0x0000000000002000) 580 #define CP0_MCD_GSDB UINT64_C(0x0000000000001000) 581 #define CP0_MCD_XXX_11 UINT64_C(0x0000000000000800) 582 #define CP0_MCD_MSKM2 UINT64_C(0x0000000000000400) 583 #define CP0_MCD_MSKM1 UINT64_C(0x0000000000000200) 584 #define CP0_MCD_MMC0 UINT64_C(0x0000000000000100) 585 #define CP0_MCD_XXX_7 UINT64_C(0x0000000000000080) 586 #define CP0_MCD_PLS2 UINT64_C(0x0000000000000040) 587 #define CP0_MCD_PLS1 UINT64_C(0x0000000000000020) 588 #define CP0_MCD_PLS0 UINT64_C(0x0000000000000010) 589 #define CP0_MCD_XXX_3 UINT64_C(0x0000000000000008) 590 #define CP0_MCD_MCD2 UINT64_C(0x0000000000000004) 591 #define CP0_MCD_MCD1 UINT64_C(0x0000000000000002) 592 #define CP0_MCD_MCD0 UINT64_C(0x0000000000000001) 593 594 /* 595 * Core EJTAG DRSEG Registers 596 */ 597 598 /* XXX */ 599 600 /* 601 * Core EJTAG TAP Registers 602 */ 603 604 /* XXX */ 605 606 /* ---- operations */ 607 608 /* XXX */ 609 610 /* 611 * OCTEON Configuration and Status Registers (CSRs) 612 */ 613 614 #define CSR_COP0 /* Core coprosessor 0 registers */ 615 #define CSR_COP2 /* Core coprosessor 2 registers */ 616 #define CSR_COREEJTAG /* Core EJTAG registers */ 617 #define CSR_COREEJTAGTAP /* Core EJTAG TAP registers */ 618 #define CSR_NCB /* NCB registers */ 619 #define CSR_RSL /* RSL registers */ 620 #define CSR_PCICONFIG /* PCICONFIG registers */ 621 #define CSR_PCI /* PCI registers */ 622 #define CSR_PCINCB /* PCI_NCB registers */ 623 #define CSR_JTAGTAP /* JTAG TAP registers */ 624 #define CSR_TWSICORE /* TWSI Core registers */ 625 626 /* XXX */ 627 628 #endif /* _OCTEON_COREREG_H_ */ 629