xref: /netbsd-src/sys/arch/mips/cavium/dev/octeon_bootbusreg.h (revision bdc22b2e01993381dcefeff2bc9b56ca75a4235c)
1 /*	$NetBSD: octeon_bootbusreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $	*/
2 
3 /*
4  * Copyright (c) 2007 Internet Initiative Japan, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 /*
30  * Boot-Bus Registers
31  */
32 
33 #ifndef _OCTEON_BOOTBUSREG_H_
34 #define _OCTEON_BOOTBUSREG_H_
35 
36 /* ---- register addresses */
37 
38 #define	MIO_BOOT_REG_CFG0			0x0001180000000000ULL
39 #define	MIO_BOOT_REG_CFG1			0x0001180000000008ULL
40 #define	MIO_BOOT_REG_CFG2			0x0001180000000010ULL
41 #define	MIO_BOOT_REG_CFG3			0x0001180000000018ULL
42 #define	MIO_BOOT_REG_CFG4			0x0001180000000020ULL
43 #define	MIO_BOOT_REG_CFG5			0x0001180000000028ULL
44 #define	MIO_BOOT_REG_CFG6			0x0001180000000030ULL
45 #define	MIO_BOOT_REG_CFG7			0x0001180000000038ULL
46 #define	MIO_BOOT_REG_TIM0			0x0001180000000040ULL
47 #define	MIO_BOOT_REG_TIM1			0x0001180000000048ULL
48 #define	MIO_BOOT_REG_TIM2			0x0001180000000050ULL
49 #define	MIO_BOOT_REG_TIM3			0x0001180000000058ULL
50 #define	MIO_BOOT_REG_TIM4			0x0001180000000060ULL
51 #define	MIO_BOOT_REG_TIM5			0x0001180000000068ULL
52 #define	MIO_BOOT_REG_TIM6			0x0001180000000070ULL
53 #define	MIO_BOOT_REG_TIM7			0x0001180000000078ULL
54 #define	MIO_BOOT_LOC_CFG0			0x0001180000000080ULL
55 #define	MIO_BOOT_LOC_CFG1			0x0001180000000088ULL
56 #define	MIO_BOOT_LOC_ADR			0x0001180000000090ULL
57 #define	MIO_BOOT_LOC_DAT			0x0001180000000098ULL
58 #define	MIO_BOOT_ERR				0x00011800000000a0ULL
59 #define	MIO_BOOT_INT				0x00011800000000a8ULL
60 #define	MIO_BOOT_THR				0x00011800000000b0ULL
61 #define	MIO_BOOT_BIST_STAT			0x00011800000000f8ULL
62 
63 /* ---- register bits */
64 
65 #define	MIO_BOOT_REG_CFGN_XXX_63_37		UINT64_C(0xffffffe000000000)
66 #define	MIO_BOOT_REG_CFGN_SAM			UINT64_C(0x0000001000000000)
67 #define	MIO_BOOT_REG_CFGN_WE_EXT		UINT64_C(0x0000000c00000000)
68 #define	MIO_BOOT_REG_CFGN_OE_EXT		UINT64_C(0x0000000300000000)
69 #define	MIO_BOOT_REG_CFGN_EN			UINT64_C(0x0000000080000000)
70 #define	MIO_BOOT_REG_CFGN_OR			UINT64_C(0x0000000040000000)
71 #define	MIO_BOOT_REG_CFGN_ALE			UINT64_C(0x0000000020000000)
72 #define	MIO_BOOT_REG_CFGN_WIDTH			UINT64_C(0x0000000010000000)
73 #define	MIO_BOOT_REG_CFGN_SIZE			UINT64_C(0x000000000fff0000)
74 #define	MIO_BOOT_REG_CFGN_BASE			UINT64_C(0x000000000000ffff)
75 
76 #define	MIO_BOOT_REG_TIMN_PAGEM			UINT64_C(0x8000000000000000)
77 #define	MIO_BOOT_REG_TIMN_WAITM			UINT64_C(0x4000000000000000)
78 #define	MIO_BOOT_REG_TIMN_PAGES			UINT64_C(0x3000000000000000)
79 #define	MIO_BOOT_REG_TIMN_ALE			UINT64_C(0x0fc0000000000000)
80 #define	MIO_BOOT_REG_TIMN_PAGE			UINT64_C(0x003f000000000000)
81 #define	MIO_BOOT_REG_TIMN_WAIT			UINT64_C(0x0000fc0000000000)
82 #define	MIO_BOOT_REG_TIMN_PAUSE			UINT64_C(0x000003f000000000)
83 #define	MIO_BOOT_REG_TIMN_WR_HLD		UINT64_C(0x0000000fc0000000)
84 #define	MIO_BOOT_REG_TIMN_RD_HLD		UINT64_C(0x000000003f000000)
85 #define	MIO_BOOT_REG_TIMN_WE			UINT64_C(0x0000000000fc0000)
86 #define	MIO_BOOT_REG_TIMN_OE			UINT64_C(0x000000000003f000)
87 #define	MIO_BOOT_REG_TIMN_CE			UINT64_C(0x0000000000000fc0)
88 #define	MIO_BOOT_REG_TIMN_ADR			UINT64_C(0x000000000000003f)
89 
90 #define	MIO_BOOT_LOC_CFGN_XXX_63_32		UINT64_C(0xffffffff00000000)
91 #define	MIO_BOOT_LOC_CFGN_EN			UINT64_C(0x0000000080000000)
92 #define	MIO_BOOT_LOC_CFGN_XXX_30_28		UINT64_C(0x0000000070000000)
93 #define	MIO_BOOT_LOC_CFGN_BASE			UINT64_C(0x000000000ffffff8)
94 #define	MIO_BOOT_LOC_CFGN_XXX_2_0		UINT64_C(0x0000000000000007)
95 
96 #define	MIO_BOOT_LOC_ADR_XXX_63_8		UINT64_C(0xffffffffffffff00)
97 #define	MIO_BOOT_LOC_ADR_ADR			UINT64_C(0x00000000000000f8)
98 #define	MIO_BOOT_LOC_ADR_XXX_2_0		UINT64_C(0x0000000000000007)
99 
100 #define	MIO_BOOT_ERR_XXX_63_2			UINT64_C(0xfffffffffffffffc)
101 #define	MIO_BOOT_ERR_WAIT_ERR			UINT64_C(0x0000000000000002)
102 #define	MIO_BOOT_ERR_ADR_ERR			UINT64_C(0x0000000000000001)
103 
104 #define	MIO_BOOT_INT_XXX_63_2			UINT64_C(0xfffffffffffffffc)
105 #define	MIO_BOOT_INT_WAIT_INT			UINT64_C(0x0000000000000002)
106 #define	MIO_BOOT_INT_ADR_INT			UINT64_C(0x0000000000000001)
107 
108 #define	MIO_BOOT_THR_XXX_63_14			UINT64_C(0xffffffffffffc000)
109 #define	MIO_BOOT_THR_FIF_CNT			UINT64_C(0x0000000000003f00)
110 #define	MIO_BOOT_THR_XXX_7_6			UINT64_C(0x00000000000000c0)
111 #define	MIO_BOOT_THR_FIF_THR			UINT64_C(0x000000000000003f)
112 
113 #define	MIO_BOOT_BIST_STAT_XXX_63_4		UINT64_C(0xfffffffffffffff0)
114 #define	MIO_BOOT_BIST_STAT_NCBO_1		UINT64_C(0x0000000000000008)
115 #define	MIO_BOOT_BIST_STAT_NCBO_0		UINT64_C(0x0000000000000004)
116 #define	MIO_BOOT_BIST_STAT_LOC			UINT64_C(0x0000000000000002)
117 #define	MIO_BOOT_BIST_STAT_NCBI			UINT64_C(0x0000000000000001)
118 
119 /* ---- snprintb */
120 
121 #define	MIO_BOOT_REG_CFGN_BITS \
122 	"\177"		/* new format */ \
123 	"\020"		/* hex display */ \
124 	"\020"		/* %016x format */ \
125 	"b\x24"		"SAM\0" \
126 	"f\x22\x02"	"WE_EXT\0" \
127 	"f\x20\x02"	"OE_EXT\0" \
128 	"b\x1f"		"EN\0" \
129 	"b\x1e"		"OR\0" \
130 	"b\x1d"		"ALE\0" \
131 	"b\x1c"		"WIDTH\0" \
132 	"f\x10\x0c"	"SIZE\0" \
133 	"f\x00\x10"	"BASE\0"
134 #define	MIO_BOOT_REG_CFG0_BITS			MIO_BOOT_REG_CFGN_BITS
135 #define	MIO_BOOT_REG_CFG1_BITS			MIO_BOOT_REG_CFGN_BITS
136 #define	MIO_BOOT_REG_CFG2_BITS			MIO_BOOT_REG_CFGN_BITS
137 #define	MIO_BOOT_REG_CFG3_BITS			MIO_BOOT_REG_CFGN_BITS
138 #define	MIO_BOOT_REG_CFG4_BITS			MIO_BOOT_REG_CFGN_BITS
139 #define	MIO_BOOT_REG_CFG5_BITS			MIO_BOOT_REG_CFGN_BITS
140 #define	MIO_BOOT_REG_CFG6_BITS			MIO_BOOT_REG_CFGN_BITS
141 #define	MIO_BOOT_REG_CFG7_BITS			MIO_BOOT_REG_CFGN_BITS
142 
143 #define	MIO_BOOT_REG_TIMN_BITS \
144 	"\177"		/* new format */ \
145 	"\020"		/* hex display */ \
146 	"\020"		/* %016x format */ \
147 	"b\x3f"		"PAGEM\0" \
148 	"b\x3e"		"WAITM\0" \
149 	"f\x3c\x02"	"PAGES\0" \
150 	"f\x36\x06"	"ALE\0" \
151 	"f\x30\x06"	"PAGE\0" \
152 	"f\x2a\x06"	"WAIT\0" \
153 	"f\x24\x06"	"PAUSE\0" \
154 	"f\x1e\x06"	"WR_HLD\0" \
155 	"f\x18\x06"	"RD_HLD\0" \
156 	"f\x12\x06"	"WE\0" \
157 	"f\x0c\x06"	"OE\0" \
158 	"f\x06\x06"	"CE\0" \
159 	"f\x00\x06"	"ADR\0"
160 #define	MIO_BOOT_REG_TIM0_BITS			MIO_BOOT_REG_TIMN_BITS
161 #define	MIO_BOOT_REG_TIM1_BITS			MIO_BOOT_REG_TIMN_BITS
162 #define	MIO_BOOT_REG_TIM2_BITS			MIO_BOOT_REG_TIMN_BITS
163 #define	MIO_BOOT_REG_TIM3_BITS			MIO_BOOT_REG_TIMN_BITS
164 #define	MIO_BOOT_REG_TIM4_BITS			MIO_BOOT_REG_TIMN_BITS
165 #define	MIO_BOOT_REG_TIM5_BITS			MIO_BOOT_REG_TIMN_BITS
166 #define	MIO_BOOT_REG_TIM6_BITS			MIO_BOOT_REG_TIMN_BITS
167 #define	MIO_BOOT_REG_TIM7_BITS			MIO_BOOT_REG_TIMN_BITS
168 
169 #define	MIO_BOOT_LOC_CFGN_BITS \
170 	"\177"		/* new format */ \
171 	"\020"		/* hex display */ \
172 	"\020"		/* %016x format */ \
173 	"b\x1f"		"EN\0" \
174 	"f\x03\x19"	"BASE\0"
175 #define	MIO_BOOT_LOC_CFG0_BITS			MIO_BOOT_LOC_CFGN_BITS
176 #define	MIO_BOOT_LOC_CFG1_BITS			MIO_BOOT_LOC_CFGN_BITS
177 #define	MIO_BOOT_LOC_CFG2_BITS			MIO_BOOT_LOC_CFGN_BITS
178 #define	MIO_BOOT_LOC_CFG3_BITS			MIO_BOOT_LOC_CFGN_BITS
179 #define	MIO_BOOT_LOC_CFG4_BITS			MIO_BOOT_LOC_CFGN_BITS
180 #define	MIO_BOOT_LOC_CFG5_BITS			MIO_BOOT_LOC_CFGN_BITS
181 #define	MIO_BOOT_LOC_CFG6_BITS			MIO_BOOT_LOC_CFGN_BITS
182 #define	MIO_BOOT_LOC_CFG7_BITS			MIO_BOOT_LOC_CFGN_BITS
183 
184 #define	MIO_BOOT_LOC_ADR_BITS \
185 	"\177"		/* new format */ \
186 	"\020"		/* hex display */ \
187 	"\020"		/* %016x format */ \
188 	"f\x03\x05"	"ADR\0"
189 
190 #define	MIO_BOOT_ERR_BITS \
191 	"\177"		/* new format */ \
192 	"\020"		/* hex display */ \
193 	"\020"		/* %016x format */ \
194 	"b\x01"		"WAIT_ERR\0" \
195 	"b\x00"		"ADR_ERR\0"
196 
197 #define	MIO_BOOT_INT_BITS \
198 	"\177"		/* new format */ \
199 	"\020"		/* hex display */ \
200 	"\020"		/* %016x format */ \
201 	"b\x01"		"WAIT_INT\0" \
202 	"b\x00"		"ADR_INT\0"
203 
204 #define	MIO_BOOT_THR_BITS \
205 	"\177"		/* new format */ \
206 	"\020"		/* hex display */ \
207 	"\020"		/* %016x format */ \
208 	"f\x08\x06"	"FIF_CNT\0" \
209 	"f\x00\x06"	"FIF_THR\0"
210 
211 #define	MIO_BOOT_BIST_STAT_BITS \
212 	"\177"		/* new format */ \
213 	"\020"		/* hex display */ \
214 	"\020"		/* %016x format */ \
215 	"b\x03"		"NCBO_1\0" \
216 	"b\x02"		"NCBO_0\0" \
217 	"b\x01"		"LOC\0" \
218 	"b\x00"		"NCBI\0"
219 
220 /* ---- bus_space */
221 
222 #define	MIO_BOOT_REG_CFG0_OFFSET		0x0000
223 #define	MIO_BOOT_REG_CFG1_OFFSET		0x0008
224 #define	MIO_BOOT_REG_CFG2_OFFSET		0x0010
225 #define	MIO_BOOT_REG_CFG3_OFFSET		0x0018
226 #define	MIO_BOOT_REG_CFG4_OFFSET		0x0020
227 #define	MIO_BOOT_REG_CFG5_OFFSET		0x0028
228 #define	MIO_BOOT_REG_CFG6_OFFSET		0x0030
229 #define	MIO_BOOT_REG_CFG7_OFFSET		0x0038
230 #define	MIO_BOOT_REG_TIM0_OFFSET		0x0040
231 #define	MIO_BOOT_REG_TIM1_OFFSET		0x0048
232 #define	MIO_BOOT_REG_TIM2_OFFSET		0x0050
233 #define	MIO_BOOT_REG_TIM3_OFFSET		0x0058
234 #define	MIO_BOOT_REG_TIM4_OFFSET		0x0060
235 #define	MIO_BOOT_REG_TIM5_OFFSET		0x0068
236 #define	MIO_BOOT_REG_TIM6_OFFSET		0x0070
237 #define	MIO_BOOT_REG_TIM7_OFFSET		0x0078
238 #define	MIO_BOOT_LOC_CFG0_OFFSET		0x0080
239 #define	MIO_BOOT_LOC_CFG1_OFFSET		0x0088
240 #define	MIO_BOOT_LOC_ADR_OFFSET			0x0090
241 #define	MIO_BOOT_LOC_DAT_OFFSET			0x0098
242 #define	MIO_BOOT_ERR_OFFSET			0x00a0
243 #define	MIO_BOOT_INT_OFFSET			0x00a8
244 #define	MIO_BOOT_THR_OFFSET			0x00b0
245 #define	MIO_BOOT_BIST_STAT_OFFSET		0x00f8
246 
247 #endif /* _OCTEON_BOOTBUSREG_H_ */
248