1 /* $NetBSD: aevar.h,v 1.1 2006/03/21 08:15:19 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #ifndef _MIPS_ATHEROS_DEV_AEVAR_H_ 41 #define _MIPS_ATHEROS_DEV_AEVAR_H_ 42 43 #include "rnd.h" 44 45 #include <sys/queue.h> 46 #include <sys/callout.h> 47 48 #if NRND > 0 49 #include <sys/rnd.h> 50 #endif 51 52 /* 53 * Misc. definitions for the Digital Semiconductor ``Tulip'' (21x4x) 54 * Ethernet controller family driver. 55 */ 56 57 /* 58 * Transmit descriptor list size. This is arbitrary, but allocate 59 * enough descriptors for 64 pending transmissions and 16 segments 60 * per packet. Since a descriptor holds 2 buffer addresses, that's 61 * 8 descriptors per packet. This MUST work out to a power of 2. 62 */ 63 #define AE_NTXSEGS 16 64 65 #define AE_TXQUEUELEN 64 66 #define AE_NTXDESC (AE_TXQUEUELEN * AE_NTXSEGS) 67 #define AE_NTXDESC_MASK (AE_NTXDESC - 1) 68 #define AE_NEXTTX(x) ((x + 1) & AE_NTXDESC_MASK) 69 70 /* 71 * Receive descriptor list size. We have one Rx buffer per incoming 72 * packet, so this logic is a little simpler. 73 */ 74 #define AE_NRXDESC 64 75 #define AE_NRXDESC_MASK (AE_NRXDESC - 1) 76 #define AE_NEXTRX(x) ((x + 1) & AE_NRXDESC_MASK) 77 78 /* 79 * Control structures are DMA'd to the TULIP chip. We allocate them in 80 * a single clump that maps to a single DMA segment to make several things 81 * easier. 82 */ 83 struct ae_control_data { 84 /* 85 * The transmit descriptors. 86 */ 87 struct ae_desc acd_txdescs[AE_NTXDESC]; 88 89 /* 90 * The receive descriptors. 91 */ 92 struct ae_desc acd_rxdescs[AE_NRXDESC]; 93 }; 94 95 #define AE_CDOFF(x) offsetof(struct ae_control_data, x) 96 #define AE_CDTXOFF(x) AE_CDOFF(acd_txdescs[(x)]) 97 #define AE_CDRXOFF(x) AE_CDOFF(acd_rxdescs[(x)]) 98 99 /* 100 * Software state for transmit jobs. 101 */ 102 struct ae_txsoft { 103 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 104 bus_dmamap_t txs_dmamap; /* our DMA map */ 105 int txs_firstdesc; /* first descriptor in packet */ 106 int txs_lastdesc; /* last descriptor in packet */ 107 int txs_ndescs; /* number of descriptors */ 108 SIMPLEQ_ENTRY(ae_txsoft) txs_q; 109 }; 110 111 SIMPLEQ_HEAD(ae_txsq, ae_txsoft); 112 113 /* 114 * Software state for receive jobs. 115 */ 116 struct ae_rxsoft { 117 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 118 bus_dmamap_t rxs_dmamap; /* our DMA map */ 119 }; 120 121 struct ae_softc; 122 123 /* 124 * Some misc. statics, useful for debugging. 125 */ 126 struct ae_stats { 127 u_long ts_tx_uf; /* transmit underflow errors */ 128 u_long ts_tx_to; /* transmit jabber timeouts */ 129 u_long ts_tx_ec; /* excessive collision count */ 130 u_long ts_tx_lc; /* late collision count */ 131 }; 132 133 #ifndef _STANDALONE 134 /* 135 * Software state per device. 136 */ 137 struct ae_softc { 138 struct device sc_dev; /* generic device information */ 139 bus_space_tag_t sc_st; /* bus space tag */ 140 bus_space_handle_t sc_sh; /* bus space handle */ 141 bus_size_t sc_size; /* bus space size */ 142 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 143 void *sc_ih; /* interrupt handle */ 144 int sc_irq; /* interrupt request line */ 145 struct ethercom sc_ethercom; /* ethernet common data */ 146 void *sc_sdhook; /* shutdown hook */ 147 void *sc_powerhook; /* power management hook */ 148 149 struct ae_stats sc_stats; /* debugging stats */ 150 151 int sc_flags; /* misc flags. */ 152 153 struct mii_data sc_mii; /* MII/media information */ 154 155 int sc_txthresh; /* current transmit threshold */ 156 157 /* Media tick function. */ 158 void (*sc_tick)(void *); 159 struct callout sc_tick_callout; 160 161 u_int32_t sc_inten; /* copy of CSR_INTEN */ 162 163 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 164 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 165 166 bus_dma_segment_t sc_cdseg; /* control data memory */ 167 int sc_cdnseg; /* number of segments */ 168 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 169 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 170 171 /* 172 * Software state for transmit and receive descriptors. 173 */ 174 struct ae_txsoft sc_txsoft[AE_TXQUEUELEN]; 175 struct ae_rxsoft sc_rxsoft[AE_NRXDESC]; 176 177 /* 178 * Control data structures. 179 */ 180 struct ae_control_data *sc_control_data; 181 #define sc_txdescs sc_control_data->acd_txdescs 182 #define sc_rxdescs sc_control_data->acd_rxdescs 183 #define sc_setup_desc sc_control_data->acd_setup_desc 184 185 int sc_txfree; /* number of free Tx descriptors */ 186 int sc_txnext; /* next ready Tx descriptor */ 187 188 struct ae_txsq sc_txfreeq; /* free Tx descsofts */ 189 struct ae_txsq sc_txdirtyq; /* dirty Tx descsofts */ 190 191 short sc_if_flags; 192 193 int sc_rxptr; /* next ready RX descriptor/descsoft */ 194 195 #if NRND > 0 196 rndsource_element_t sc_rnd_source; /* random source */ 197 #endif 198 }; 199 #endif 200 201 /* sc_flags */ 202 #define AE_ATTACHED 0x00000800 /* attach has succeeded */ 203 #define AE_ENABLED 0x00001000 /* chip is enabled */ 204 205 #define AE_IS_ENABLED(sc) ((sc)->sc_flags & AE_ENABLED) 206 207 /* 208 * This macro returns the current media entry. 209 */ 210 #define AE_CURRENT_MEDIA(sc) ((sc)->sc_mii.mii_media.ifm_cur) 211 212 /* 213 * This macro determines if a change to media-related OPMODE bits requires 214 * a chip reset. 215 */ 216 #define TULIP_MEDIA_NEEDSRESET(sc, newbits) \ 217 (((sc)->sc_opmode & OPMODE_MEDIA_BITS) != \ 218 ((newbits) & OPMODE_MEDIA_BITS)) 219 220 #define AE_CDTXADDR(sc, x) ((sc)->sc_cddma + AE_CDTXOFF((x))) 221 #define AE_CDRXADDR(sc, x) ((sc)->sc_cddma + AE_CDRXOFF((x))) 222 223 #define AE_CDTXSYNC(sc, x, n, ops) \ 224 do { \ 225 int __x, __n; \ 226 \ 227 __x = (x); \ 228 __n = (n); \ 229 \ 230 /* If it will wrap around, sync to the end of the ring. */ \ 231 if ((__x + __n) > AE_NTXDESC) { \ 232 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 233 AE_CDTXOFF(__x), sizeof(struct ae_desc) * \ 234 (AE_NTXDESC - __x), (ops)); \ 235 __n -= (AE_NTXDESC - __x); \ 236 __x = 0; \ 237 } \ 238 \ 239 /* Now sync whatever is left. */ \ 240 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 241 AE_CDTXOFF(__x), sizeof(struct ae_desc) * __n, (ops)); \ 242 } while (0) 243 244 #define AE_CDRXSYNC(sc, x, ops) \ 245 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 246 AE_CDRXOFF((x)), sizeof(struct ae_desc), (ops)) 247 248 /* 249 * Note we rely on MCLBYTES being a power of two. Because the `length' 250 * field is only 11 bits, we must subtract 1 from the length to avoid 251 * having it truncated to 0! 252 */ 253 #define AE_INIT_RXDESC(sc, x) \ 254 do { \ 255 struct ae_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 256 struct ae_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 257 struct mbuf *__m = __rxs->rxs_mbuf; \ 258 \ 259 __m->m_data = __m->m_ext.ext_buf; \ 260 __rxd->ad_bufaddr1 = \ 261 (__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 262 __rxd->ad_bufaddr2 = \ 263 AE_CDRXADDR((sc), AE_NEXTRX((x))); \ 264 __rxd->ad_ctl = \ 265 ((((__m->m_ext.ext_size - 1) & ~0x3U) \ 266 << ADCTL_SIZE1_SHIFT) | \ 267 ((x) == (AE_NRXDESC - 1) ? ADCTL_ER : 0)); \ 268 __rxd->ad_status = ADSTAT_OWN|ADSTAT_Rx_FS|ADSTAT_Rx_LS; \ 269 AE_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 270 } while (0) 271 272 /* CSR access */ 273 274 #define AE_READ(sc, reg) \ 275 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 276 277 #define AE_WRITE(sc, reg, val) \ 278 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 279 280 #define AE_SET(sc, reg, mask) \ 281 AE_WRITE((sc), (reg), AE_READ((sc), (reg)) | (mask)) 282 283 #define AE_CLR(sc, reg, mask) \ 284 AE_WRITE((sc), (reg), AE_READ((sc), (reg)) & ~(mask)) 285 286 #define AE_ISSET(sc, reg, mask) \ 287 (AE_READ((sc), (reg)) & (mask)) 288 289 #define AE_BARRIER(sc) \ 290 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_size, \ 291 BUS_SPACE_BARRIER_WRITE) 292 293 #endif /* _MIPS_ATHEROS_DEV_AEVAR_H_ */ 294