1 /* $NetBSD: ar5312.c,v 1.7 2010/12/15 00:06:47 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Urbana-Champaign Independent Media Center. 5 * Copyright (c) 2006 Garrett D'Amore. 6 * All rights reserved. 7 * 8 * Portions of this code were written by Garrett D'Amore for the 9 * Champaign-Urbana Community Wireless Network Project. 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer in the documentation and/or other materials provided 19 * with the distribution. 20 * 3. All advertising materials mentioning features or use of this 21 * software must display the following acknowledgements: 22 * This product includes software developed by the Urbana-Champaign 23 * Independent Media Center. 24 * This product includes software developed by Garrett D'Amore. 25 * 4. Urbana-Champaign Independent Media Center's name and Garrett 26 * D'Amore's name may not be used to endorse or promote products 27 * derived from this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE URBANA-CHAMPAIGN INDEPENDENT 30 * MEDIA CENTER AND GARRETT D'AMORE ``AS IS'' AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 32 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE URBANA-CHAMPAIGN INDEPENDENT 34 * MEDIA CENTER OR GARRETT D'AMORE BE LIABLE FOR ANY DIRECT, INDIRECT, 35 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 36 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 37 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 41 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 */ 43 44 /* 45 * This file includes a bunch of implementation specific bits for 46 * AR5312, which differents these from other members of the AR5315 47 * family. 48 */ 49 #include "opt_ddb.h" 50 #include "opt_kgdb.h" 51 52 #include "opt_memsize.h" 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/device.h> 56 #include <sys/kernel.h> 57 #include <sys/buf.h> 58 59 #include <mips/cache.h> 60 #include <mips/locore.h> 61 #include <mips/cpuregs.h> 62 63 #include <sys/socket.h> /* these three just to get ETHER_ADDR_LEN(!) */ 64 #include <net/if.h> 65 #include <net/if_ether.h> 66 67 #include <prop/proplib.h> 68 69 #include <mips/atheros/include/ar5312reg.h> 70 #include <mips/atheros/include/ar531xvar.h> 71 #include <mips/atheros/include/arbusvar.h> 72 #include "com.h" 73 74 uint32_t 75 ar531x_memsize(void) 76 { 77 uint32_t memsize; 78 uint32_t memcfg, bank0, bank1; 79 80 /* 81 * Determine the memory size as established by system 82 * firmware. 83 * 84 * NB: we allow compile time override 85 */ 86 #if defined(MEMSIZE) 87 memsize = MEMSIZE; 88 #else 89 memcfg = GETSDRAMREG(AR5312_SDRAMCTL_MEM_CFG1); 90 bank0 = (memcfg & AR5312_MEM_CFG1_BANK0_MASK) >> 91 AR5312_MEM_CFG1_BANK0_SHIFT; 92 bank1 = (memcfg & AR5312_MEM_CFG1_BANK1_MASK) >> 93 AR5312_MEM_CFG1_BANK1_SHIFT; 94 95 memsize = (bank0 ? (1 << (bank0 + 1)) : 0) + 96 (bank1 ? (1 << (bank1 + 1)) : 0); 97 memsize <<= 20; 98 #endif 99 100 return (memsize); 101 } 102 103 void 104 ar531x_wdog(uint32_t period) 105 { 106 107 if (period == 0) { 108 PUTSYSREG(AR5312_SYSREG_WDOG_CTL, AR5312_WDOG_CTL_IGNORE); 109 PUTSYSREG(AR5312_SYSREG_WDOG_TIMER, 0); 110 } else { 111 PUTSYSREG(AR5312_SYSREG_WDOG_TIMER, period); 112 PUTSYSREG(AR5312_SYSREG_WDOG_CTL, AR5312_WDOG_CTL_RESET); 113 } 114 } 115 116 const char * 117 ar531x_cpuname(void) 118 { 119 uint32_t revision; 120 121 revision = GETSYSREG(AR5312_SYSREG_REVISION); 122 switch (AR5312_REVISION_MAJOR(revision)) { 123 case AR5312_REVISION_MAJ_AR5311: 124 return ("Atheros AR5311"); 125 case AR5312_REVISION_MAJ_AR5312: 126 return ("Atheros AR5312"); 127 case AR5312_REVISION_MAJ_AR2313: 128 return ("Atheros AR2313"); 129 case AR5312_REVISION_MAJ_AR5315: 130 return ("Atheros AR5315"); 131 default: 132 return ("Atheros AR531X"); 133 } 134 } 135 136 void 137 ar531x_businit(void) 138 139 { 140 /* 141 * Clear previous AHB errors 142 */ 143 GETSYSREG(AR5312_SYSREG_AHBPERR); 144 GETSYSREG(AR5312_SYSREG_AHBDMAE); 145 } 146 147 uint32_t 148 ar531x_cpu_freq(void) 149 { 150 static uint32_t cpufreq; 151 uint32_t wisoc = GETSYSREG(AR5312_SYSREG_REVISION); 152 153 uint32_t predivmask; 154 uint32_t predivshift; 155 uint32_t multmask; 156 uint32_t multshift; 157 uint32_t doublermask; 158 uint32_t divisor; 159 uint32_t multiplier; 160 uint32_t clockctl; 161 162 const int predivide_table[4] = { 1, 2, 4, 5 }; 163 164 /* XXX: in theory we might be able to get clock from bootrom */ 165 166 /* 167 * This logic looks at the clock control register and 168 * determines the actual CPU frequency. These parts lack any 169 * kind of real-time clock on them, but the cpu clocks should 170 * be very accurate -- WiFi requires usec resolution timers. 171 */ 172 173 if (cpufreq) { 174 return cpufreq; 175 } 176 177 if (AR5312_REVISION_MAJOR(wisoc) == AR5312_REVISION_MAJ_AR2313) { 178 predivmask = AR2313_CLOCKCTL_PREDIVIDE_MASK; 179 predivshift = AR2313_CLOCKCTL_PREDIVIDE_SHIFT; 180 multmask = AR2313_CLOCKCTL_MULTIPLIER_MASK; 181 multshift = AR2313_CLOCKCTL_MULTIPLIER_SHIFT; 182 doublermask = AR2313_CLOCKCTL_DOUBLER_MASK; 183 } else { 184 predivmask = AR5312_CLOCKCTL_PREDIVIDE_MASK; 185 predivshift = AR5312_CLOCKCTL_PREDIVIDE_SHIFT; 186 multmask = AR5312_CLOCKCTL_MULTIPLIER_MASK; 187 multshift = AR5312_CLOCKCTL_MULTIPLIER_SHIFT; 188 doublermask = AR5312_CLOCKCTL_DOUBLER_MASK; 189 } 190 191 /* 192 * Note that the source clock involved here is a 40MHz. 193 */ 194 195 clockctl = GETSYSREG(AR5312_SYSREG_CLOCKCTL); 196 divisor = predivide_table[(clockctl & predivmask) >> predivshift]; 197 multiplier = (clockctl & multmask) >> multshift; 198 199 if (clockctl & doublermask) 200 multiplier <<= 1; 201 202 cpufreq = (40000000 / divisor) * multiplier; 203 204 return (cpufreq); 205 } 206 207 uint32_t 208 ar531x_bus_freq(void) 209 { 210 return (ar531x_cpu_freq() / 4); 211 } 212 213 static void 214 addprop_data(struct device *dev, const char *name, const uint8_t *data, 215 int len) 216 { 217 prop_data_t pd; 218 pd = prop_data_create_data(data, len); 219 KASSERT(pd != NULL); 220 if (prop_dictionary_set(device_properties(dev), name, pd) == false) { 221 printf("WARNING: unable to set %s property for %s\n", 222 name, device_xname(dev)); 223 } 224 prop_object_release(pd); 225 } 226 227 static void 228 addprop_integer(struct device *dev, const char *name, uint32_t val) 229 { 230 prop_number_t pn; 231 pn = prop_number_create_integer(val); 232 KASSERT(pn != NULL); 233 if (prop_dictionary_set(device_properties(dev), name, pn) == false) { 234 printf("WARNING: unable to set %s property for %s", 235 name, device_xname(dev)); 236 } 237 prop_object_release(pn); 238 } 239 240 void 241 ar531x_device_register(struct device *dev, void *aux) 242 { 243 struct arbus_attach_args *aa = aux; 244 const struct ar531x_boarddata *info; 245 246 info = ar531x_board_info(); 247 if (info == NULL) { 248 /* nothing known about this board! */ 249 return; 250 } 251 252 /* 253 * We don't ever know the boot device. But that's because the 254 * firmware only loads from the network. 255 */ 256 257 /* Fetch the MAC addresses. */ 258 if (device_is_a(dev, "ae")) { 259 const uint8_t *enet; 260 261 if (aa->aa_addr == AR5312_ENET0_BASE) 262 enet = info->enet0Mac; 263 else if (aa->aa_addr == AR5312_ENET1_BASE) 264 enet = info->enet1Mac; 265 else 266 return; 267 268 addprop_data(dev, "mac-address", enet, ETHER_ADDR_LEN); 269 } 270 271 if (device_is_a(dev, "ath")) { 272 const uint8_t *enet; 273 274 if (aa->aa_addr == AR5312_WLAN0_BASE) 275 enet = info->wlan0Mac; 276 else if (aa->aa_addr == AR5312_WLAN1_BASE) 277 enet = info->wlan1Mac; 278 else 279 return; 280 281 addprop_data(dev, "mac-address", enet, ETHER_ADDR_LEN); 282 283 addprop_integer(dev, "wmac-rev", 284 AR5312_REVISION_WMAC(GETSYSREG(AR5312_SYSREG_REVISION))); 285 286 } 287 288 if (device_is_a(dev, "com")) { 289 addprop_integer(dev, "frequency", ar531x_cpu_freq() / 4); 290 } 291 292 if (device_is_a(dev, "argpio")) { 293 if (info->config & BD_RSTFACTORY) { 294 addprop_integer(dev, "reset-pin", 295 info->resetConfigGpio); 296 } 297 if (info->config & BD_SYSLED) { 298 addprop_integer(dev, "sysled-pin", 299 info->sysLedGpio); 300 } 301 } 302 } 303 304 int 305 ar531x_enable_device(const struct ar531x_device *dev) 306 { 307 const struct ar531x_boarddata *info; 308 309 info = ar531x_board_info(); 310 if (dev->mask && ((dev->mask & info->config) == 0)) { 311 return -1; 312 } 313 if (dev->reset) { 314 /* put device into reset */ 315 PUTSYSREG(AR5312_SYSREG_RESETCTL, 316 GETSYSREG(AR5312_SYSREG_RESETCTL) | dev->reset); 317 318 delay(15000); /* XXX: tsleep? */ 319 320 /* take it out of reset */ 321 PUTSYSREG(AR5312_SYSREG_RESETCTL, 322 GETSYSREG(AR5312_SYSREG_RESETCTL) & ~dev->reset); 323 324 delay(25); 325 } 326 if (dev->enable) { 327 PUTSYSREG(AR5312_SYSREG_ENABLE, 328 GETSYSREG(AR5312_SYSREG_ENABLE) | dev->enable); 329 } 330 return 0; 331 } 332 333 const struct ar531x_device * 334 ar531x_get_devices(void) 335 { 336 static const struct ar531x_device devices[] = { 337 { 338 "ae", 339 AR5312_ENET0_BASE, 0x100000, 340 AR5312_IRQ_ENET0, -1, 341 AR5312_BOARD_CONFIG_ENET0, 342 AR5312_RESET_ENET0 | AR5312_RESET_PHY0, 343 AR5312_ENABLE_ENET0 344 }, 345 { 346 "ae", 347 AR5312_ENET1_BASE, 0x100000, 348 AR5312_IRQ_ENET1, -1, 349 AR5312_BOARD_CONFIG_ENET1, 350 AR5312_RESET_ENET1 | AR5312_RESET_PHY1, 351 AR5312_ENABLE_ENET1 352 }, 353 { 354 "com", 355 AR5312_UART0_BASE, 0x1000, 356 AR5312_IRQ_MISC, AR5312_MISC_IRQ_UART0, 357 AR5312_BOARD_CONFIG_UART0, 358 0, 359 0, 360 }, 361 { 362 "com", 363 AR5312_UART1_BASE, 0x1000, 364 -1, -1, 365 AR5312_BOARD_CONFIG_UART1, 366 0, 367 0, 368 }, 369 { 370 "ath", 371 AR5312_WLAN0_BASE, 0x100000, 372 AR5312_IRQ_WLAN0, -1, 373 AR5312_BOARD_CONFIG_WLAN0, 374 AR5312_RESET_WLAN0 | 375 AR5312_RESET_WARM_WLAN0_MAC | 376 AR5312_RESET_WARM_WLAN0_BB, 377 AR5312_ENABLE_WLAN0 378 }, 379 { 380 "ath", 381 AR5312_WLAN1_BASE, 0x100000, 382 AR5312_IRQ_WLAN1, -1, 383 AR5312_BOARD_CONFIG_WLAN1, 384 AR5312_RESET_WLAN1 | 385 AR5312_RESET_WARM_WLAN1_MAC | 386 AR5312_RESET_WARM_WLAN1_BB, 387 AR5312_ENABLE_WLAN1 388 }, 389 { 390 "athflash", 391 AR5312_FLASH_BASE, 0, 392 -1, -1, 393 0, 394 0, 395 0, 396 }, 397 { 398 "argpio", 0x1000, 399 AR5312_GPIO_BASE, 400 AR5312_IRQ_MISC, AR5312_MISC_IRQ_GPIO, 401 0, 402 0, 403 0 404 }, 405 { NULL } 406 }; 407 408 return devices; 409 } 410 411