1 /* $NetBSD: aureg.h,v 1.5 2004/11/11 10:11:40 soren Exp $ */ 2 3 /* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* ********************************************************************* 39 * Naming schemes for constants in these files: 40 * 41 * M_xxx MASK constant (identifies bits in a register). 42 * For multi-bit fields, all bits in the field will 43 * be set. 44 * 45 * K_xxx "Code" constant (value for data in a multi-bit 46 * field). The value is right justified. 47 * 48 * V_xxx "Value" constant. This is the same as the 49 * corresponding "K_xxx" constant, except it is 50 * shifted to the correct position in the register. 51 * 52 * S_xxx SHIFT constant. This is the number of bits that 53 * a field value (code) needs to be shifted 54 * (towards the left) to put the value in the right 55 * position for the register. 56 * 57 * A_xxx ADDRESS constant. This will be a physical 58 * address. Use the MIPS_PHYS_TO_KSEG1 macro to 59 * generate a K1SEG address. 60 * 61 * R_xxx RELATIVE offset constant. This is an offset from 62 * an A_xxx constant (usually the first register in 63 * a group). 64 * 65 * G_xxx(X) GET value. This macro obtains a multi-bit field 66 * from a register, masks it, and shifts it to 67 * the bottom of the register (retrieving a K_xxx 68 * value, for example). 69 * 70 * V_xxx(X) VALUE. This macro computes the value of a 71 * K_xxx constant shifted to the correct position 72 * in the register. 73 ********************************************************************* */ 74 75 #if !defined(__ASSEMBLER__) 76 #define _MAKE64(x) ((uint64_t)(x)) 77 #define _MAKE32(x) ((uint32_t)(x)) 78 #else 79 #define _MAKE64(x) (x) 80 #define _MAKE32(x) (x) 81 #endif 82 83 /* Make a mask for 1 bit at position 'n' */ 84 #define _MAKEMASK1_64(n) (_MAKE64(1) << _MAKE64(n)) 85 #define _MAKEMASK1_32(n) (_MAKE32(1) << _MAKE32(n)) 86 87 /* Make a mask for 'v' bits at position 'n' */ 88 #define _MAKEMASK_64(v,n) (_MAKE64((_MAKE64(1)<<(v))-1) << _MAKE64(n)) 89 #define _MAKEMASK_32(v,n) (_MAKE32((_MAKE32(1)<<(v))-1) << _MAKE32(n)) 90 91 /* Make a value at 'v' at bit position 'n' */ 92 #define _MAKEVALUE_64(v,n) (_MAKE64(v) << _MAKE64(n)) 93 #define _MAKEVALUE_32(v,n) (_MAKE32(v) << _MAKE32(n)) 94 95 #define _GETVALUE_64(v,n,m) ((_MAKE64(v) & _MAKE64(m)) >> _MAKE64(n)) 96 #define _GETVALUE_32(v,n,m) ((_MAKE32(v) & _MAKE32(m)) >> _MAKE32(n)) 97 98 99 /************************************************************************/ 100 /******************** AC97 Controller registers *********************/ 101 /************************************************************************/ 102 #define AC97_BASE 0x10000000 103 104 #define AC97_CONFIG 0x00 105 106 #define M_AC97CFG_RS _MAKEMASK1_32(0) 107 #define M_AC97CFG_SN _MAKEMASK1_32(1) 108 #define M_AC97CFG_SG _MAKEMASK1_32(2) 109 110 #define S_AC97CFG_XS _MAKE32(12) 111 #define M_AC97CFG_XS _MAKEMASK_32(10) 112 #define V_AC97CFG_XS(x) _MAKEVALUE_32(x, S_AC97CFG_XS) 113 #define G_AC97CFG_XS(x) _GETVALUE_32(x, S_AC97CFG_XS, M_AC97CFG_XS) 114 115 #define S_AC97CFG_RC _MAKE32(12) 116 #define M_AC97CFG_RC _MAKEMASK_32(10) 117 #define V_AC97CFG_RC(x) _MAKEVALUE_32(x, S_AC97CFG_RC) 118 #define G_AC97CFG_RC(x) _GETVALUE_32(x, S_AC97CFG_RC, M_AC97CFG_RC) 119 120 #define AC97_STATUS 0x04 121 122 #define M_AC97STAT_RF _MAKEMASK1_32(0) 123 #define M_AC97STAT_RE _MAKEMASK1_32(1) 124 #define M_AC97STAT_TF _MAKEMASK1_32(3) 125 #define M_AC97STAT_TE _MAKEMASK1_32(4) 126 #define M_AC97STAT_CP _MAKEMASK1_32(6) 127 #define M_AC97STAT_RD _MAKEMASK1_32(7) 128 #define M_AC97STAT_RO _MAKEMASK1_32(8) 129 #define M_AC97STAT_RU _MAKEMASK1_32(9) 130 #define M_AC97STAT_XO _MAKEMASK1_32(10) 131 #define M_AC97STAT_XU _MAKEMASK1_32(11) 132 133 #define AC97_DATA 0x08 134 135 #define S_AC97DATA_DATA _MAKE32(0) 136 #define M_AC97DATA_DATA _MAKEMASK_32(16) 137 #define V_AC97DATA_DATA(x) _MAKEVALUE_32(x, S_AC97DATA_DATA) 138 #define G_AC97DATA_DATA(x) _GETVALUE_32(x, S_AC97DATA_DATA, M_AC97DATA_DATA) 139 140 #define AC97_COMMAND 0x0c 141 142 #define S_AC97CMD_INDEX _MAKE32(0) 143 #define M_AC97CMD_INDEX _MAKEMASK_32(7) 144 #define V_AC97CMD_INDEX(x) _MAKEVALUE_32(x, S_AC97CMD_INDEX) 145 #define G_AC97CMD_INDEX(x) _GETVALUE_32(x, S_AC97CMD_INDEX, M_AC97CMD_INDEX) 146 147 #define M_AC97CMD_RW _MAKEMASK1_32(7) 148 149 #define S_AC97CMD_DATA _MAKE32(16) 150 #define M_AC97CMD_DATA _MAKEMASK_32(16) 151 #define V_AC97CMD_DATA(x) _MAKEVALUE_32(x, S_AC97CMD_DATA) 152 #define G_AC97CMD_DATA(x) _GETVALUE_32(x, S_AC97CMD_DATA, M_AC97CMD_DATA) 153 154 #define AC97_COMMAND_RESPONSE 0x0c 155 156 #define S_AC97CMDRESP_DATA _MAKE32(0) 157 #define M_AC97CMDRESP_DATA _MAKEMASK_32(16) 158 #define V_AC97CMDRESP_DATA(x) _MAKEVALUE_32(x, S_AC97CMDRESP_DATA) 159 #define G_AC97CMDRESP_DATA(x) _GETVALUE_32(x, S_AC97CMDRESP_DATA, M_AC97CMDRESP_DATA) 160 161 #define AC97_ENABLE 0x10 162 163 #define M_AC97EN_CE _MAKEMASK1_32(0) 164 #define M_AC97EN_D _MAKEMASK1_32(1) 165 166 #define AC97_SIZE 0x14 /* size of register set */ 167 168 /************************************************************************/ 169 /*********************** USB Host registers *************************/ 170 /************************************************************************/ 171 #define USBH_BASE 0x10100000 172 173 #define USBH_ENABLE 0x7fffc 174 #define UE_RD 0x00000010 /* reset done */ 175 #define UE_CE 0x00000008 /* clock enable */ 176 #define UE_E 0x00000004 /* enable */ 177 #define UE_C 0x00000002 /* coherent */ 178 #define UE_BE 0x00000001 /* big-endian */ 179 180 #define USBH_SIZE 0x80000 /* size of register set */ 181 182 /************************************************************************/ 183 /********************** USB Device registers ************************/ 184 /************************************************************************/ 185 #define USBD_BASE 0x10200000 186 187 #define USBD_EP0RD 0x00 /* Read from endpoint 0 */ 188 #define USBD_EP0WR 0x04 /* Write to endpoint 0 */ 189 #define USBD_EP1WR 0x08 /* Write to endpoint 1 */ 190 #define USBD_EP2WR 0x0c /* Write to endpoint 2 */ 191 #define USBD_EP3RD 0x10 /* Read from endpoint 3 */ 192 #define USBD_EP4RD 0x14 /* Read from endpoint 4 */ 193 #define USBD_INTEN 0x18 /* Interrupt Enable Register */ 194 #define USBD_INTSTAT 0x1c /* Interrupt Status Register */ 195 #define USBD_CONFIG 0x20 /* Write Configuration Register */ 196 #define USBD_EP0CS 0x24 /* Endpoint 0 control and status */ 197 #define USBD_EP1CS 0x28 /* Endpoint 1 control and status */ 198 #define USBD_EP2CS 0x2c /* Endpoint 2 control and status */ 199 #define USBD_EP3CS 0x30 /* Endpoint 3 control and status */ 200 #define USBD_EP4CS 0x34 /* Endpoint 4 control and status */ 201 #define USBD_FRAMENUM 0x38 /* Current frame number */ 202 #define USBD_EP0RDSTAT 0x40 /* EP0 Read FIFO Status */ 203 #define USBD_EP0WRSTAT 0x44 /* EP0 Write FIFO Status */ 204 #define USBD_EP1WRSTAT 0x48 /* EP1 Write FIFO Status */ 205 #define USBD_EP2WRSTAT 0x4c /* EP2 Write FIFO Status */ 206 #define USBD_EP3RDSTAT 0x50 /* EP3 Read FIFO Status */ 207 #define USBD_EP4RDSTAT 0x54 /* EP4 Read FIFO Status */ 208 #define USBD_ENABLE 0x58 /* USB Device Controller Enable */ 209 210 /************************************************************************/ 211 /************************* IRDA registers ***************************/ 212 /************************************************************************/ 213 #define IRDA_BASE 0x10300000 214 215 /************************************************************************/ 216 /****************** Interrupt Controller registers ******************/ 217 /************************************************************************/ 218 219 #define IC0_BASE 0x10400000 220 #define IC1_BASE 0x11800000 221 222 /* 223 * The *_READ registers read the current value of the register 224 * The *_SET registers set to 1 all bits that are written 1 225 * The *_CLEAR registers clear to zero all bits that are written as 1 226 */ 227 #define IC_CONFIG0_READ 0x40 /* See table below */ 228 #define IC_CONFIG0_SET 0x40 229 #define IC_CONFIG0_CLEAR 0x44 230 231 #define IC_CONFIG1_READ 0x48 /* See table below */ 232 #define IC_CONFIG1_SET 0x48 233 #define IC_CONFIG1_CLEAR 0x4c 234 235 #define IC_CONFIG2_READ 0x50 /* See table below */ 236 #define IC_CONFIG2_SET 0x50 237 #define IC_CONFIG2_CLEAR 0x54 238 239 #define IC_REQUEST0_INT 0x54 /* Show active interrupts on request 0 */ 240 241 #define IC_SOURCE_READ 0x58 /* Interrupt source */ 242 #define IC_SOURCE_SET 0x58 /* 0 - test bit used as source */ 243 #define IC_SOURCE_CLEAR 0x5c /* 1 - peripheral/GPIO used as source */ 244 245 #define IC_REQUEST1_INT 0x5c /* Show active interrupts on request 1 */ 246 247 #define IC_ASSIGN_REQUEST_READ 0x60 /* Assigns the interrupt to one of the */ 248 #define IC_ASSIGN_REQUEST_SET 0x60 /* CPU requests (0 - assign to request 1, */ 249 #define IC_ASSIGN_REQUEST_CLEAR 0x64 /* 1 - assign to request 0) */ 250 251 #define IC_WAKEUP_READ 0x68 /* Controls whether the interrupt can */ 252 #define IC_WAKEUP_SET 0x68 /* cause a wakeup from IDLE */ 253 #define IC_WAKEUP_CLEAR 0x6c 254 255 #define IC_MASK_READ 0x70 /* Enables/Disables the interrupt */ 256 #define IC_MASK_SET 0x70 257 #define IC_MASK_CLEAR 0x74 258 259 #define IC_RISING_EDGE_DETECT 0x78 /* Check/clear rising edge interrupts */ 260 #define IC_RISING_EDGE_DETECT_CLEAR 0x78 261 262 #define IC_FAILLING_EDGE_DETECT 0x7c /* Check/clear falling edge interrupts */ 263 #define IC_FAILLING_EDGE_DETECT_CLEAR 0x7c 264 265 #define IC_TEST_BIT 0x80 /* single bit source select testing register */ 266 267 /* 268 * Interrupt Configuration Register Functions 269 * 270 * Cfg2[n] Cfg1[n] Cfg0[n] Function 271 * 0 0 0 Interrupts Disabled 272 * 0 0 1 Rising Edge Enabled 273 * 0 1 0 Falling Edge Enabled 274 * 0 1 1 Rising and Falling Edge Enabled 275 * 1 0 0 Interrupts Disabled 276 * 1 0 1 High Level Enabled 277 * 1 1 0 Low Level Enabled 278 * 1 1 1 Both Levels and Both Edges Enabled 279 */ 280 281 /************************************************************************/ 282 /********************** Ethernet MAC registers **********************/ 283 /************************************************************************/ 284 285 #define MAC0_BASE 0x10500000 286 #define MAC1_BASE 0x10510000 287 #define MACx_SIZE 0x28 288 289 #define AU1500_MAC0_BASE 0x11500000 /* Grr, difference on Au1500 */ 290 #define AU1500_MAC1_BASE 0x11510000 /* Grr, difference on Au1500 */ 291 292 #if 0 293 #define MAC_CONTROL 0x00 /* operation mode and address filter */ 294 #define MC_RA 0x80000000 /* Receive All */ 295 #define MC_EM 0x40000000 /* Endian Mode - data buffer is big endian */ 296 #define MC_DRO 0x00800000 /* Disable Receive Own */ 297 #define MC_LM_MASK 0x00600000 /* Loopback Operating Mode - mask */ 298 #define MC_LM_NORMAL 0x00600000 299 #define MC_LM_INTERNAL 0x00400000 300 #define MC_LM_EXTERNAL 0x00200000 301 #define MC_F 0x00100000 /* Full duplex mode */ 302 #define MC_PM 0x00080000 /* Pall all Multicast */ 303 #define MC_PR 0x00040000 /* Promiscious Mode */ 304 #define MC_IF 0x00020000 /* Inverse Filtering */ 305 #define MC_PB 0x00010000 /* Pass Bad frames */ 306 #define MC_HO 0x00008000 /* Hash Only filtering mode */ 307 #define MC_HP 0x00002000 /* Hash/Perfect filtering mode */ 308 #define MC_LC 0x00001000 /* Late Collision control */ 309 #define MC_DB 0x00000800 /* Disable Broadcast frames */ 310 #define MC_DR 0x00000400 /* Disable Retry */ 311 #define MC_AP 0x00000100 /* Automatic Pad stripping */ 312 #define MC_BL_MASK 0x000000c0 /* Backoff Limit mask */ 313 #define MC_BL_SHIFT 6 314 #define MC_DC 0x00000020 /* Deferral Check */ 315 #define MC_TE 0x00000008 /* Transmitter Enable */ 316 #define MC_RE 0x00000004 /* Receiver Enable */ 317 #define MAC_ADDRESS_HIGH 0x04 /* high 16 bits of the MAC address */ 318 #define MAC_ADDRESS_LOW 0x08 /* lower 32 bits of the MAC address */ 319 #define MAC_MCAST_HASH_HIGH 0x0c /* high 16 bits of mcat hash address */ 320 #define MAC_MCAST_HASH_LOW 0x10 /* low 32 bits of mcat hash address */ 321 #define MAC_MII_CONTROL 0x14 /* control of PHY management interface */ 322 #define MMC_PHY_ADDR_MASK 0x0000f800 /* PHY Address mask */ 323 #define MMC_PHY_ADDR_SHIFT 11 324 #define MMC_MIIREG_MASK 0x000007c0 /* MII Register mask */ 325 #define MMC_MIIREG_SHIFT 6 326 #define MMC_MW 0x00000002 /* MII Write */ 327 #define MMC_MB 0x00000001 /* MII Busy */ 328 #define MAC_MII_DATA 0x18 /* data to/from PHY */ 329 #define MAC_FLOW_CONTROL 0x1c /* frame generation control */ 330 #define MFC_PT_MASK 0xffff0000 /* Pause Time mask */ 331 #define MFC_PT_SHIFT 16 332 #define MFC_PC 0x00000004 /* Pass Control frame */ 333 #define MFC_FE 0x00000002 /* Flow Control enable */ 334 #define MFC_FB 0x00000001 /* Flow control Busy */ 335 #define MAC_VLAN1_TAG 0x20 /* VLAN1 tag */ 336 #define MAC_VLAN2_TAG 0x24 /* VLAN2 tag */ 337 #endif 338 339 #define MAC0_ENABLE 0x10520000 340 #define MAC1_ENABLE 0x10520004 341 #define MACENx_SIZE 0x04 342 343 #define AU1500_MAC0_ENABLE 0x11520000 /* Grr, difference on Au1500 */ 344 #define AU1500_MAC1_ENABLE 0x11520004 /* Grr, difference on Au1500 */ 345 346 #if 0 347 #define ME_DR 0x40 /* DMA reset */ 348 #define ME_R2 0x20 /* Reset2 */ 349 #define ME_R1 0x10 /* Reset1 */ 350 #define ME_C 0x08 /* Cacheable */ 351 #define ME_TS 0x04 /* Toss */ 352 #define ME_R0 0x02 /* Reset0 */ 353 #define ME_EN 0x01 /* Clock Enable */ 354 #endif 355 356 #define MAC0_DMA_BASE 0x14004000 357 #define MAC1_DMA_BASE 0x14004200 358 #define MACx_DMA_SIZE 0x140 359 #if 0 360 #define MAC_TXDMA 0x000 361 #define MAC_RXDMA 0x100 362 #define MAC_TXQLEN 4 363 #define MAC_RXQLEN 4 364 365 /* MAC Transmit Status registers */ 366 #define MTS_PR 0x80000000 /* Packet Retry */ 367 #define MTS_HB 0x00004000 /* ?!?? */ 368 #define MTS_CC_MASK 0x00003c00 /* Collision Count mask */ 369 #define MTS_CC_SHIFT 10 370 #define MTS_LO 0x00000200 /* Late collision Observed */ 371 #define MTS_DF 0x00000100 /* Deferred */ 372 #define MTS_UR 0x00000080 /* Underrun */ 373 #define MTS_EC 0x00000040 /* Excessive Collisions */ 374 #define MTS_LC 0x00000020 /* Late Collision */ 375 #define MTS_ED 0x00000010 /* Excessive Deferral */ 376 #define MFS_LS 0x00000008 /* LoSs of carrier */ 377 #define MFS_NC 0x00000004 /* No Carrier */ 378 #define MFS_JT 0x00000002 /* Jabber Timeout */ 379 #define MFS_FA 0x00000001 /* Frame Aborted */ 380 381 /* MAC Transmit Buffer Address/Enable registers */ 382 #define MTBAE_ADDR_MASK 0xffffffe0 /* Buffer address */ 383 #define MTBAE_CB_MASK 0x0000000c /* Current (DMA) Buffer */ 384 #define MTBAE_CB_SHIFT 2 385 #define MTBAE_DONE 0x00000002 /* transation DONE */ 386 #define MTBAE_EN 0x00000001 /* MAC DMA Enable */ 387 388 /* MAC Transmit Buffer Length registers */ 389 #define MTBL_LEN_MASK 0x000007ff /* buffer LENgth */ 390 #define MTBL_LEN_SHIFT 0 391 392 /* MAC Receive Status registers */ 393 #define MRS_MI 0x80000000 /* MIssed frame */ 394 #define MRS_PF 0x40000000 /* Packet Filter */ 395 #define MRS_FF 0x20000000 /* Filtering Fail */ 396 #define MRS_BF 0x10000000 /* Broadcast Frame */ 397 #define MRS_MF 0x08000000 /* Multicast Frame */ 398 #define MRS_UC 0x04000000 /* Unsupported Control frame */ 399 #define MRS_CF 0x02000000 /* Control Frame */ 400 #define MRS_LE 0x01000000 /* Length Error */ 401 #define MRS_V2 0x00800000 /* Vlan2 ID */ 402 #define MRS_V1 0x00400000 /* Vlan1 ID */ 403 #define MRS_CR 0x00200000 /* CRC error */ 404 #define MRS_DB 0x00100000 /* Dribbling Bit */ 405 #define MRS_ME 0x00080000 /* MII Error */ 406 #define MRS_FT 0x00040000 /* Frame Type */ 407 #define MRS_CS 0x00020000 /* Collision Seen */ 408 #define MRS_FL 0x00010000 /* Frame too Long */ 409 #define MRS_RF 0x00008000 /* Runt Frame */ 410 #define MRS_WT 0x00004000 /* Watchdog Timeout */ 411 #define MRS_L_MASK 0x00003fff /* frame Length mask*/ 412 #define MRS_L_SHIFT 0 413 414 /* MAC Receive Buffer Address/Enable registers */ 415 #define MRBAE_ADDR_MASK 0xffffffe0 /* Buffer address */ 416 #define MRBAE_CB_MASK 0x0000000c /* Current (DMA) Buffer */ 417 #define MRBAE_CB_SHIFT 2 418 #define MRBAE_DN 0x00000002 /* transation DoNe */ 419 #define MRBAE_EN 0x00000001 /* MAC DMA Enable */ 420 #endif 421 422 /************************************************************************/ 423 /******************** Secure Digital registers **********************/ 424 /************************************************************************/ 425 #define SD0_BASE 0x10600000 426 #define SD1_BASE 0x10680000 427 428 /************************************************************************/ 429 /************************* I^2S registers ***************************/ 430 /************************************************************************/ 431 #define I2S_BASE 0x11000000 432 433 /************************************************************************/ 434 /************************** UART registers **************************/ 435 /************************************************************************/ 436 437 #define UART0_BASE 0x11100000 438 #define UART1_BASE 0x11200000 439 #define UART2_BASE 0x11300000 440 #define UART3_BASE 0x11400000 441 442 #define UART_RXDATA 0x000 /* Received Data FIFO (R) */ 443 #define UART_TXDATA 0x004 /* Transmit Data FIFO (W) */ 444 #define UART_INTERRUPT_ENABLE 0x008 /* Interrupt Enable Register (R/W) */ 445 #define UIE_MIE 0x8 /* Modem Status Interrupt enable */ 446 #define UIE_LIE 0x4 /* Line Status Interrupt enable */ 447 #define UIE_TIE 0x2 /* Transmit Interrupt Enable */ 448 #define UIE_RIE 0x1 /* Receive Interrupt Enable */ 449 #define UART_INTERRUPT_CAUSE 0x00c /* Pending Interrupt Cause Register (R) */ 450 #define UIC_IID_MASK 0xe /* mask for Interrupt IDentifier */ 451 #define UIC_IID_MS 0x0 /* Modem Status */ 452 #define UIC_IID_TBA 0x2 /* Transmit Buffer Available */ 453 #define UIC_IID_RDA 0x4 /* Receive Data Available */ 454 #define UIC_IID_RLS 0x6 /* Receive Line Status */ 455 #define UIC_IID_CTO 0xc /* Character Time Out */ 456 #define UIC_IP 0x1 /* XXX-no?-XXX Interrupt Pending */ 457 #define UART_FIFO_CONTROL 0x010 /* FIFO Control Register (W) */ 458 #define UFC_RFT_0 0x00 /* Receiver FIFO Threshold of 0 chars */ 459 #define UFC_RFT_4 0x40 /* Receiver FIFO Threshold of 4 chars */ 460 #define UFC_RFT_8 0x80 /* Receiver FIFO Threshold of 8 chars */ 461 #define UFC_RFT_12 0xc0 /* Receiver FIFO Threshold of 12 chars */ 462 #define UFC_TFT_0 0x00 /* Transmit FIFO Threshold of 0 chars */ 463 #define UFC_TFT_4 0x10 /* Transmit FIFO Threshold of 4 chars */ 464 #define UFC_TFT_8 0x20 /* Transmit FIFO Threshold of 8 chars */ 465 #define UFC_TFT_12 0x30 /* Transmit FIFO Threshold of 12 chars */ 466 #define UFC_MS 0x08 /* Mode Select */ 467 #define UFC_TR 0x04 /* Transmitter Reset */ 468 #define UFC_RR 0x02 /* Receiver Reset */ 469 #define UFC_FE 0x01 /* FIFO Enable */ 470 #define UART_LINE_CONTROL 0x014 /* Line Control Register (R/W) */ 471 #define ULC_SB 0x40 /* Send Break */ 472 #define ULC_PAR_MASK 0x30 /* mask for PARity select */ 473 #define ULC_PAR_ODD 0x00 /* odd parity */ 474 #define ULC_PAR_EVEN 0x10 /* even parity */ 475 #define ULC_PAR_MARK 0x20 /* mark parity */ 476 #define ULC_PAR_ZERO 0x30 /* zero parity */ 477 #define ULC_PE 0x08 /* Parity Enable */ 478 #define ULC_ST 0x04 /* 1.5 or 2 stop bits */ 479 #define ULC_WLS_MASK 0x03 /* mask for Word Length Select */ 480 #define ULC_WLS_5 0x00 /* 5 bits per serial word */ 481 #define ULC_WLS_6 0x01 /* 6 bits */ 482 #define ULC_WLS_7 0x02 /* 7 bits */ 483 #define ULC_WLS_8 0x03 /* 8 bits */ 484 #define UART_MODEM_CONTROL 0x018 /* Modem Line Control Register (UART 4 only) (R/W) */ 485 #define UMC_LB 0x10 /* Loop Back */ 486 #define UMC_X2 0x08 /* eXternal line 2 state */ 487 #define UMC_X1 0x04 /* eXternal line 1 state */ 488 #define UMC_RT 0x02 /* Request To send */ 489 #define UMC_DT 0x01 /* Data Terminal ready */ 490 #define UART_LINE_STATUS 0x01c /* Line Status Register (R/W) */ 491 #define ULS_RF 0x80 /* Receiver FIFO contains error */ 492 #define ULS_TE 0x40 /* Transmit shift register Empty */ 493 #define ULS_TFE 0x20 /* Transmit FIFO Empty */ 494 #define ULS_BI 0x10 /* Break Indication */ 495 #define ULS_FE 0x08 /* Framing Error */ 496 #define ULS_PE 0x04 /* Parity Error */ 497 #define ULS_OE 0x02 /* Overrun Error */ 498 #define ULS_DR 0x01 /* Data Ready */ 499 #define ULS_RCV_MASK 0x1f /* mask for incoming data or error */ 500 #define UART_MODEM_STATUS 0x020 /* Modem Line Status Register (UART 4 only) (R/W) */ 501 #define UMS_CD 0x80 /* data Carrier Detect */ 502 #define UMS_RI 0x40 /* Ring Indication */ 503 #define UMS_DS 0x20 /* Data Set ready */ 504 #define UMS_CT 0x10 /* Clear To send */ 505 #define UMS_DD 0x08 /* Delta DCD */ 506 #define UMS_TRI 0x04 /* Terminate Ring Indication */ 507 #define UMS_DR 0x02 /* Delta DSR */ 508 #define UMS_DC 0x01 /* Delta CTS */ 509 #define UART_CLOCK_DIVIDER 0x028 /* Baud Rate Clock Divider (16bit) */ 510 #define UART_MODULE_CONTROL 0x100 /* Module Control Register */ 511 #define UMC_CE 0x2 /* Module Clock Enable */ 512 #define UMC_ME 0x1 /* Module Enable */ 513 514 #define UART_SIZE 0x104 515 516 /************************************************************************/ 517 /************************* SSI registers ****************************/ 518 /************************************************************************/ 519 #define SSI0_BASE 0x11600000 520 #define SSI1_BASE 0x11680000 521 522 /************************************************************************/ 523 /************************ GPIO2 registers ***************************/ 524 /************************************************************************/ 525 #define GPIO2_BASE 0x11700000 526 527 /************************************************************************/ 528 /****************** Programmable Counter registers ******************/ 529 /************************************************************************/ 530 531 #define SYS_BASE 0x11900000 532 533 #define PC_BASE SYS_BASE 534 535 #define PC_TRIM0 0x00 /* PC0 Divide (16 bits) */ 536 #define PC_COUNTER_WRITE0 0x04 /* set PC0 */ 537 #define PC_MATCH0_0 0x08 /* match counter & interrupt */ 538 #define PC_MATCH1_0 0x0c /* match counter & interrupt */ 539 #define PC_MATCH2_0 0x10 /* match counter & interrupt */ 540 #define PC_COUNTER_CONTROL 0x14 /* Programmable Counter Control */ 541 #define CC_E1S 0x00800000 /* Enable PC1 write status */ 542 #define CC_T1S 0x00100000 /* Trim PC1 write status */ 543 #define CC_M21 0x00080000 /* Match 2 of PC1 write status */ 544 #define CC_M11 0x00040000 /* Match 1 of PC1 write status */ 545 #define CC_M01 0x00020000 /* Match 0 of PC1 write status */ 546 #define CC_C1S 0x00010000 /* PC1 write status */ 547 #define CC_BP 0x00004000 /* Bypass OSC (use GPIO1) */ 548 #define CC_EN1 0x00002000 /* Enable PC1 */ 549 #define CC_BT1 0x00001000 /* Bypass Trim on PC1 */ 550 #define CC_EN0 0x00000800 /* Enable PC0 */ 551 #define CC_BT0 0x00000400 /* Bypass Trim on PC0 */ 552 #define CC_EO 0x00000100 /* Enable Oscillator */ 553 #define CC_E0S 0x00000080 /* Enable PC0 write status */ 554 #define CC_32S 0x00000020 /* 32.768kHz OSC status */ 555 #define CC_T0S 0x00000010 /* Trim PC0 write status */ 556 #define CC_M20 0x00000008 /* Match 2 of PC0 write status */ 557 #define CC_M10 0x00000004 /* Match 1 of PC0 write status */ 558 #define CC_M00 0x00000002 /* Match 0 of PC0 write status */ 559 #define CC_C0S 0x00000001 /* PC0 write status */ 560 #define PC_COUNTER_READ_0 0x40 /* get PC0 */ 561 #define PC_TRIM1 0x44 /* PC1 Divide (16 bits) */ 562 #define PC_COUNTER_WRITE1 0x48 /* set PC1 */ 563 #define PC_MATCH0_1 0x4c /* match counter & interrupt */ 564 #define PC_MATCH1_1 0x50 /* match counter & interrupt */ 565 #define PC_MATCH2_1 0x54 /* match counter & interrupt */ 566 #define PC_COUNTER_READ_1 0x58 /* get PC1 */ 567 568 #define PC_SIZE 0x5c /* size of register set */ 569 #define PC_RATE 32768 /* counter rate is 32.768kHz */ 570 571 /************************************************************************/ 572 /******************* Frequency Generator Registers ******************/ 573 /************************************************************************/ 574 575 #define SYS_FREQCTRL0 (SYS_BASE + 0x20) 576 #define SFC_FRDIV2(f) (f<<22) /* 29:22. Freq Divider 2 */ 577 #define SFC_FE2 (1<<21) /* Freq generator output enable 2 */ 578 #define SFC_FS2 (1<<20) /* Freq generator source 2 */ 579 #define SFC_FRDIV1(f) (f<<12) /* 19:12. Freq Divider 1 */ 580 #define SFC_FE1 (1<<11) /* Freq generator output enable 1 */ 581 #define SFC_FS1 (1<<10) /* Freq generator source 1 */ 582 #define SFC_FRDIV0(f) (f<<2) /* 9:2. Freq Divider 0 */ 583 #define SFC_FE0 2 /* Freq generator output enable 0 */ 584 #define SFC_FS0 1 /* Freq generator source 0 */ 585 586 #define SYS_FREQCTRL1 (SYS_BASE + 0x24) 587 #define SFC_FRDIV5(f) (f<<22) /* 29:22. Freq Divider 5 */ 588 #define SFC_FE5 (1<<21) /* Freq generator output enable 5 */ 589 #define SFC_FS5 (1<<20) /* Freq generator source 5 */ 590 #define SFC_FRDIV4(f) (f<<12) /* 19:12. Freq Divider 4 */ 591 #define SFC_FE4 (1<<11) /* Freq generator output enable 4 */ 592 #define SFC_FS4 (1<<10) /* Freq generator source 4 */ 593 #define SFC_FRDIV3(f) (f<<2) /* 9:2. Freq Divider 3 */ 594 #define SFC_FE3 2 /* Freq generator output enable 3 */ 595 #define SFC_FS3 1 /* Freq generator source 3 */ 596 597 /************************************************************************/ 598 /****************** Clock Source Control Registers ******************/ 599 /************************************************************************/ 600 601 #define SYS_CLKSRC (SYS_BASE + 0x28) 602 #define SCS_ME1(n) (n<<27) /* EXTCLK1 Clock Mux input select */ 603 #define SCS_ME0(n) (n<<22) /* EXTCLK0 Clock Mux input select */ 604 #define SCS_MPC(n) (n<<17) /* PCI clock mux input select */ 605 #define SCS_MUH(n) (n<<12) /* USB Host clock mux input select */ 606 #define SCS_MUD(n) (n<<7) /* USB Device clock mux input select */ 607 #define SCS_MEx_AUX 0x1 /* Aux clock */ 608 #define SCS_MEx_FREQ0 0x2 /* FREQ0 */ 609 #define SCS_MEx_FREQ1 0x3 /* FREQ1 */ 610 #define SCS_MEx_FREQ2 0x4 /* FREQ2 */ 611 #define SCS_MEx_FREQ3 0x5 /* FREQ3 */ 612 #define SCS_MEx_FREQ4 0x6 /* FREQ4 */ 613 #define SCS_MEx_FREQ5 0x7 /* FREQ5 */ 614 #define SCS_DE1 (1<<26) /* EXTCLK1 clock divider select */ 615 #define SCS_CE1 (1<<25) /* EXTCLK1 clock select */ 616 #define SCS_DE0 (1<<21) /* EXTCLK0 clock divider select */ 617 #define SCS_CE0 (1<<20) /* EXTCLK0 clock select */ 618 #define SCS_DPC (1<<16) /* PCI clock divider select */ 619 #define SCS_CPC (1<<15) /* PCI clock select */ 620 #define SCS_DUH (1<<11) /* USB Host clock divider select */ 621 #define SCS_CUH (1<<10) /* USB Host clock select */ 622 #define SCS_DUD (1<<6) /* USB Device clock divider select */ 623 #define SCS_CUD (1<<5) /* USB Device clock select */ 624 625 /************************************************************************/ 626 /*************************** PLL Control *****************************/ 627 /************************************************************************/ 628 629 #define SYS_CPUPLL (SYS_BASE + 0x60) 630 #define SYS_AUXPLL (SYS_BASE + 0x64) 631