1 /* $NetBSD: if_aumac.c,v 1.17 2006/05/05 18:04:41 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.17 2006/05/05 18:04:41 thorpej Exp $"); 50 51 #include "bpfilter.h" 52 #include "rnd.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/callout.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/queue.h> 65 66 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 #if NRND > 0 77 #include <sys/rnd.h> 78 #endif 79 80 #include <machine/bus.h> 81 #include <machine/intr.h> 82 #include <machine/endian.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <mips/alchemy/include/aureg.h> 88 #include <mips/alchemy/include/auvar.h> 89 #include <mips/alchemy/include/aubusvar.h> 90 #include <mips/alchemy/dev/if_aumacreg.h> 91 92 /* 93 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 94 * must consist of a single DMA segment, and must be aligned to a 2K 95 * boundary. Therefore, this driver does not perform DMA directly 96 * to/from mbufs. Instead, we copy the data to/from buffers allocated 97 * at device attach time. 98 * 99 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 100 * there's little point in not making assumptions based on the CPU type. 101 * We also program the Au1X00 cache to be DMA coherent, so the buffers 102 * are accessed via KSEG0 addresses. 103 */ 104 #define AUMAC_NTXDESC 4 105 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 106 107 #define AUMAC_NRXDESC 4 108 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 109 110 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 111 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 112 113 #define AUMAC_TXBUF_OFFSET 0 114 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 115 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 116 117 struct aumac_buf { 118 caddr_t buf_vaddr; /* virtual address of buffer */ 119 bus_addr_t buf_paddr; /* DMA address of buffer */ 120 }; 121 122 /* 123 * Software state per device. 124 */ 125 struct aumac_softc { 126 struct device sc_dev; /* generic device information */ 127 bus_space_tag_t sc_st; /* bus space tag */ 128 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 129 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 130 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 131 struct ethercom sc_ethercom; /* Ethernet common data */ 132 void *sc_sdhook; /* shutdown hook */ 133 134 void *sc_ih; /* interrupt cookie */ 135 136 struct mii_data sc_mii; /* MII/media information */ 137 138 struct callout sc_tick_ch; /* tick callout */ 139 140 /* Transmit and receive buffers */ 141 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 142 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 143 caddr_t sc_bufaddr; 144 145 int sc_txfree; /* number of free Tx descriptors */ 146 int sc_txnext; /* next Tx descriptor to use */ 147 int sc_txdirty; /* first dirty Tx descriptor */ 148 149 int sc_rxptr; /* next ready Rx descriptor */ 150 151 #if NRND > 0 152 rndsource_element_t rnd_source; 153 #endif 154 155 #ifdef AUMAC_EVENT_COUNTERS 156 struct evcnt sc_ev_txstall; /* Tx stalled */ 157 struct evcnt sc_ev_rxstall; /* Rx stalled */ 158 struct evcnt sc_ev_txintr; /* Tx interrupts */ 159 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 160 #endif 161 162 uint32_t sc_control; /* MAC_CONTROL contents */ 163 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 164 }; 165 166 #ifdef AUMAC_EVENT_COUNTERS 167 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 168 #else 169 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 170 #endif 171 172 #define AUMAC_INIT_RXDESC(sc, x) \ 173 do { \ 174 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 175 MACDMA_RX_STAT((x)), 0); \ 176 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 177 MACDMA_RX_ADDR((x)), \ 178 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 179 } while (/*CONSTCOND*/0) 180 181 static void aumac_start(struct ifnet *); 182 static void aumac_watchdog(struct ifnet *); 183 static int aumac_ioctl(struct ifnet *, u_long, caddr_t); 184 static int aumac_init(struct ifnet *); 185 static void aumac_stop(struct ifnet *, int); 186 187 static void aumac_shutdown(void *); 188 189 static void aumac_tick(void *); 190 191 static void aumac_set_filter(struct aumac_softc *); 192 193 static void aumac_powerup(struct aumac_softc *); 194 static void aumac_powerdown(struct aumac_softc *); 195 196 static int aumac_intr(void *); 197 static int aumac_txintr(struct aumac_softc *); 198 static int aumac_rxintr(struct aumac_softc *); 199 200 static int aumac_mii_readreg(struct device *, int, int); 201 static void aumac_mii_writereg(struct device *, int, int, int); 202 static void aumac_mii_statchg(struct device *); 203 static int aumac_mii_wait(struct aumac_softc *, const char *); 204 205 static int aumac_mediachange(struct ifnet *); 206 static void aumac_mediastatus(struct ifnet *, struct ifmediareq *); 207 208 static int aumac_match(struct device *, struct cfdata *, void *); 209 static void aumac_attach(struct device *, struct device *, void *); 210 211 int aumac_copy_small = 0; 212 213 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 214 aumac_match, aumac_attach, NULL, NULL); 215 216 static int 217 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 218 { 219 struct aubus_attach_args *aa = aux; 220 221 if (strcmp(aa->aa_name, cf->cf_name) == 0) 222 return (1); 223 224 return (0); 225 } 226 227 static void 228 aumac_attach(struct device *parent, struct device *self, void *aux) 229 { 230 const uint8_t *enaddr; 231 prop_data_t ea; 232 struct aumac_softc *sc = (void *) self; 233 struct aubus_attach_args *aa = aux; 234 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 235 struct pglist pglist; 236 paddr_t bufaddr; 237 caddr_t vbufaddr; 238 int i; 239 240 callout_init(&sc->sc_tick_ch); 241 242 printf(": Au1X00 10/100 Ethernet\n"); 243 244 sc->sc_st = aa->aa_st; 245 246 /* Get the MAC address. */ 247 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 248 if (ea == NULL) { 249 printf("%s: unable to get mac-addr property\n", 250 sc->sc_dev.dv_xname); 251 return; 252 } 253 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 254 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 255 enaddr = prop_data_data_nocopy(ea); 256 257 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 258 ether_sprintf(enaddr)); 259 260 /* Map the device. */ 261 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 262 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 263 printf("%s: unable to map MAC registers\n", 264 sc->sc_dev.dv_xname); 265 return; 266 } 267 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 268 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 269 printf("%s: unable to map MACEN registers\n", 270 sc->sc_dev.dv_xname); 271 return; 272 } 273 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 274 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 275 printf("%s: unable to map MACDMA registers\n", 276 sc->sc_dev.dv_xname); 277 return; 278 } 279 280 /* Make sure the MAC is powered off. */ 281 aumac_powerdown(sc); 282 283 /* Hook up the interrupt handler. */ 284 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 285 aumac_intr, sc); 286 if (sc->sc_ih == NULL) { 287 printf("%s: unable to register interrupt handler\n", 288 sc->sc_dev.dv_xname); 289 return; 290 } 291 292 /* 293 * Allocate space for the transmit and receive buffers. 294 */ 295 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 296 &pglist, 1, 0)) 297 return; 298 299 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 300 vbufaddr = (void *)MIPS_PHYS_TO_KSEG0(bufaddr); 301 302 for (i = 0; i < AUMAC_NTXDESC; i++) { 303 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 304 305 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 306 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 307 } 308 309 for (i = 0; i < AUMAC_NRXDESC; i++) { 310 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 311 312 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 313 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 314 } 315 316 /* 317 * Power up the MAC before accessing any MAC registers (including 318 * MII configuration. 319 */ 320 aumac_powerup(sc); 321 322 /* 323 * Initialize the media structures and probe the MII. 324 */ 325 sc->sc_mii.mii_ifp = ifp; 326 sc->sc_mii.mii_readreg = aumac_mii_readreg; 327 sc->sc_mii.mii_writereg = aumac_mii_writereg; 328 sc->sc_mii.mii_statchg = aumac_mii_statchg; 329 ifmedia_init(&sc->sc_mii.mii_media, 0, aumac_mediachange, 330 aumac_mediastatus); 331 332 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 333 MII_OFFSET_ANY, 0); 334 335 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 336 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 337 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 338 } else 339 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 340 341 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 342 ifp->if_softc = sc; 343 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 344 ifp->if_ioctl = aumac_ioctl; 345 ifp->if_start = aumac_start; 346 ifp->if_watchdog = aumac_watchdog; 347 ifp->if_init = aumac_init; 348 ifp->if_stop = aumac_stop; 349 IFQ_SET_READY(&ifp->if_snd); 350 351 /* Attach the interface. */ 352 if_attach(ifp); 353 ether_ifattach(ifp, enaddr); 354 355 #if NRND > 0 356 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 357 RND_TYPE_NET, 0); 358 #endif 359 360 #ifdef AUMAC_EVENT_COUNTERS 361 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 362 NULL, sc->sc_dev.dv_xname, "txstall"); 363 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 364 NULL, sc->sc_dev.dv_xname, "rxstall"); 365 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 366 NULL, sc->sc_dev.dv_xname, "txintr"); 367 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 368 NULL, sc->sc_dev.dv_xname, "rxintr"); 369 #endif 370 371 /* Make sure the interface is shutdown during reboot. */ 372 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 373 if (sc->sc_sdhook == NULL) 374 printf("%s: WARNING: unable to establish shutdown hook\n", 375 sc->sc_dev.dv_xname); 376 return; 377 } 378 379 /* 380 * aumac_shutdown: 381 * 382 * Make sure the interface is stopped at reboot time. 383 */ 384 static void 385 aumac_shutdown(void *arg) 386 { 387 struct aumac_softc *sc = arg; 388 389 aumac_stop(&sc->sc_ethercom.ec_if, 1); 390 391 /* 392 * XXX aumac_stop leaves device powered up at the moment 393 * XXX but this still isn't enough to keep yamon happy... :-( 394 */ 395 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 396 } 397 398 /* 399 * aumac_start: [ifnet interface function] 400 * 401 * Start packet transmission on the interface. 402 */ 403 static void 404 aumac_start(struct ifnet *ifp) 405 { 406 struct aumac_softc *sc = ifp->if_softc; 407 struct mbuf *m; 408 int nexttx; 409 410 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 411 return; 412 413 /* 414 * Loop through the send queue, setting up transmit descriptors 415 * unitl we drain the queue, or use up all available transmit 416 * descriptors. 417 */ 418 for (;;) { 419 /* Grab a packet off the queue. */ 420 IFQ_POLL(&ifp->if_snd, m); 421 if (m == NULL) 422 return; 423 424 /* Get a spare descriptor. */ 425 if (sc->sc_txfree == 0) { 426 /* No more slots left; notify upper layer. */ 427 ifp->if_flags |= IFF_OACTIVE; 428 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 429 return; 430 } 431 nexttx = sc->sc_txnext; 432 433 IFQ_DEQUEUE(&ifp->if_snd, m); 434 435 /* 436 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 437 */ 438 439 m_copydata(m, 0, m->m_pkthdr.len, 440 sc->sc_txbufs[nexttx].buf_vaddr); 441 442 /* Zero out the remainder of any short packets. */ 443 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 444 memset(sc->sc_txbufs[nexttx].buf_vaddr + 445 m->m_pkthdr.len, 0, 446 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 447 448 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 449 MACDMA_TX_STAT(nexttx), 0); 450 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 451 MACDMA_TX_LEN(nexttx), 452 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 453 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 454 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 455 MACDMA_TX_ADDR(nexttx), 456 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 457 /* XXX - needed?? we should be coherent */ 458 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 459 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 460 461 /* Advance the Tx pointer. */ 462 sc->sc_txfree--; 463 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 464 465 #if NBPFILTER > 0 466 /* Pass the packet to any BPF listeners. */ 467 if (ifp->if_bpf) 468 bpf_mtap(ifp->if_bpf, m); 469 #endif /* NBPFILTER */ 470 471 m_freem(m); 472 473 /* Set a watchdog timer in case the chip flakes out. */ 474 ifp->if_timer = 5; 475 } 476 /* NOTREACHED */ 477 } 478 479 /* 480 * aumac_watchdog: [ifnet interface function] 481 * 482 * Watchdog timer handler. 483 */ 484 static void 485 aumac_watchdog(struct ifnet *ifp) 486 { 487 struct aumac_softc *sc = ifp->if_softc; 488 489 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 490 (void) aumac_init(ifp); 491 492 /* Try to get more packets going. */ 493 aumac_start(ifp); 494 } 495 496 /* 497 * aumac_ioctl: [ifnet interface function] 498 * 499 * Handle control requests from the operator. 500 */ 501 static int 502 aumac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 503 { 504 struct aumac_softc *sc = ifp->if_softc; 505 struct ifreq *ifr = (struct ifreq *) data; 506 int s, error; 507 508 s = splnet(); 509 510 switch (cmd) { 511 case SIOCSIFMEDIA: 512 case SIOCGIFMEDIA: 513 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 514 break; 515 516 default: 517 error = ether_ioctl(ifp, cmd, data); 518 if (error == ENETRESET) { 519 /* 520 * Multicast list has changed; set the hardware filter 521 * accordingly. 522 */ 523 if (ifp->if_flags & IFF_RUNNING) 524 aumac_set_filter(sc); 525 } 526 break; 527 } 528 529 /* Try to get more packets going. */ 530 aumac_start(ifp); 531 532 splx(s); 533 return (error); 534 } 535 536 /* 537 * aumac_intr: 538 * 539 * Interrupt service routine. 540 */ 541 static int 542 aumac_intr(void *arg) 543 { 544 struct aumac_softc *sc = arg; 545 int status; 546 547 /* 548 * There aren't really any interrupt status bits on the 549 * Au1X00 MAC, and each MAC has a dedicated interrupt 550 * in the CPU's built-in interrupt controller. Just 551 * check for new incoming packets, and then Tx completions 552 * (for status updating). 553 */ 554 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 555 return (0); 556 557 status = aumac_rxintr(sc); 558 status += aumac_txintr(sc); 559 560 #if NRND > 0 561 if (RND_ENABLED(&sc->rnd_source)) 562 rnd_add_uint32(&sc->rnd_source, status); 563 #endif 564 565 return status; 566 } 567 568 /* 569 * aumac_txintr: 570 * 571 * Helper; handle transmit interrupts. 572 */ 573 static int 574 aumac_txintr(struct aumac_softc *sc) 575 { 576 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 577 uint32_t stat; 578 int i; 579 int pkts = 0; 580 581 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 582 i = AUMAC_NEXTTX(i)) { 583 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 584 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 585 break; 586 pkts++; 587 588 /* ACK interrupt. */ 589 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 590 MACDMA_TX_ADDR(i), 0); 591 592 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 593 MACDMA_TX_STAT(i)); 594 595 if (stat & TX_STAT_FA) { 596 /* XXX STATS */ 597 ifp->if_oerrors++; 598 } else 599 ifp->if_opackets++; 600 601 if (stat & TX_STAT_EC) 602 ifp->if_collisions += 16; 603 else 604 ifp->if_collisions += TX_STAT_CC(stat); 605 606 sc->sc_txfree++; 607 ifp->if_flags &= ~IFF_OACTIVE; 608 609 /* Try to queue more packets. */ 610 aumac_start(ifp); 611 } 612 613 if (pkts) 614 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 615 616 /* Update the dirty descriptor pointer. */ 617 sc->sc_txdirty = i; 618 619 /* 620 * If there are no more pending transmissions, cancel the watchdog 621 * timer. 622 */ 623 if (sc->sc_txfree == AUMAC_NTXDESC) 624 ifp->if_timer = 0; 625 626 return pkts; 627 } 628 629 /* 630 * aumac_rxintr: 631 * 632 * Helper; handle receive interrupts. 633 */ 634 static int 635 aumac_rxintr(struct aumac_softc *sc) 636 { 637 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 638 struct mbuf *m; 639 uint32_t stat; 640 int i, len; 641 int pkts = 0; 642 643 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 644 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 645 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 646 break; 647 pkts++; 648 649 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 650 MACDMA_RX_STAT(i)); 651 652 #define PRINTERR(str) \ 653 do { \ 654 error++; \ 655 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 656 } while (0) 657 658 if (stat & RX_STAT_ERRS) { 659 int error = 0; 660 661 if (stat & RX_STAT_MI) 662 PRINTERR("missed frame"); 663 if (stat & RX_STAT_UC) 664 PRINTERR("unknown control frame"); 665 if (stat & RX_STAT_LE) 666 PRINTERR("short frame"); 667 if (stat & RX_STAT_CR) 668 PRINTERR("CRC error"); 669 if (stat & RX_STAT_ME) 670 PRINTERR("medium error"); 671 if (stat & RX_STAT_CS) 672 PRINTERR("late collision"); 673 if (stat & RX_STAT_FL) 674 PRINTERR("frame too big"); 675 if (stat & RX_STAT_RF) 676 PRINTERR("runt frame (collision)"); 677 if (stat & RX_STAT_WT) 678 PRINTERR("watch dog"); 679 if (stat & RX_STAT_DB) { 680 if (stat & (RX_STAT_CS | RX_STAT_RF | 681 RX_STAT_CR)) { 682 if (!error) 683 goto pktok; 684 } else 685 PRINTERR("dribbling bit"); 686 } 687 #undef PRINTERR 688 ifp->if_ierrors++; 689 690 dropit: 691 /* reuse the current descriptor */ 692 AUMAC_INIT_RXDESC(sc, i); 693 continue; 694 } 695 pktok: 696 len = RX_STAT_L(stat); 697 698 /* 699 * The Au1X00 MAC includes the CRC with every packet; 700 * trim it off here. 701 */ 702 len -= ETHER_CRC_LEN; 703 704 /* 705 * Truncate the packet if it's too big to fit in 706 * a single mbuf cluster. 707 */ 708 if (len > MCLBYTES - 2) 709 len = MCLBYTES - 2; 710 711 MGETHDR(m, M_DONTWAIT, MT_DATA); 712 if (m == NULL) { 713 printf("%s: unable to allocate Rx mbuf\n", 714 sc->sc_dev.dv_xname); 715 goto dropit; 716 } 717 if (len > MHLEN - 2) { 718 MCLGET(m, M_DONTWAIT); 719 if ((m->m_flags & M_EXT) == 0) { 720 printf("%s: unable to allocate Rx cluster\n", 721 sc->sc_dev.dv_xname); 722 m_freem(m); 723 goto dropit; 724 } 725 } 726 727 m->m_data += 2; /* align payload */ 728 memcpy(mtod(m, caddr_t), 729 sc->sc_rxbufs[i].buf_vaddr, len); 730 AUMAC_INIT_RXDESC(sc, i); 731 732 m->m_pkthdr.rcvif = ifp; 733 m->m_pkthdr.len = m->m_len = len; 734 735 #if NBPFILTER > 0 736 /* Pass this up to any BPF listeners. */ 737 if (ifp->if_bpf) 738 bpf_mtap(ifp->if_bpf, m); 739 #endif /* NBPFILTER > 0 */ 740 741 /* Pass it on. */ 742 (*ifp->if_input)(ifp, m); 743 ifp->if_ipackets++; 744 } 745 if (pkts) 746 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 747 if (pkts == AUMAC_NRXDESC) 748 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 749 750 /* Update the receive pointer. */ 751 sc->sc_rxptr = i; 752 753 return pkts; 754 } 755 756 /* 757 * aumac_tick: 758 * 759 * One second timer, used to tick the MII. 760 */ 761 static void 762 aumac_tick(void *arg) 763 { 764 struct aumac_softc *sc = arg; 765 int s; 766 767 s = splnet(); 768 mii_tick(&sc->sc_mii); 769 splx(s); 770 771 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 772 } 773 774 /* 775 * aumac_init: [ifnet interface function] 776 * 777 * Initialize the interface. Must be called at splnet(). 778 */ 779 static int 780 aumac_init(struct ifnet *ifp) 781 { 782 struct aumac_softc *sc = ifp->if_softc; 783 int i, error = 0; 784 785 /* Cancel any pending I/O, reset MAC. */ 786 aumac_stop(ifp, 0); 787 788 /* Set up the transmit ring. */ 789 for (i = 0; i < AUMAC_NTXDESC; i++) { 790 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 791 MACDMA_TX_STAT(i), 0); 792 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 793 MACDMA_TX_LEN(i), 0); 794 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 795 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 796 } 797 sc->sc_txfree = AUMAC_NTXDESC; 798 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 799 MACDMA_TX_ADDR(0))); 800 sc->sc_txdirty = sc->sc_txnext; 801 802 /* Set up the receive ring. */ 803 for (i = 0; i < AUMAC_NRXDESC; i++) 804 AUMAC_INIT_RXDESC(sc, i); 805 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 806 MACDMA_RX_ADDR(0))); 807 808 /* 809 * Power up the MAC. 810 */ 811 aumac_powerup(sc); 812 813 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 814 #if _BYTE_ORDER == _BIG_ENDIAN 815 sc->sc_control |= CONTROL_EM; 816 #endif 817 818 /* Set the media. */ 819 aumac_mediachange(ifp); 820 821 /* 822 * Set the receive filter. This will actually start the transmit 823 * and receive processes. 824 */ 825 aumac_set_filter(sc); 826 827 /* Start the one second clock. */ 828 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 829 830 /* ...all done! */ 831 ifp->if_flags |= IFF_RUNNING; 832 ifp->if_flags &= ~IFF_OACTIVE; 833 834 if (error) 835 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 836 return (error); 837 } 838 839 /* 840 * aumac_stop: [ifnet interface function] 841 * 842 * Stop transmission on the interface. 843 */ 844 static void 845 aumac_stop(struct ifnet *ifp, int disable) 846 { 847 struct aumac_softc *sc = ifp->if_softc; 848 849 /* Stop the one-second clock. */ 850 callout_stop(&sc->sc_tick_ch); 851 852 /* Down the MII. */ 853 mii_down(&sc->sc_mii); 854 855 /* Stop the transmit and receive processes. */ 856 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 857 858 /* Power down/reset the MAC. */ 859 aumac_powerdown(sc); 860 861 /* Mark the interface as down and cancel the watchdog timer. */ 862 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 863 ifp->if_timer = 0; 864 } 865 866 /* 867 * aumac_powerdown: 868 * 869 * Power down the MAC. 870 */ 871 static void 872 aumac_powerdown(struct aumac_softc *sc) 873 { 874 875 /* Disable the MAC clocks, and place the device in reset. */ 876 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 877 878 // delay(10000); 879 } 880 881 /* 882 * aumac_powerup: 883 * 884 * Bring the device out of reset. 885 */ 886 static void 887 aumac_powerup(struct aumac_softc *sc) 888 { 889 890 /* Enable clocks to the MAC. */ 891 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 892 893 /* Enable MAC, coherent transactions, pass only valid frames. */ 894 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 895 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 896 897 delay(20000); 898 } 899 900 /* 901 * aumac_set_filter: 902 * 903 * Set up the receive filter. 904 */ 905 static void 906 aumac_set_filter(struct aumac_softc *sc) 907 { 908 struct ethercom *ec = &sc->sc_ethercom; 909 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 910 struct ether_multi *enm; 911 struct ether_multistep step; 912 const uint8_t *enaddr = LLADDR(ifp->if_sadl); 913 uint32_t mchash[2], crc; 914 915 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 916 917 /* Stop the receiver. */ 918 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 919 sc->sc_control & ~CONTROL_RE); 920 921 if (ifp->if_flags & IFF_PROMISC) { 922 sc->sc_control |= CONTROL_PR; 923 goto allmulti; 924 } 925 926 /* Set the station address. */ 927 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 928 enaddr[4] | (enaddr[5] << 8)); 929 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 930 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 931 (enaddr[3] << 24)); 932 933 sc->sc_control |= CONTROL_HP; 934 935 mchash[0] = mchash[1] = 0; 936 937 /* 938 * Set up the multicast address filter by passing all multicast 939 * addresses through a CRC generator, and then using the high 940 * order 6 bits as an index into the 64-bit multicast hash table. 941 * The high order bits select the word, while the rest of the bits 942 * select the bit within the word. 943 */ 944 ETHER_FIRST_MULTI(step, ec, enm); 945 while (enm != NULL) { 946 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 947 /* 948 * We must listen to a range of multicast addresses. 949 * For now, just accept all multicasts, rather than 950 * trying to set only those filter bits needed to match 951 * the range. (At this time, the only use of address 952 * ranges is for IP multicast routing, for which the 953 * range is large enough to require all bits set.) 954 */ 955 goto allmulti; 956 } 957 958 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 959 960 /* Just want the 6 most significant bits. */ 961 crc >>= 26; 962 963 /* Set the corresponding bit in the filter. */ 964 mchash[crc >> 5] |= 1U << (crc & 0x1f); 965 966 ETHER_NEXT_MULTI(step, enm); 967 } 968 969 ifp->if_flags &= ~IFF_ALLMULTI; 970 971 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 972 mchash[1]); 973 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 974 mchash[0]); 975 976 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 977 sc->sc_control); 978 return; 979 980 allmulti: 981 sc->sc_control |= CONTROL_PM; 982 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 983 sc->sc_control); 984 } 985 986 /* 987 * aumac_mediastatus: [ifmedia interface function] 988 * 989 * Get the current interface media status. 990 */ 991 static void 992 aumac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 993 { 994 struct aumac_softc *sc = ifp->if_softc; 995 996 mii_pollstat(&sc->sc_mii); 997 ifmr->ifm_status = sc->sc_mii.mii_media_status; 998 ifmr->ifm_active = sc->sc_mii.mii_media_active; 999 } 1000 1001 /* 1002 * aumac_mediachange: [ifmedia interface function] 1003 * 1004 * Set hardware to newly selected media. 1005 */ 1006 static int 1007 aumac_mediachange(struct ifnet *ifp) 1008 { 1009 struct aumac_softc *sc = ifp->if_softc; 1010 1011 if (ifp->if_flags & IFF_UP) 1012 mii_mediachg(&sc->sc_mii); 1013 return (0); 1014 } 1015 1016 /* 1017 * aumac_mii_wait: 1018 * 1019 * Wait for the MII interface to not be busy. 1020 */ 1021 static int 1022 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 1023 { 1024 int i; 1025 1026 for (i = 0; i < 10000; i++) { 1027 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 1028 MAC_MIICTRL) & MIICTRL_MB) == 0) 1029 return (0); 1030 delay(10); 1031 } 1032 1033 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 1034 return (1); 1035 } 1036 1037 /* 1038 * aumac_mii_readreg: [mii interface function] 1039 * 1040 * Read a PHY register on the MII. 1041 */ 1042 static int 1043 aumac_mii_readreg(struct device *self, int phy, int reg) 1044 { 1045 struct aumac_softc *sc = (void *) self; 1046 1047 if (aumac_mii_wait(sc, "become ready")) 1048 return (0); 1049 1050 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1051 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1052 1053 if (aumac_mii_wait(sc, "complete")) 1054 return (0); 1055 1056 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1057 MIIDATA_MASK); 1058 } 1059 1060 /* 1061 * aumac_mii_writereg: [mii interface function] 1062 * 1063 * Write a PHY register on the MII. 1064 */ 1065 static void 1066 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1067 { 1068 struct aumac_softc *sc = (void *) self; 1069 1070 if (aumac_mii_wait(sc, "become ready")) 1071 return; 1072 1073 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1074 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1075 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1076 1077 (void) aumac_mii_wait(sc, "complete"); 1078 } 1079 1080 /* 1081 * aumac_mii_statchg: [mii interface function] 1082 * 1083 * Callback from MII layer when media changes. 1084 */ 1085 static void 1086 aumac_mii_statchg(struct device *self) 1087 { 1088 struct aumac_softc *sc = (void *) self; 1089 1090 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1091 sc->sc_control |= CONTROL_F; 1092 else 1093 sc->sc_control &= ~CONTROL_F; 1094 1095 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1096 sc->sc_control); 1097 } 1098