1 /* $NetBSD: if_aumac.c,v 1.47 2019/05/28 07:41:47 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.47 2019/05/28 07:41:47 msaitoh Exp $"); 50 51 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/callout.h> 56 #include <sys/device.h> 57 #include <sys/endian.h> 58 #include <sys/errno.h> 59 #include <sys/intr.h> 60 #include <sys/ioctl.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/socket.h> 65 66 #include <uvm/uvm.h> /* for PAGE_SIZE */ 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #include <net/bpf.h> 74 #include <sys/rndsource.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <mips/alchemy/include/aureg.h> 80 #include <mips/alchemy/include/auvar.h> 81 #include <mips/alchemy/include/aubusvar.h> 82 #include <mips/alchemy/dev/if_aumacreg.h> 83 84 /* 85 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 86 * must consist of a single DMA segment, and must be aligned to a 2K 87 * boundary. Therefore, this driver does not perform DMA directly 88 * to/from mbufs. Instead, we copy the data to/from buffers allocated 89 * at device attach time. 90 * 91 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 92 * there's little point in not making assumptions based on the CPU type. 93 * We also program the Au1X00 cache to be DMA coherent, so the buffers 94 * are accessed via KSEG0 addresses. 95 */ 96 #define AUMAC_NTXDESC 4 97 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 98 99 #define AUMAC_NRXDESC 4 100 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 101 102 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 103 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 104 105 #define AUMAC_TXBUF_OFFSET 0 106 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 107 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 108 109 struct aumac_buf { 110 vaddr_t buf_vaddr; /* virtual address of buffer */ 111 bus_addr_t buf_paddr; /* DMA address of buffer */ 112 }; 113 114 /* 115 * Software state per device. 116 */ 117 struct aumac_softc { 118 device_t sc_dev; /* generic device information */ 119 bus_space_tag_t sc_st; /* bus space tag */ 120 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 121 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 122 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 123 struct ethercom sc_ethercom; /* Ethernet common data */ 124 void *sc_sdhook; /* shutdown hook */ 125 126 int sc_irq; 127 void *sc_ih; /* interrupt cookie */ 128 129 struct mii_data sc_mii; /* MII/media information */ 130 131 struct callout sc_tick_ch; /* tick callout */ 132 133 /* Transmit and receive buffers */ 134 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 135 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 136 void *sc_bufaddr; 137 138 int sc_txfree; /* number of free Tx descriptors */ 139 int sc_txnext; /* next Tx descriptor to use */ 140 int sc_txdirty; /* first dirty Tx descriptor */ 141 142 int sc_rxptr; /* next ready Rx descriptor */ 143 144 krndsource_t rnd_source; 145 146 #ifdef AUMAC_EVENT_COUNTERS 147 struct evcnt sc_ev_txstall; /* Tx stalled */ 148 struct evcnt sc_ev_rxstall; /* Rx stalled */ 149 struct evcnt sc_ev_txintr; /* Tx interrupts */ 150 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 151 #endif 152 153 uint32_t sc_control; /* MAC_CONTROL contents */ 154 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 155 }; 156 157 #ifdef AUMAC_EVENT_COUNTERS 158 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 159 #else 160 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 161 #endif 162 163 #define AUMAC_INIT_RXDESC(sc, x) \ 164 do { \ 165 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 166 MACDMA_RX_STAT((x)), 0); \ 167 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 168 MACDMA_RX_ADDR((x)), \ 169 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 170 } while (/*CONSTCOND*/0) 171 172 static void aumac_start(struct ifnet *); 173 static void aumac_watchdog(struct ifnet *); 174 static int aumac_ioctl(struct ifnet *, u_long, void *); 175 static int aumac_init(struct ifnet *); 176 static void aumac_stop(struct ifnet *, int); 177 178 static void aumac_shutdown(void *); 179 180 static void aumac_tick(void *); 181 182 static void aumac_set_filter(struct aumac_softc *); 183 184 static void aumac_powerup(struct aumac_softc *); 185 static void aumac_powerdown(struct aumac_softc *); 186 187 static int aumac_intr(void *); 188 static int aumac_txintr(struct aumac_softc *); 189 static int aumac_rxintr(struct aumac_softc *); 190 191 static int aumac_mii_readreg(device_t, int, int, uint16_t *); 192 static int aumac_mii_writereg(device_t, int, int, uint16_t); 193 static void aumac_mii_statchg(struct ifnet *); 194 static int aumac_mii_wait(struct aumac_softc *, const char *); 195 196 static int aumac_match(device_t, struct cfdata *, void *); 197 static void aumac_attach(device_t, device_t, void *); 198 199 int aumac_copy_small = 0; 200 201 CFATTACH_DECL_NEW(aumac, sizeof(struct aumac_softc), 202 aumac_match, aumac_attach, NULL, NULL); 203 204 static int 205 aumac_match(device_t parent, struct cfdata *cf, void *aux) 206 { 207 struct aubus_attach_args *aa = aux; 208 209 if (strcmp(aa->aa_name, cf->cf_name) == 0) 210 return 1; 211 212 return 0; 213 } 214 215 static void 216 aumac_attach(device_t parent, device_t self, void *aux) 217 { 218 const uint8_t *enaddr; 219 prop_data_t ea; 220 struct aumac_softc *sc = device_private(self); 221 struct aubus_attach_args *aa = aux; 222 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 223 struct mii_data * const mii = &sc->sc_mii; 224 struct pglist pglist; 225 paddr_t bufaddr; 226 vaddr_t vbufaddr; 227 int i; 228 229 callout_init(&sc->sc_tick_ch, 0); 230 231 aprint_normal(": Au1X00 10/100 Ethernet\n"); 232 aprint_naive("\n"); 233 234 sc->sc_dev = self; 235 sc->sc_st = aa->aa_st; 236 237 /* Get the MAC address. */ 238 ea = prop_dictionary_get(device_properties(self), "mac-address"); 239 if (ea == NULL) { 240 aprint_error_dev(self, "unable to get mac-addr property\n"); 241 return; 242 } 243 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 244 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 245 enaddr = prop_data_data_nocopy(ea); 246 247 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 248 249 /* Map the device. */ 250 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 251 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 252 aprint_error_dev(self, "unable to map MAC registers\n"); 253 return; 254 } 255 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 256 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 257 aprint_error_dev(self, "unable to map MACEN registers\n"); 258 return; 259 } 260 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 261 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 262 aprint_error_dev(self, "unable to map MACDMA registers\n"); 263 return; 264 } 265 266 /* Make sure the MAC is powered off. */ 267 aumac_powerdown(sc); 268 269 /* Hook up the interrupt handler. */ 270 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 271 aumac_intr, sc); 272 if (sc->sc_ih == NULL) { 273 aprint_error_dev(self, 274 "unable to register interrupt handler\n"); 275 return; 276 } 277 sc->sc_irq = aa->aa_irq[0]; 278 au_intr_disable(sc->sc_irq); 279 280 /* 281 * Allocate space for the transmit and receive buffers. 282 */ 283 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 284 &pglist, 1, 0)) 285 return; 286 287 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 288 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 289 290 for (i = 0; i < AUMAC_NTXDESC; i++) { 291 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 292 293 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 294 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 295 } 296 297 for (i = 0; i < AUMAC_NRXDESC; i++) { 298 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 299 300 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 301 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 302 } 303 304 /* 305 * Power up the MAC before accessing any MAC registers (including 306 * MII configuration. 307 */ 308 aumac_powerup(sc); 309 310 /* 311 * Initialize the media structures and probe the MII. 312 */ 313 mii->mii_ifp = ifp; 314 mii->mii_readreg = aumac_mii_readreg; 315 mii->mii_writereg = aumac_mii_writereg; 316 mii->mii_statchg = aumac_mii_statchg; 317 sc->sc_ethercom.ec_mii = mii; 318 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 319 320 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, 321 MII_OFFSET_ANY, 0); 322 323 if (LIST_FIRST(&mii->mii_phys) == NULL) { 324 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 325 0, NULL); 326 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 327 } else 328 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 329 330 strcpy(ifp->if_xname, device_xname(self)); 331 ifp->if_softc = sc; 332 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 333 ifp->if_ioctl = aumac_ioctl; 334 ifp->if_start = aumac_start; 335 ifp->if_watchdog = aumac_watchdog; 336 ifp->if_init = aumac_init; 337 ifp->if_stop = aumac_stop; 338 IFQ_SET_READY(&ifp->if_snd); 339 340 /* Attach the interface. */ 341 if_attach(ifp); 342 if_deferred_start_init(ifp, NULL); 343 ether_ifattach(ifp, enaddr); 344 345 rnd_attach_source(&sc->rnd_source, device_xname(self), 346 RND_TYPE_NET, RND_FLAG_DEFAULT); 347 348 #ifdef AUMAC_EVENT_COUNTERS 349 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 350 NULL, device_xname(self), "txstall"); 351 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 352 NULL, device_xname(self), "rxstall"); 353 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 354 NULL, device_xname(self), "txintr"); 355 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 356 NULL, device_xname(self), "rxintr"); 357 #endif 358 359 /* Make sure the interface is shutdown during reboot. */ 360 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 361 if (sc->sc_sdhook == NULL) 362 aprint_error_dev(self, 363 "WARNING: unable to establish shutdown hook\n"); 364 return; 365 } 366 367 /* 368 * aumac_shutdown: 369 * 370 * Make sure the interface is stopped at reboot time. 371 */ 372 static void 373 aumac_shutdown(void *arg) 374 { 375 struct aumac_softc *sc = arg; 376 377 aumac_stop(&sc->sc_ethercom.ec_if, 1); 378 379 /* 380 * XXX aumac_stop leaves device powered up at the moment 381 * XXX but this still isn't enough to keep yamon happy... :-( 382 */ 383 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 384 } 385 386 /* 387 * aumac_start: [ifnet interface function] 388 * 389 * Start packet transmission on the interface. 390 */ 391 static void 392 aumac_start(struct ifnet *ifp) 393 { 394 struct aumac_softc *sc = ifp->if_softc; 395 struct mbuf *m; 396 int nexttx; 397 398 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 399 return; 400 401 /* 402 * Loop through the send queue, setting up transmit descriptors 403 * unitl we drain the queue, or use up all available transmit 404 * descriptors. 405 */ 406 for (;;) { 407 /* Grab a packet off the queue. */ 408 IFQ_POLL(&ifp->if_snd, m); 409 if (m == NULL) 410 return; 411 412 /* Get a spare descriptor. */ 413 if (sc->sc_txfree == 0) { 414 /* No more slots left; notify upper layer. */ 415 ifp->if_flags |= IFF_OACTIVE; 416 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 417 return; 418 } 419 nexttx = sc->sc_txnext; 420 421 IFQ_DEQUEUE(&ifp->if_snd, m); 422 423 /* 424 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 425 */ 426 427 m_copydata(m, 0, m->m_pkthdr.len, 428 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 429 430 /* Zero out the remainder of any short packets. */ 431 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 432 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 433 m->m_pkthdr.len, 0, 434 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 435 436 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 437 MACDMA_TX_STAT(nexttx), 0); 438 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 439 MACDMA_TX_LEN(nexttx), 440 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 441 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 442 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 443 MACDMA_TX_ADDR(nexttx), 444 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 445 /* XXX - needed?? we should be coherent */ 446 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 447 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 448 449 /* Advance the Tx pointer. */ 450 sc->sc_txfree--; 451 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 452 453 /* Pass the packet to any BPF listeners. */ 454 bpf_mtap(ifp, m, BPF_D_OUT); 455 456 m_freem(m); 457 458 /* Set a watchdog timer in case the chip flakes out. */ 459 ifp->if_timer = 5; 460 } 461 /* NOTREACHED */ 462 } 463 464 /* 465 * aumac_watchdog: [ifnet interface function] 466 * 467 * Watchdog timer handler. 468 */ 469 static void 470 aumac_watchdog(struct ifnet *ifp) 471 { 472 struct aumac_softc *sc = ifp->if_softc; 473 474 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 475 (void) aumac_init(ifp); 476 477 /* Try to get more packets going. */ 478 aumac_start(ifp); 479 } 480 481 /* 482 * aumac_ioctl: [ifnet interface function] 483 * 484 * Handle control requests from the operator. 485 */ 486 static int 487 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 488 { 489 struct aumac_softc *sc = ifp->if_softc; 490 int s, error; 491 492 s = splnet(); 493 494 error = ether_ioctl(ifp, cmd, data); 495 if (error == ENETRESET) { 496 /* 497 * Multicast list has changed; set the hardware filter 498 * accordingly. 499 */ 500 if (ifp->if_flags & IFF_RUNNING) 501 aumac_set_filter(sc); 502 error = 0; 503 } 504 505 /* Try to get more packets going. */ 506 aumac_start(ifp); 507 508 splx(s); 509 return error; 510 } 511 512 /* 513 * aumac_intr: 514 * 515 * Interrupt service routine. 516 */ 517 static int 518 aumac_intr(void *arg) 519 { 520 struct aumac_softc *sc = arg; 521 int status; 522 523 /* 524 * There aren't really any interrupt status bits on the 525 * Au1X00 MAC, and each MAC has a dedicated interrupt 526 * in the CPU's built-in interrupt controller. Just 527 * check for new incoming packets, and then Tx completions 528 * (for status updating). 529 */ 530 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 531 return 0; 532 533 status = aumac_rxintr(sc); 534 status += aumac_txintr(sc); 535 536 rnd_add_uint32(&sc->rnd_source, status); 537 538 return status; 539 } 540 541 /* 542 * aumac_txintr: 543 * 544 * Helper; handle transmit interrupts. 545 */ 546 static int 547 aumac_txintr(struct aumac_softc *sc) 548 { 549 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 550 uint32_t stat; 551 int i; 552 int pkts = 0; 553 554 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 555 i = AUMAC_NEXTTX(i)) { 556 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 557 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 558 break; 559 pkts++; 560 561 /* ACK interrupt. */ 562 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 563 MACDMA_TX_ADDR(i), 0); 564 565 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 566 MACDMA_TX_STAT(i)); 567 568 if (stat & TX_STAT_FA) { 569 /* XXX STATS */ 570 ifp->if_oerrors++; 571 } else 572 ifp->if_opackets++; 573 574 if (stat & TX_STAT_EC) 575 ifp->if_collisions += 16; 576 else 577 ifp->if_collisions += TX_STAT_CC(stat); 578 579 sc->sc_txfree++; 580 ifp->if_flags &= ~IFF_OACTIVE; 581 582 /* Try to queue more packets. */ 583 if_schedule_deferred_start(ifp); 584 } 585 586 if (pkts) 587 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 588 589 /* Update the dirty descriptor pointer. */ 590 sc->sc_txdirty = i; 591 592 /* 593 * If there are no more pending transmissions, cancel the watchdog 594 * timer. 595 */ 596 if (sc->sc_txfree == AUMAC_NTXDESC) 597 ifp->if_timer = 0; 598 599 return pkts; 600 } 601 602 /* 603 * aumac_rxintr: 604 * 605 * Helper; handle receive interrupts. 606 */ 607 static int 608 aumac_rxintr(struct aumac_softc *sc) 609 { 610 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 611 struct mbuf *m; 612 uint32_t stat; 613 int i, len; 614 int pkts = 0; 615 616 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 617 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 618 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 619 break; 620 pkts++; 621 622 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 623 MACDMA_RX_STAT(i)); 624 625 #define PRINTERR(str) \ 626 do { \ 627 error++; \ 628 printf("%s: %s\n", device_xname(sc->sc_dev), str); \ 629 } while (0) 630 631 if (stat & RX_STAT_ERRS) { 632 int error = 0; 633 634 #if 0 /* 635 * Missed frames are a semi-frequent occurence with this hardware, 636 * and reporting of them just makes everything run slower and fills 637 * the system log. Be silent. 638 * 639 * Additionally, this missed bit indicates an error with the previous 640 * packet, and not with this one! So PRINTERR is definitely wrong 641 * here. 642 * 643 * These should probably all be converted to evcnt counters anyway. 644 */ 645 if (stat & RX_STAT_MI) 646 PRINTERR("missed frame"); 647 #endif 648 if (stat & RX_STAT_UC) 649 PRINTERR("unknown control frame"); 650 if (stat & RX_STAT_LE) 651 PRINTERR("short frame"); 652 if (stat & RX_STAT_CR) 653 PRINTERR("CRC error"); 654 if (stat & RX_STAT_ME) 655 PRINTERR("medium error"); 656 if (stat & RX_STAT_CS) 657 PRINTERR("late collision"); 658 if (stat & RX_STAT_FL) 659 PRINTERR("frame too big"); 660 if (stat & RX_STAT_RF) 661 PRINTERR("runt frame (collision)"); 662 if (stat & RX_STAT_WT) 663 PRINTERR("watch dog"); 664 if (stat & RX_STAT_DB) { 665 if (stat & (RX_STAT_CS | RX_STAT_RF | 666 RX_STAT_CR)) { 667 if (!error) 668 goto pktok; 669 } else 670 PRINTERR("dribbling bit"); 671 } 672 #undef PRINTERR 673 ifp->if_ierrors++; 674 675 dropit: 676 /* reuse the current descriptor */ 677 AUMAC_INIT_RXDESC(sc, i); 678 continue; 679 } 680 pktok: 681 len = RX_STAT_L(stat); 682 683 /* 684 * The Au1X00 MAC includes the CRC with every packet; 685 * trim it off here. 686 */ 687 len -= ETHER_CRC_LEN; 688 689 /* 690 * Truncate the packet if it's too big to fit in 691 * a single mbuf cluster. 692 */ 693 if (len > MCLBYTES - 2) 694 len = MCLBYTES - 2; 695 696 MGETHDR(m, M_DONTWAIT, MT_DATA); 697 if (m == NULL) { 698 printf("%s: unable to allocate Rx mbuf\n", 699 device_xname(sc->sc_dev)); 700 goto dropit; 701 } 702 if (len > MHLEN - 2) { 703 MCLGET(m, M_DONTWAIT); 704 if ((m->m_flags & M_EXT) == 0) { 705 printf("%s: unable to allocate Rx cluster\n", 706 device_xname(sc->sc_dev)); 707 m_freem(m); 708 goto dropit; 709 } 710 } 711 712 m->m_data += 2; /* align payload */ 713 memcpy(mtod(m, void *), 714 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 715 AUMAC_INIT_RXDESC(sc, i); 716 717 m_set_rcvif(m, ifp); 718 m->m_pkthdr.len = m->m_len = len; 719 720 /* Pass it on. */ 721 if_percpuq_enqueue(ifp->if_percpuq, m); 722 } 723 if (pkts) 724 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 725 if (pkts == AUMAC_NRXDESC) 726 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 727 728 /* Update the receive pointer. */ 729 sc->sc_rxptr = i; 730 731 return pkts; 732 } 733 734 /* 735 * aumac_tick: 736 * 737 * One second timer, used to tick the MII. 738 */ 739 static void 740 aumac_tick(void *arg) 741 { 742 struct aumac_softc *sc = arg; 743 int s; 744 745 s = splnet(); 746 mii_tick(&sc->sc_mii); 747 splx(s); 748 749 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 750 } 751 752 /* 753 * aumac_init: [ifnet interface function] 754 * 755 * Initialize the interface. Must be called at splnet(). 756 */ 757 static int 758 aumac_init(struct ifnet *ifp) 759 { 760 struct aumac_softc *sc = ifp->if_softc; 761 int i, error = 0; 762 763 /* Cancel any pending I/O, reset MAC. */ 764 aumac_stop(ifp, 0); 765 766 /* Set up the transmit ring. */ 767 for (i = 0; i < AUMAC_NTXDESC; i++) { 768 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 769 MACDMA_TX_STAT(i), 0); 770 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 771 MACDMA_TX_LEN(i), 0); 772 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 773 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 774 } 775 sc->sc_txfree = AUMAC_NTXDESC; 776 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 777 MACDMA_TX_ADDR(0))); 778 sc->sc_txdirty = sc->sc_txnext; 779 780 /* Set up the receive ring. */ 781 for (i = 0; i < AUMAC_NRXDESC; i++) 782 AUMAC_INIT_RXDESC(sc, i); 783 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 784 MACDMA_RX_ADDR(0))); 785 786 /* 787 * Power up the MAC. 788 */ 789 aumac_powerup(sc); 790 791 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 792 #if _BYTE_ORDER == _BIG_ENDIAN 793 sc->sc_control |= CONTROL_EM; 794 #endif 795 796 /* Set the media. */ 797 if ((error = ether_mediachange(ifp)) != 0) 798 goto out; 799 800 /* 801 * Set the receive filter. This will actually start the transmit 802 * and receive processes. 803 */ 804 aumac_set_filter(sc); 805 806 /* Start the one second clock. */ 807 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 808 809 /* ...all done! */ 810 ifp->if_flags |= IFF_RUNNING; 811 ifp->if_flags &= ~IFF_OACTIVE; 812 813 au_intr_enable(sc->sc_irq); 814 out: 815 if (error) 816 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 817 return error; 818 } 819 820 /* 821 * aumac_stop: [ifnet interface function] 822 * 823 * Stop transmission on the interface. 824 */ 825 static void 826 aumac_stop(struct ifnet *ifp, int disable) 827 { 828 struct aumac_softc *sc = ifp->if_softc; 829 830 /* Stop the one-second clock. */ 831 callout_stop(&sc->sc_tick_ch); 832 833 /* Down the MII. */ 834 mii_down(&sc->sc_mii); 835 836 /* Stop the transmit and receive processes. */ 837 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 838 839 /* Power down/reset the MAC. */ 840 aumac_powerdown(sc); 841 842 au_intr_disable(sc->sc_irq); 843 844 /* Mark the interface as down and cancel the watchdog timer. */ 845 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 846 ifp->if_timer = 0; 847 } 848 849 /* 850 * aumac_powerdown: 851 * 852 * Power down the MAC. 853 */ 854 static void 855 aumac_powerdown(struct aumac_softc *sc) 856 { 857 858 /* Disable the MAC clocks, and place the device in reset. */ 859 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 860 861 // delay(10000); 862 } 863 864 /* 865 * aumac_powerup: 866 * 867 * Bring the device out of reset. 868 */ 869 static void 870 aumac_powerup(struct aumac_softc *sc) 871 { 872 873 /* Enable clocks to the MAC. */ 874 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP | MACEN_CE); 875 876 /* Enable MAC, coherent transactions, pass only valid frames. */ 877 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 878 MACEN_E2 | MACEN_E1 | MACEN_E0 | MACEN_CE); 879 880 delay(20000); 881 } 882 883 /* 884 * aumac_set_filter: 885 * 886 * Set up the receive filter. 887 */ 888 static void 889 aumac_set_filter(struct aumac_softc *sc) 890 { 891 struct ethercom *ec = &sc->sc_ethercom; 892 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 893 struct ether_multi *enm; 894 struct ether_multistep step; 895 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 896 uint32_t mchash[2], crc; 897 898 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 899 900 /* Stop the receiver. */ 901 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 902 sc->sc_control & ~CONTROL_RE); 903 904 if (ifp->if_flags & IFF_PROMISC) { 905 sc->sc_control |= CONTROL_PR; 906 goto allmulti; 907 } 908 909 /* Set the station address. */ 910 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 911 enaddr[4] | (enaddr[5] << 8)); 912 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 913 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 914 (enaddr[3] << 24)); 915 916 sc->sc_control |= CONTROL_HP; 917 918 mchash[0] = mchash[1] = 0; 919 920 /* 921 * Set up the multicast address filter by passing all multicast 922 * addresses through a CRC generator, and then using the high 923 * order 6 bits as an index into the 64-bit multicast hash table. 924 * The high order bits select the word, while the rest of the bits 925 * select the bit within the word. 926 */ 927 ETHER_LOCK(ec); 928 ETHER_FIRST_MULTI(step, ec, enm); 929 while (enm != NULL) { 930 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 931 /* 932 * We must listen to a range of multicast addresses. 933 * For now, just accept all multicasts, rather than 934 * trying to set only those filter bits needed to match 935 * the range. (At this time, the only use of address 936 * ranges is for IP multicast routing, for which the 937 * range is large enough to require all bits set.) 938 */ 939 ETHER_UNLOCK(ec); 940 goto allmulti; 941 } 942 943 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 944 945 /* Just want the 6 most significant bits. */ 946 crc >>= 26; 947 948 /* Set the corresponding bit in the filter. */ 949 mchash[crc >> 5] |= 1U << (crc & 0x1f); 950 951 ETHER_NEXT_MULTI(step, enm); 952 } 953 ETHER_UNLOCK(ec); 954 955 ifp->if_flags &= ~IFF_ALLMULTI; 956 957 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 958 mchash[1]); 959 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 960 mchash[0]); 961 962 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 963 sc->sc_control); 964 return; 965 966 allmulti: 967 sc->sc_control |= CONTROL_PM; 968 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 969 sc->sc_control); 970 } 971 972 /* 973 * aumac_mii_wait: 974 * 975 * Wait for the MII interface to not be busy. 976 */ 977 static int 978 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 979 { 980 int i; 981 982 for (i = 0; i < 10000; i++) { 983 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 984 MAC_MIICTRL) & MIICTRL_MB) == 0) 985 return 0; 986 delay(10); 987 } 988 989 printf("%s: MII failed to %s\n", device_xname(sc->sc_dev), msg); 990 return ETIMEDOUT; 991 } 992 993 /* 994 * aumac_mii_readreg: [mii interface function] 995 * 996 * Read a PHY register on the MII. 997 */ 998 static int 999 aumac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 1000 { 1001 struct aumac_softc *sc = device_private(self); 1002 int rv; 1003 1004 if ((rv = aumac_mii_wait(sc, "become ready")) != 0) 1005 return rv; 1006 1007 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1008 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1009 1010 if ((rv = aumac_mii_wait(sc, "complete")) != 0) 1011 return rv; 1012 1013 *val = bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) 1014 & MIIDATA_MASK; 1015 return 0; 1016 } 1017 1018 /* 1019 * aumac_mii_writereg: [mii interface function] 1020 * 1021 * Write a PHY register on the MII. 1022 */ 1023 static int 1024 aumac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 1025 { 1026 struct aumac_softc *sc = device_private(self); 1027 int rv; 1028 1029 if ((rv = aumac_mii_wait(sc, "become ready")) != 0) 1030 return rv; 1031 1032 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1033 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1034 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1035 1036 return aumac_mii_wait(sc, "complete"); 1037 } 1038 1039 /* 1040 * aumac_mii_statchg: [mii interface function] 1041 * 1042 * Callback from MII layer when media changes. 1043 */ 1044 static void 1045 aumac_mii_statchg(struct ifnet *ifp) 1046 { 1047 struct aumac_softc *sc = ifp->if_softc; 1048 1049 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1050 sc->sc_control |= CONTROL_F; 1051 else 1052 sc->sc_control &= ~CONTROL_F; 1053 1054 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1055 sc->sc_control); 1056 } 1057