1 /* $NetBSD: if_aumac.c,v 1.10 2003/03/27 01:21:52 simonb Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.10 2003/03/27 01:21:52 simonb Exp $"); 50 51 #include "bpfilter.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/queue.h> 64 65 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 #include <machine/endian.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <mips/alchemy/include/aureg.h> 84 #include <mips/alchemy/include/auvar.h> 85 #include <mips/alchemy/include/aubusvar.h> 86 #include <mips/alchemy/dev/if_aumacreg.h> 87 88 /* 89 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 90 * must consist of a single DMA segment, and must be aligned to a 2K 91 * boundary. Therefore, this driver does not perform DMA directly 92 * to/from mbufs. Instead, we copy the data to/from buffers allocated 93 * at device attach time. 94 * 95 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 96 * there's little point in not making assumptions based on the CPU type. 97 * We also program the Au1X00 cache to be DMA coherent, so the buffers 98 * are accessed via KSEG0 addresses. 99 */ 100 #define AUMAC_NTXDESC 4 101 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 102 103 #define AUMAC_NRXDESC 4 104 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 105 106 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 107 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 108 109 #define AUMAC_TXBUF_OFFSET 0 110 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 111 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 112 113 struct aumac_buf { 114 caddr_t buf_vaddr; /* virtual address of buffer */ 115 bus_addr_t buf_paddr; /* DMA address of buffer */ 116 }; 117 118 /* 119 * Software state per device. 120 */ 121 struct aumac_softc { 122 struct device sc_dev; /* generic device information */ 123 bus_space_tag_t sc_st; /* bus space tag */ 124 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 125 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 126 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 127 struct ethercom sc_ethercom; /* Ethernet common data */ 128 void *sc_sdhook; /* shutdown hook */ 129 130 void *sc_ih; /* interrupt cookie */ 131 132 struct mii_data sc_mii; /* MII/media information */ 133 134 struct callout sc_tick_ch; /* tick callout */ 135 136 /* Transmit and receive buffers */ 137 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 138 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 139 caddr_t sc_bufaddr; 140 141 int sc_txfree; /* number of free Tx descriptors */ 142 int sc_txnext; /* next Tx descriptor to use */ 143 int sc_txdirty; /* first dirty Tx descriptor */ 144 145 int sc_rxptr; /* next ready Rx descriptor */ 146 147 #ifdef AUMAC_EVENT_COUNTERS 148 struct evcnt sc_ev_txstall; /* Tx stalled */ 149 struct evcnt sc_ev_rxstall; /* Rx stalled */ 150 struct evcnt sc_ev_txintr; /* Tx interrupts */ 151 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 152 #endif 153 154 uint32_t sc_control; /* MAC_CONTROL contents */ 155 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 156 }; 157 158 #ifdef AUMAC_EVENT_COUNTERS 159 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 160 #else 161 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 162 #endif 163 164 #define AUMAC_INIT_RXDESC(sc, x) \ 165 do { \ 166 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 167 MACDMA_RX_STAT((x)), 0); \ 168 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 169 MACDMA_RX_ADDR((x)), \ 170 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 171 } while (/*CONSTCOND*/0) 172 173 static void aumac_start(struct ifnet *); 174 static void aumac_watchdog(struct ifnet *); 175 static int aumac_ioctl(struct ifnet *, u_long, caddr_t); 176 static int aumac_init(struct ifnet *); 177 static void aumac_stop(struct ifnet *, int); 178 179 static void aumac_shutdown(void *); 180 181 static void aumac_tick(void *); 182 183 static void aumac_set_filter(struct aumac_softc *); 184 185 static void aumac_powerup(struct aumac_softc *); 186 static void aumac_powerdown(struct aumac_softc *); 187 188 static int aumac_intr(void *); 189 static void aumac_txintr(struct aumac_softc *); 190 static void aumac_rxintr(struct aumac_softc *); 191 192 static int aumac_mii_readreg(struct device *, int, int); 193 static void aumac_mii_writereg(struct device *, int, int, int); 194 static void aumac_mii_statchg(struct device *); 195 static int aumac_mii_wait(struct aumac_softc *, const char *); 196 197 static int aumac_mediachange(struct ifnet *); 198 static void aumac_mediastatus(struct ifnet *, struct ifmediareq *); 199 200 static int aumac_match(struct device *, struct cfdata *, void *); 201 static void aumac_attach(struct device *, struct device *, void *); 202 203 int aumac_copy_small = 0; 204 205 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 206 aumac_match, aumac_attach, NULL, NULL); 207 208 static int 209 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 210 { 211 struct aubus_attach_args *aa = aux; 212 213 if (strcmp(aa->aa_name, cf->cf_name) == 0) 214 return (1); 215 216 return (0); 217 } 218 219 static void 220 aumac_attach(struct device *parent, struct device *self, void *aux) 221 { 222 char prop_name[sizeof("0xffffffff:mac-addr") + 1]; 223 uint8_t enaddr[ETHER_ADDR_LEN]; 224 struct aumac_softc *sc = (void *) self; 225 struct aubus_attach_args *aa = aux; 226 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 227 struct pglist pglist; 228 paddr_t bufaddr; 229 caddr_t vbufaddr; 230 int i; 231 232 callout_init(&sc->sc_tick_ch); 233 234 printf(": Au1X00 10/100 Ethernet\n"); 235 236 sc->sc_st = aa->aa_st; 237 238 /* Get the MAC address. */ 239 snprintf(prop_name, sizeof(prop_name), "%p:mac-addr", self); 240 if (alchemy_info_get(prop_name, enaddr, sizeof(enaddr)) == -1) { 241 printf("%s: unable to determine MAC address\n", 242 sc->sc_dev.dv_xname); 243 return; 244 } 245 246 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 247 ether_sprintf(enaddr)); 248 249 /* Map the device. */ 250 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 251 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 252 printf("%s: unable to map MAC registers\n", 253 sc->sc_dev.dv_xname); 254 return; 255 } 256 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 257 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 258 printf("%s: unable to map MACEN registers\n", 259 sc->sc_dev.dv_xname); 260 return; 261 } 262 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 263 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 264 printf("%s: unable to map MACDMA registers\n", 265 sc->sc_dev.dv_xname); 266 return; 267 } 268 269 /* Make sure the MAC is powered off. */ 270 aumac_powerdown(sc); 271 272 /* Hook up the interrupt handler. */ 273 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 274 aumac_intr, sc); 275 if (sc->sc_ih == NULL) { 276 printf("%s: unable to register interrupt handler\n", 277 sc->sc_dev.dv_xname); 278 return; 279 } 280 281 /* 282 * Allocate space for the transmit and receive buffers. 283 */ 284 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 285 &pglist, 1, 0)) 286 return; 287 288 bufaddr = TAILQ_FIRST(&pglist)->phys_addr; 289 vbufaddr = (void *)MIPS_PHYS_TO_KSEG0(bufaddr); 290 291 for (i = 0; i < AUMAC_NTXDESC; i++) { 292 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 293 294 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 295 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 296 } 297 298 for (i = 0; i < AUMAC_NRXDESC; i++) { 299 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 300 301 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 302 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 303 } 304 305 /* 306 * Power up the MAC before accessing any MAC registers (including 307 * MII configuration. 308 */ 309 aumac_powerup(sc); 310 311 /* 312 * Initialize the media structures and probe the MII. 313 */ 314 sc->sc_mii.mii_ifp = ifp; 315 sc->sc_mii.mii_readreg = aumac_mii_readreg; 316 sc->sc_mii.mii_writereg = aumac_mii_writereg; 317 sc->sc_mii.mii_statchg = aumac_mii_statchg; 318 ifmedia_init(&sc->sc_mii.mii_media, 0, aumac_mediachange, 319 aumac_mediastatus); 320 321 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 322 MII_OFFSET_ANY, 0); 323 324 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 325 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 326 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 327 } else 328 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 329 330 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 331 ifp->if_softc = sc; 332 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 333 ifp->if_ioctl = aumac_ioctl; 334 ifp->if_start = aumac_start; 335 ifp->if_watchdog = aumac_watchdog; 336 ifp->if_init = aumac_init; 337 ifp->if_stop = aumac_stop; 338 IFQ_SET_READY(&ifp->if_snd); 339 340 /* Attach the interface. */ 341 if_attach(ifp); 342 ether_ifattach(ifp, enaddr); 343 344 #ifdef AUMAC_EVENT_COUNTERS 345 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 346 NULL, sc->sc_dev.dv_xname, "txstall"); 347 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 348 NULL, sc->sc_dev.dv_xname, "rxstall"); 349 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 350 NULL, sc->sc_dev.dv_xname, "txintr"); 351 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 352 NULL, sc->sc_dev.dv_xname, "rxintr"); 353 #endif 354 355 /* Make sure the interface is shutdown during reboot. */ 356 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 357 if (sc->sc_sdhook == NULL) 358 printf("%s: WARNING: unable to establish shutdown hook\n", 359 sc->sc_dev.dv_xname); 360 return; 361 } 362 363 /* 364 * aumac_shutdown: 365 * 366 * Make sure the interface is stopped at reboot time. 367 */ 368 static void 369 aumac_shutdown(void *arg) 370 { 371 struct aumac_softc *sc = arg; 372 373 aumac_stop(&sc->sc_ethercom.ec_if, 1); 374 375 /* 376 * XXX aumac_stop leaves device powered up at the moment 377 * XXX but this still isn't enough to keep yamon happy... :-( 378 */ 379 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 380 } 381 382 /* 383 * aumac_start: [ifnet interface function] 384 * 385 * Start packet transmission on the interface. 386 */ 387 static void 388 aumac_start(struct ifnet *ifp) 389 { 390 struct aumac_softc *sc = ifp->if_softc; 391 struct mbuf *m; 392 int nexttx; 393 394 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 395 return; 396 397 /* 398 * Loop through the send queue, setting up transmit descriptors 399 * unitl we drain the queue, or use up all available transmit 400 * descriptors. 401 */ 402 for (;;) { 403 /* Grab a packet off the queue. */ 404 IFQ_POLL(&ifp->if_snd, m); 405 if (m == NULL) 406 return; 407 408 /* Get a spare descriptor. */ 409 if (sc->sc_txfree == 0) { 410 /* No more slots left; notify upper layer. */ 411 ifp->if_flags |= IFF_OACTIVE; 412 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 413 return; 414 } 415 nexttx = sc->sc_txnext; 416 417 IFQ_DEQUEUE(&ifp->if_snd, m); 418 419 /* 420 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 421 */ 422 423 m_copydata(m, 0, m->m_pkthdr.len, 424 sc->sc_txbufs[nexttx].buf_vaddr); 425 426 /* Zero out the remainder of any short packets. */ 427 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 428 memset(sc->sc_txbufs[nexttx].buf_vaddr + 429 m->m_pkthdr.len, 0, 430 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 431 432 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 433 MACDMA_TX_STAT(nexttx), 0); 434 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 435 MACDMA_TX_LEN(nexttx), 436 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 437 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 438 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 439 MACDMA_TX_ADDR(nexttx), 440 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 441 /* XXX - needed?? we should be coherent */ 442 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 443 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 444 445 /* Advance the Tx pointer. */ 446 sc->sc_txfree--; 447 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 448 449 #if NBPFILTER > 0 450 /* Pass the packet to any BPF listeners. */ 451 if (ifp->if_bpf) 452 bpf_mtap(ifp->if_bpf, m); 453 #endif /* NBPFILTER */ 454 455 m_freem(m); 456 457 /* Set a watchdog timer in case the chip flakes out. */ 458 ifp->if_timer = 5; 459 } 460 /* NOTREACHED */ 461 } 462 463 /* 464 * aumac_watchdog: [ifnet interface function] 465 * 466 * Watchdog timer handler. 467 */ 468 static void 469 aumac_watchdog(struct ifnet *ifp) 470 { 471 struct aumac_softc *sc = ifp->if_softc; 472 473 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 474 (void) aumac_init(ifp); 475 476 /* Try to get more packets going. */ 477 aumac_start(ifp); 478 } 479 480 /* 481 * aumac_ioctl: [ifnet interface function] 482 * 483 * Handle control requests from the operator. 484 */ 485 static int 486 aumac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 487 { 488 struct aumac_softc *sc = ifp->if_softc; 489 struct ifreq *ifr = (struct ifreq *) data; 490 int s, error; 491 492 s = splnet(); 493 494 switch (cmd) { 495 case SIOCSIFMEDIA: 496 case SIOCGIFMEDIA: 497 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 498 break; 499 500 default: 501 error = ether_ioctl(ifp, cmd, data); 502 if (error == ENETRESET) { 503 /* 504 * Multicast list has changed; set the hardware filter 505 * accordingly. 506 */ 507 aumac_set_filter(sc); 508 } 509 break; 510 } 511 512 /* Try to get more packets going. */ 513 aumac_start(ifp); 514 515 splx(s); 516 return (error); 517 } 518 519 /* 520 * aumac_intr: 521 * 522 * Interrupt service routine. 523 */ 524 static int 525 aumac_intr(void *arg) 526 { 527 struct aumac_softc *sc = arg; 528 529 /* 530 * There aren't really any interrupt status bits on the 531 * Au1X00 MAC, and each MAC has a dedicated interrupt 532 * in the CPU's built-in interrupt controller. Just 533 * check for new incoming packets, and then Tx completions 534 * (for status updating). 535 */ 536 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 537 return (0); 538 539 aumac_rxintr(sc); 540 aumac_txintr(sc); 541 542 return (1); 543 } 544 545 /* 546 * aumac_txintr: 547 * 548 * Helper; handle transmit interrupts. 549 */ 550 static void 551 aumac_txintr(struct aumac_softc *sc) 552 { 553 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 554 uint32_t stat; 555 int i; 556 #ifdef AUMAC_EVENT_COUNTERS 557 int gotone = 0; 558 #endif 559 560 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 561 i = AUMAC_NEXTTX(i)) { 562 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 563 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 564 break; 565 #ifdef AUMAC_EVENT_COUNTERS 566 gotone = 1; 567 #endif 568 569 /* ACK interrupt. */ 570 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 571 MACDMA_TX_ADDR(i), 0); 572 573 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 574 MACDMA_TX_STAT(i)); 575 576 if (stat & TX_STAT_FA) { 577 /* XXX STATS */ 578 ifp->if_oerrors++; 579 } else 580 ifp->if_opackets++; 581 582 if (stat & TX_STAT_EC) 583 ifp->if_collisions += 16; 584 else 585 ifp->if_collisions += TX_STAT_CC(stat); 586 587 sc->sc_txfree++; 588 ifp->if_flags &= ~IFF_OACTIVE; 589 590 /* Try to queue more packets. */ 591 aumac_start(ifp); 592 } 593 594 if (gotone) 595 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 596 597 /* Update the dirty descriptor pointer. */ 598 sc->sc_txdirty = i; 599 600 /* 601 * If there are no more pending transmissions, cancel the watchdog 602 * timer. 603 */ 604 if (sc->sc_txfree == AUMAC_NTXDESC) 605 ifp->if_timer = 0; 606 } 607 608 /* 609 * aumac_rxintr: 610 * 611 * Helper; handle receive interrupts. 612 */ 613 static void 614 aumac_rxintr(struct aumac_softc *sc) 615 { 616 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 617 struct mbuf *m; 618 uint32_t stat; 619 int i, len; 620 #ifdef AUMAC_EVENT_COUNTERS 621 int pkts = 0; 622 #endif 623 624 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 625 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 626 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 627 break; 628 #ifdef AUMAC_EVENT_COUNTERS 629 pkts++; 630 #endif 631 632 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 633 MACDMA_RX_STAT(i)); 634 635 #define PRINTERR(str) \ 636 do { \ 637 error++; \ 638 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 639 } while (0) 640 641 if (stat & RX_STAT_ERRS) { 642 int error = 0; 643 644 if (stat & RX_STAT_MI) 645 PRINTERR("missed frame"); 646 if (stat & RX_STAT_UC) 647 PRINTERR("unknown control frame"); 648 if (stat & RX_STAT_LE) 649 PRINTERR("short frame"); 650 if (stat & RX_STAT_CR) 651 PRINTERR("CRC error"); 652 if (stat & RX_STAT_ME) 653 PRINTERR("medium error"); 654 if (stat & RX_STAT_CS) 655 PRINTERR("late collision"); 656 if (stat & RX_STAT_FL) 657 PRINTERR("frame too big"); 658 if (stat & RX_STAT_RF) 659 PRINTERR("runt frame (collision)"); 660 if (stat & RX_STAT_WT) 661 PRINTERR("watch dog"); 662 if (stat & RX_STAT_DB) { 663 if (stat & (RX_STAT_CS | RX_STAT_RF | 664 RX_STAT_CR)) { 665 if (!error) 666 goto pktok; 667 } else 668 PRINTERR("dribbling bit"); 669 } 670 #undef PRINTERR 671 ifp->if_ierrors++; 672 673 dropit: 674 /* reuse the current descriptor */ 675 AUMAC_INIT_RXDESC(sc, i); 676 continue; 677 } 678 pktok: 679 len = RX_STAT_L(stat); 680 681 /* 682 * The Au1X00 MAC includes the CRC with every packet; 683 * trim it off here. 684 */ 685 len -= ETHER_CRC_LEN; 686 687 /* 688 * Truncate the packet if it's too big to fit in 689 * a single mbuf cluster. 690 */ 691 if (len > MCLBYTES - 2) 692 len = MCLBYTES - 2; 693 694 MGETHDR(m, M_DONTWAIT, MT_DATA); 695 if (m == NULL) { 696 printf("%s: unable to allocate Rx mbuf\n", 697 sc->sc_dev.dv_xname); 698 goto dropit; 699 } 700 if (len > MHLEN - 2) { 701 MCLGET(m, M_DONTWAIT); 702 if ((m->m_flags & M_EXT) == 0) { 703 printf("%s: unable to allocate Rx cluster\n", 704 sc->sc_dev.dv_xname); 705 m_freem(m); 706 goto dropit; 707 } 708 } 709 710 m->m_data += 2; /* align payload */ 711 memcpy(mtod(m, caddr_t), 712 sc->sc_rxbufs[i].buf_vaddr, len); 713 AUMAC_INIT_RXDESC(sc, i); 714 715 m->m_pkthdr.rcvif = ifp; 716 m->m_pkthdr.len = m->m_len = len; 717 718 #if NBPFILTER > 0 719 /* Pass this up to any BPF listeners. */ 720 if (ifp->if_bpf) 721 bpf_mtap(ifp->if_bpf, m); 722 #endif /* NBPFILTER > 0 */ 723 724 /* Pass it on. */ 725 (*ifp->if_input)(ifp, m); 726 ifp->if_ipackets++; 727 } 728 if (pkts) 729 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 730 if (pkts == AUMAC_NRXDESC) 731 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 732 733 /* Update the receive pointer. */ 734 sc->sc_rxptr = i; 735 } 736 737 /* 738 * aumac_tick: 739 * 740 * One second timer, used to tick the MII. 741 */ 742 static void 743 aumac_tick(void *arg) 744 { 745 struct aumac_softc *sc = arg; 746 int s; 747 748 s = splnet(); 749 mii_tick(&sc->sc_mii); 750 splx(s); 751 752 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 753 } 754 755 /* 756 * aumac_init: [ifnet interface function] 757 * 758 * Initialize the interface. Must be called at splnet(). 759 */ 760 static int 761 aumac_init(struct ifnet *ifp) 762 { 763 struct aumac_softc *sc = ifp->if_softc; 764 int i, error = 0; 765 766 /* Cancel any pending I/O, reset MAC. */ 767 aumac_stop(ifp, 0); 768 769 /* Set up the transmit ring. */ 770 for (i = 0; i < AUMAC_NTXDESC; i++) { 771 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 772 MACDMA_TX_STAT(i), 0); 773 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 774 MACDMA_TX_LEN(i), 0); 775 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 776 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 777 } 778 sc->sc_txfree = AUMAC_NTXDESC; 779 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 780 MACDMA_TX_ADDR(0))); 781 sc->sc_txdirty = sc->sc_txnext; 782 783 /* Set up the receive ring. */ 784 for (i = 0; i < AUMAC_NRXDESC; i++) 785 AUMAC_INIT_RXDESC(sc, i); 786 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 787 MACDMA_RX_ADDR(0))); 788 789 /* 790 * Power up the MAC. 791 */ 792 aumac_powerup(sc); 793 794 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 795 #if _BYTE_ORDER == _BIG_ENDIAN 796 sc->sc_control |= CONTROL_EM; 797 #endif 798 799 /* Set the media. */ 800 aumac_mediachange(ifp); 801 802 /* 803 * Set the receive filter. This will actually start the transmit 804 * and receive processes. 805 */ 806 aumac_set_filter(sc); 807 808 /* Start the one second clock. */ 809 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 810 811 /* ...all done! */ 812 ifp->if_flags |= IFF_RUNNING; 813 ifp->if_flags &= ~IFF_OACTIVE; 814 815 if (error) 816 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 817 return (error); 818 } 819 820 /* 821 * aumac_stop: [ifnet interface function] 822 * 823 * Stop transmission on the interface. 824 */ 825 static void 826 aumac_stop(struct ifnet *ifp, int disable) 827 { 828 struct aumac_softc *sc = ifp->if_softc; 829 830 /* Stop the one-second clock. */ 831 callout_stop(&sc->sc_tick_ch); 832 833 /* Down the MII. */ 834 mii_down(&sc->sc_mii); 835 836 /* Stop the transmit and receive processes. */ 837 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 838 839 /* Power down/reset the MAC. */ 840 aumac_powerdown(sc); 841 842 /* Mark the interface as down and cancel the watchdog timer. */ 843 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 844 ifp->if_timer = 0; 845 } 846 847 /* 848 * aumac_powerdown: 849 * 850 * Power down the MAC. 851 */ 852 static void 853 aumac_powerdown(struct aumac_softc *sc) 854 { 855 856 /* Disable the MAC clocks, and place the device in reset. */ 857 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 858 859 // delay(10000); 860 } 861 862 /* 863 * aumac_powerup: 864 * 865 * Bring the device out of reset. 866 */ 867 static void 868 aumac_powerup(struct aumac_softc *sc) 869 { 870 871 /* Enable clocks to the MAC. */ 872 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 873 874 /* Enable MAC, coherent transactions, pass only valid frames. */ 875 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 876 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 877 878 delay(20000); 879 } 880 881 /* 882 * aumac_set_filter: 883 * 884 * Set up the receive filter. 885 */ 886 static void 887 aumac_set_filter(struct aumac_softc *sc) 888 { 889 struct ethercom *ec = &sc->sc_ethercom; 890 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 891 struct ether_multi *enm; 892 struct ether_multistep step; 893 const uint8_t *enaddr = LLADDR(ifp->if_sadl); 894 uint32_t mchash[2], crc; 895 896 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 897 898 /* Stop the receiver. */ 899 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 900 sc->sc_control & ~CONTROL_RE); 901 902 if (ifp->if_flags & IFF_PROMISC) { 903 sc->sc_control |= CONTROL_PR; 904 goto allmulti; 905 } 906 907 /* Set the station address. */ 908 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 909 enaddr[4] | (enaddr[5] << 8)); 910 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 911 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 912 (enaddr[3] << 24)); 913 914 sc->sc_control |= CONTROL_HP; 915 916 mchash[0] = mchash[1] = 0; 917 918 /* 919 * Set up the multicast address filter by passing all multicast 920 * addresses through a CRC generator, and then using the high 921 * order 6 bits as an index into the 64-bit multicast hash table. 922 * The high order bits select the word, while the rest of the bits 923 * select the bit within the word. 924 */ 925 ETHER_FIRST_MULTI(step, ec, enm); 926 while (enm != NULL) { 927 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 928 /* 929 * We must listen to a range of multicast addresses. 930 * For now, just accept all multicasts, rather than 931 * trying to set only those filter bits needed to match 932 * the range. (At this time, the only use of address 933 * ranges is for IP multicast routing, for which the 934 * range is large enough to require all bits set.) 935 */ 936 goto allmulti; 937 } 938 939 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 940 941 /* Just want the 6 most significant bits. */ 942 crc >>= 26; 943 944 /* Set the corresponding bit in the filter. */ 945 mchash[crc >> 5] |= 1U << (crc & 0x1f); 946 947 ETHER_NEXT_MULTI(step, enm); 948 } 949 950 ifp->if_flags &= ~IFF_ALLMULTI; 951 952 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 953 mchash[1]); 954 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 955 mchash[0]); 956 957 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 958 sc->sc_control); 959 return; 960 961 allmulti: 962 sc->sc_control |= CONTROL_PM; 963 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 964 sc->sc_control); 965 } 966 967 /* 968 * aumac_mediastatus: [ifmedia interface function] 969 * 970 * Get the current interface media status. 971 */ 972 static void 973 aumac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 974 { 975 struct aumac_softc *sc = ifp->if_softc; 976 977 mii_pollstat(&sc->sc_mii); 978 ifmr->ifm_status = sc->sc_mii.mii_media_status; 979 ifmr->ifm_active = sc->sc_mii.mii_media_active; 980 } 981 982 /* 983 * aumac_mediachange: [ifmedia interface function] 984 * 985 * Set hardware to newly selected media. 986 */ 987 static int 988 aumac_mediachange(struct ifnet *ifp) 989 { 990 struct aumac_softc *sc = ifp->if_softc; 991 992 if (ifp->if_flags & IFF_UP) 993 mii_mediachg(&sc->sc_mii); 994 return (0); 995 } 996 997 /* 998 * aumac_mii_wait: 999 * 1000 * Wait for the MII interface to not be busy. 1001 */ 1002 static int 1003 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 1004 { 1005 int i; 1006 1007 for (i = 0; i < 10000; i++) { 1008 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 1009 MAC_MIICTRL) & MIICTRL_MB) == 0) 1010 return (0); 1011 delay(10); 1012 } 1013 1014 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 1015 return (1); 1016 } 1017 1018 /* 1019 * aumac_mii_readreg: [mii interface function] 1020 * 1021 * Read a PHY register on the MII. 1022 */ 1023 static int 1024 aumac_mii_readreg(struct device *self, int phy, int reg) 1025 { 1026 struct aumac_softc *sc = (void *) self; 1027 1028 if (aumac_mii_wait(sc, "become ready")) 1029 return (0); 1030 1031 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1032 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1033 1034 if (aumac_mii_wait(sc, "complete")) 1035 return (0); 1036 1037 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1038 MIIDATA_MASK); 1039 } 1040 1041 /* 1042 * aumac_mii_writereg: [mii interface function] 1043 * 1044 * Write a PHY register on the MII. 1045 */ 1046 static void 1047 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1048 { 1049 struct aumac_softc *sc = (void *) self; 1050 1051 if (aumac_mii_wait(sc, "become ready")) 1052 return; 1053 1054 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1055 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1056 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1057 1058 (void) aumac_mii_wait(sc, "complete"); 1059 } 1060 1061 /* 1062 * aumac_mii_statchg: [mii interface function] 1063 * 1064 * Callback from MII layer when media changes. 1065 */ 1066 static void 1067 aumac_mii_statchg(struct device *self) 1068 { 1069 struct aumac_softc *sc = (void *) self; 1070 1071 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1072 sc->sc_control |= CONTROL_F; 1073 else 1074 sc->sc_control &= ~CONTROL_F; 1075 1076 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1077 sc->sc_control); 1078 } 1079