1 /* $NetBSD: if_aumac.c,v 1.31 2011/07/10 23:13:23 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.31 2011/07/10 23:13:23 matt Exp $"); 50 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/callout.h> 56 #include <sys/device.h> 57 #include <sys/endian.h> 58 #include <sys/errno.h> 59 #include <sys/intr.h> 60 #include <sys/ioctl.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/socket.h> 65 66 #include <uvm/uvm.h> /* for PAGE_SIZE */ 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #include <net/bpf.h> 74 #if NRND > 0 75 #include <sys/rnd.h> 76 #endif 77 78 #include <dev/mii/mii.h> 79 #include <dev/mii/miivar.h> 80 81 #include <mips/alchemy/include/aureg.h> 82 #include <mips/alchemy/include/auvar.h> 83 #include <mips/alchemy/include/aubusvar.h> 84 #include <mips/alchemy/dev/if_aumacreg.h> 85 86 /* 87 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 88 * must consist of a single DMA segment, and must be aligned to a 2K 89 * boundary. Therefore, this driver does not perform DMA directly 90 * to/from mbufs. Instead, we copy the data to/from buffers allocated 91 * at device attach time. 92 * 93 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 94 * there's little point in not making assumptions based on the CPU type. 95 * We also program the Au1X00 cache to be DMA coherent, so the buffers 96 * are accessed via KSEG0 addresses. 97 */ 98 #define AUMAC_NTXDESC 4 99 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 100 101 #define AUMAC_NRXDESC 4 102 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 103 104 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 105 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 106 107 #define AUMAC_TXBUF_OFFSET 0 108 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 109 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 110 111 struct aumac_buf { 112 vaddr_t buf_vaddr; /* virtual address of buffer */ 113 bus_addr_t buf_paddr; /* DMA address of buffer */ 114 }; 115 116 /* 117 * Software state per device. 118 */ 119 struct aumac_softc { 120 struct device sc_dev; /* generic device information */ 121 bus_space_tag_t sc_st; /* bus space tag */ 122 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 123 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 124 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 125 struct ethercom sc_ethercom; /* Ethernet common data */ 126 void *sc_sdhook; /* shutdown hook */ 127 128 void *sc_ih; /* interrupt cookie */ 129 130 struct mii_data sc_mii; /* MII/media information */ 131 132 struct callout sc_tick_ch; /* tick callout */ 133 134 /* Transmit and receive buffers */ 135 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 136 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 137 void *sc_bufaddr; 138 139 int sc_txfree; /* number of free Tx descriptors */ 140 int sc_txnext; /* next Tx descriptor to use */ 141 int sc_txdirty; /* first dirty Tx descriptor */ 142 143 int sc_rxptr; /* next ready Rx descriptor */ 144 145 #if NRND > 0 146 rndsource_element_t rnd_source; 147 #endif 148 149 #ifdef AUMAC_EVENT_COUNTERS 150 struct evcnt sc_ev_txstall; /* Tx stalled */ 151 struct evcnt sc_ev_rxstall; /* Rx stalled */ 152 struct evcnt sc_ev_txintr; /* Tx interrupts */ 153 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 154 #endif 155 156 uint32_t sc_control; /* MAC_CONTROL contents */ 157 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 158 }; 159 160 #ifdef AUMAC_EVENT_COUNTERS 161 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 162 #else 163 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 164 #endif 165 166 #define AUMAC_INIT_RXDESC(sc, x) \ 167 do { \ 168 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 169 MACDMA_RX_STAT((x)), 0); \ 170 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 171 MACDMA_RX_ADDR((x)), \ 172 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 173 } while (/*CONSTCOND*/0) 174 175 static void aumac_start(struct ifnet *); 176 static void aumac_watchdog(struct ifnet *); 177 static int aumac_ioctl(struct ifnet *, u_long, void *); 178 static int aumac_init(struct ifnet *); 179 static void aumac_stop(struct ifnet *, int); 180 181 static void aumac_shutdown(void *); 182 183 static void aumac_tick(void *); 184 185 static void aumac_set_filter(struct aumac_softc *); 186 187 static void aumac_powerup(struct aumac_softc *); 188 static void aumac_powerdown(struct aumac_softc *); 189 190 static int aumac_intr(void *); 191 static int aumac_txintr(struct aumac_softc *); 192 static int aumac_rxintr(struct aumac_softc *); 193 194 static int aumac_mii_readreg(struct device *, int, int); 195 static void aumac_mii_writereg(struct device *, int, int, int); 196 static void aumac_mii_statchg(struct device *); 197 static int aumac_mii_wait(struct aumac_softc *, const char *); 198 199 static int aumac_match(struct device *, struct cfdata *, void *); 200 static void aumac_attach(struct device *, struct device *, void *); 201 202 int aumac_copy_small = 0; 203 204 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 205 aumac_match, aumac_attach, NULL, NULL); 206 207 static int 208 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 209 { 210 struct aubus_attach_args *aa = aux; 211 212 if (strcmp(aa->aa_name, cf->cf_name) == 0) 213 return (1); 214 215 return (0); 216 } 217 218 static void 219 aumac_attach(struct device *parent, struct device *self, void *aux) 220 { 221 const uint8_t *enaddr; 222 prop_data_t ea; 223 struct aumac_softc *sc = (void *) self; 224 struct aubus_attach_args *aa = aux; 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 struct pglist pglist; 227 paddr_t bufaddr; 228 vaddr_t vbufaddr; 229 int i; 230 231 callout_init(&sc->sc_tick_ch, 0); 232 233 printf(": Au1X00 10/100 Ethernet\n"); 234 235 sc->sc_st = aa->aa_st; 236 237 /* Get the MAC address. */ 238 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-address"); 239 if (ea == NULL) { 240 printf("%s: unable to get mac-addr property\n", 241 sc->sc_dev.dv_xname); 242 return; 243 } 244 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 245 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 246 enaddr = prop_data_data_nocopy(ea); 247 248 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 249 ether_sprintf(enaddr)); 250 251 /* Map the device. */ 252 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 253 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 254 printf("%s: unable to map MAC registers\n", 255 sc->sc_dev.dv_xname); 256 return; 257 } 258 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 259 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 260 printf("%s: unable to map MACEN registers\n", 261 sc->sc_dev.dv_xname); 262 return; 263 } 264 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 265 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 266 printf("%s: unable to map MACDMA registers\n", 267 sc->sc_dev.dv_xname); 268 return; 269 } 270 271 /* Make sure the MAC is powered off. */ 272 aumac_powerdown(sc); 273 274 /* Hook up the interrupt handler. */ 275 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 276 aumac_intr, sc); 277 if (sc->sc_ih == NULL) { 278 printf("%s: unable to register interrupt handler\n", 279 sc->sc_dev.dv_xname); 280 return; 281 } 282 283 /* 284 * Allocate space for the transmit and receive buffers. 285 */ 286 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 287 &pglist, 1, 0)) 288 return; 289 290 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 291 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 292 293 for (i = 0; i < AUMAC_NTXDESC; i++) { 294 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 295 296 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 297 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 298 } 299 300 for (i = 0; i < AUMAC_NRXDESC; i++) { 301 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 302 303 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 304 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 305 } 306 307 /* 308 * Power up the MAC before accessing any MAC registers (including 309 * MII configuration. 310 */ 311 aumac_powerup(sc); 312 313 /* 314 * Initialize the media structures and probe the MII. 315 */ 316 sc->sc_mii.mii_ifp = ifp; 317 sc->sc_mii.mii_readreg = aumac_mii_readreg; 318 sc->sc_mii.mii_writereg = aumac_mii_writereg; 319 sc->sc_mii.mii_statchg = aumac_mii_statchg; 320 sc->sc_ethercom.ec_mii = &sc->sc_mii; 321 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 322 ether_mediastatus); 323 324 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 325 MII_OFFSET_ANY, 0); 326 327 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 328 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 329 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 330 } else 331 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 332 333 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 334 ifp->if_softc = sc; 335 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 336 ifp->if_ioctl = aumac_ioctl; 337 ifp->if_start = aumac_start; 338 ifp->if_watchdog = aumac_watchdog; 339 ifp->if_init = aumac_init; 340 ifp->if_stop = aumac_stop; 341 IFQ_SET_READY(&ifp->if_snd); 342 343 /* Attach the interface. */ 344 if_attach(ifp); 345 ether_ifattach(ifp, enaddr); 346 347 #if NRND > 0 348 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 349 RND_TYPE_NET, 0); 350 #endif 351 352 #ifdef AUMAC_EVENT_COUNTERS 353 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 354 NULL, sc->sc_dev.dv_xname, "txstall"); 355 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 356 NULL, sc->sc_dev.dv_xname, "rxstall"); 357 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 358 NULL, sc->sc_dev.dv_xname, "txintr"); 359 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 360 NULL, sc->sc_dev.dv_xname, "rxintr"); 361 #endif 362 363 /* Make sure the interface is shutdown during reboot. */ 364 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 365 if (sc->sc_sdhook == NULL) 366 printf("%s: WARNING: unable to establish shutdown hook\n", 367 sc->sc_dev.dv_xname); 368 return; 369 } 370 371 /* 372 * aumac_shutdown: 373 * 374 * Make sure the interface is stopped at reboot time. 375 */ 376 static void 377 aumac_shutdown(void *arg) 378 { 379 struct aumac_softc *sc = arg; 380 381 aumac_stop(&sc->sc_ethercom.ec_if, 1); 382 383 /* 384 * XXX aumac_stop leaves device powered up at the moment 385 * XXX but this still isn't enough to keep yamon happy... :-( 386 */ 387 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 388 } 389 390 /* 391 * aumac_start: [ifnet interface function] 392 * 393 * Start packet transmission on the interface. 394 */ 395 static void 396 aumac_start(struct ifnet *ifp) 397 { 398 struct aumac_softc *sc = ifp->if_softc; 399 struct mbuf *m; 400 int nexttx; 401 402 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 403 return; 404 405 /* 406 * Loop through the send queue, setting up transmit descriptors 407 * unitl we drain the queue, or use up all available transmit 408 * descriptors. 409 */ 410 for (;;) { 411 /* Grab a packet off the queue. */ 412 IFQ_POLL(&ifp->if_snd, m); 413 if (m == NULL) 414 return; 415 416 /* Get a spare descriptor. */ 417 if (sc->sc_txfree == 0) { 418 /* No more slots left; notify upper layer. */ 419 ifp->if_flags |= IFF_OACTIVE; 420 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 421 return; 422 } 423 nexttx = sc->sc_txnext; 424 425 IFQ_DEQUEUE(&ifp->if_snd, m); 426 427 /* 428 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 429 */ 430 431 m_copydata(m, 0, m->m_pkthdr.len, 432 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 433 434 /* Zero out the remainder of any short packets. */ 435 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 436 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 437 m->m_pkthdr.len, 0, 438 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 439 440 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 441 MACDMA_TX_STAT(nexttx), 0); 442 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 443 MACDMA_TX_LEN(nexttx), 444 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 445 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 446 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 447 MACDMA_TX_ADDR(nexttx), 448 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 449 /* XXX - needed?? we should be coherent */ 450 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 451 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 452 453 /* Advance the Tx pointer. */ 454 sc->sc_txfree--; 455 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 456 457 /* Pass the packet to any BPF listeners. */ 458 bpf_mtap(ifp, m); 459 460 m_freem(m); 461 462 /* Set a watchdog timer in case the chip flakes out. */ 463 ifp->if_timer = 5; 464 } 465 /* NOTREACHED */ 466 } 467 468 /* 469 * aumac_watchdog: [ifnet interface function] 470 * 471 * Watchdog timer handler. 472 */ 473 static void 474 aumac_watchdog(struct ifnet *ifp) 475 { 476 struct aumac_softc *sc = ifp->if_softc; 477 478 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 479 (void) aumac_init(ifp); 480 481 /* Try to get more packets going. */ 482 aumac_start(ifp); 483 } 484 485 /* 486 * aumac_ioctl: [ifnet interface function] 487 * 488 * Handle control requests from the operator. 489 */ 490 static int 491 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 492 { 493 struct aumac_softc *sc = ifp->if_softc; 494 int s, error; 495 496 s = splnet(); 497 498 error = ether_ioctl(ifp, cmd, data); 499 if (error == ENETRESET) { 500 /* 501 * Multicast list has changed; set the hardware filter 502 * accordingly. 503 */ 504 if (ifp->if_flags & IFF_RUNNING) 505 aumac_set_filter(sc); 506 } 507 508 /* Try to get more packets going. */ 509 aumac_start(ifp); 510 511 splx(s); 512 return (error); 513 } 514 515 /* 516 * aumac_intr: 517 * 518 * Interrupt service routine. 519 */ 520 static int 521 aumac_intr(void *arg) 522 { 523 struct aumac_softc *sc = arg; 524 int status; 525 526 /* 527 * There aren't really any interrupt status bits on the 528 * Au1X00 MAC, and each MAC has a dedicated interrupt 529 * in the CPU's built-in interrupt controller. Just 530 * check for new incoming packets, and then Tx completions 531 * (for status updating). 532 */ 533 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 534 return (0); 535 536 status = aumac_rxintr(sc); 537 status += aumac_txintr(sc); 538 539 #if NRND > 0 540 if (RND_ENABLED(&sc->rnd_source)) 541 rnd_add_uint32(&sc->rnd_source, status); 542 #endif 543 544 return status; 545 } 546 547 /* 548 * aumac_txintr: 549 * 550 * Helper; handle transmit interrupts. 551 */ 552 static int 553 aumac_txintr(struct aumac_softc *sc) 554 { 555 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 556 uint32_t stat; 557 int i; 558 int pkts = 0; 559 560 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 561 i = AUMAC_NEXTTX(i)) { 562 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 563 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 564 break; 565 pkts++; 566 567 /* ACK interrupt. */ 568 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 569 MACDMA_TX_ADDR(i), 0); 570 571 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 572 MACDMA_TX_STAT(i)); 573 574 if (stat & TX_STAT_FA) { 575 /* XXX STATS */ 576 ifp->if_oerrors++; 577 } else 578 ifp->if_opackets++; 579 580 if (stat & TX_STAT_EC) 581 ifp->if_collisions += 16; 582 else 583 ifp->if_collisions += TX_STAT_CC(stat); 584 585 sc->sc_txfree++; 586 ifp->if_flags &= ~IFF_OACTIVE; 587 588 /* Try to queue more packets. */ 589 aumac_start(ifp); 590 } 591 592 if (pkts) 593 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 594 595 /* Update the dirty descriptor pointer. */ 596 sc->sc_txdirty = i; 597 598 /* 599 * If there are no more pending transmissions, cancel the watchdog 600 * timer. 601 */ 602 if (sc->sc_txfree == AUMAC_NTXDESC) 603 ifp->if_timer = 0; 604 605 return pkts; 606 } 607 608 /* 609 * aumac_rxintr: 610 * 611 * Helper; handle receive interrupts. 612 */ 613 static int 614 aumac_rxintr(struct aumac_softc *sc) 615 { 616 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 617 struct mbuf *m; 618 uint32_t stat; 619 int i, len; 620 int pkts = 0; 621 622 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 623 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 624 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 625 break; 626 pkts++; 627 628 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 629 MACDMA_RX_STAT(i)); 630 631 #define PRINTERR(str) \ 632 do { \ 633 error++; \ 634 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 635 } while (0) 636 637 if (stat & RX_STAT_ERRS) { 638 int error = 0; 639 640 #if 0 /* 641 * Missed frames are a semi-frequent occurence with this hardware, 642 * and reporting of them just makes everything run slower and fills 643 * the system log. Be silent. 644 * 645 * Additionally, this missed bit indicates an error with the previous 646 * packet, and not with this one! So PRINTERR is definitely wrong 647 * here. 648 * 649 * These should probably all be converted to evcnt counters anyway. 650 */ 651 if (stat & RX_STAT_MI) 652 PRINTERR("missed frame"); 653 #endif 654 if (stat & RX_STAT_UC) 655 PRINTERR("unknown control frame"); 656 if (stat & RX_STAT_LE) 657 PRINTERR("short frame"); 658 if (stat & RX_STAT_CR) 659 PRINTERR("CRC error"); 660 if (stat & RX_STAT_ME) 661 PRINTERR("medium error"); 662 if (stat & RX_STAT_CS) 663 PRINTERR("late collision"); 664 if (stat & RX_STAT_FL) 665 PRINTERR("frame too big"); 666 if (stat & RX_STAT_RF) 667 PRINTERR("runt frame (collision)"); 668 if (stat & RX_STAT_WT) 669 PRINTERR("watch dog"); 670 if (stat & RX_STAT_DB) { 671 if (stat & (RX_STAT_CS | RX_STAT_RF | 672 RX_STAT_CR)) { 673 if (!error) 674 goto pktok; 675 } else 676 PRINTERR("dribbling bit"); 677 } 678 #undef PRINTERR 679 ifp->if_ierrors++; 680 681 dropit: 682 /* reuse the current descriptor */ 683 AUMAC_INIT_RXDESC(sc, i); 684 continue; 685 } 686 pktok: 687 len = RX_STAT_L(stat); 688 689 /* 690 * The Au1X00 MAC includes the CRC with every packet; 691 * trim it off here. 692 */ 693 len -= ETHER_CRC_LEN; 694 695 /* 696 * Truncate the packet if it's too big to fit in 697 * a single mbuf cluster. 698 */ 699 if (len > MCLBYTES - 2) 700 len = MCLBYTES - 2; 701 702 MGETHDR(m, M_DONTWAIT, MT_DATA); 703 if (m == NULL) { 704 printf("%s: unable to allocate Rx mbuf\n", 705 sc->sc_dev.dv_xname); 706 goto dropit; 707 } 708 if (len > MHLEN - 2) { 709 MCLGET(m, M_DONTWAIT); 710 if ((m->m_flags & M_EXT) == 0) { 711 printf("%s: unable to allocate Rx cluster\n", 712 sc->sc_dev.dv_xname); 713 m_freem(m); 714 goto dropit; 715 } 716 } 717 718 m->m_data += 2; /* align payload */ 719 memcpy(mtod(m, void *), 720 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 721 AUMAC_INIT_RXDESC(sc, i); 722 723 m->m_pkthdr.rcvif = ifp; 724 m->m_pkthdr.len = m->m_len = len; 725 726 /* Pass this up to any BPF listeners. */ 727 bpf_mtap(ifp, m); 728 729 /* Pass it on. */ 730 (*ifp->if_input)(ifp, m); 731 ifp->if_ipackets++; 732 } 733 if (pkts) 734 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 735 if (pkts == AUMAC_NRXDESC) 736 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 737 738 /* Update the receive pointer. */ 739 sc->sc_rxptr = i; 740 741 return pkts; 742 } 743 744 /* 745 * aumac_tick: 746 * 747 * One second timer, used to tick the MII. 748 */ 749 static void 750 aumac_tick(void *arg) 751 { 752 struct aumac_softc *sc = arg; 753 int s; 754 755 s = splnet(); 756 mii_tick(&sc->sc_mii); 757 splx(s); 758 759 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 760 } 761 762 /* 763 * aumac_init: [ifnet interface function] 764 * 765 * Initialize the interface. Must be called at splnet(). 766 */ 767 static int 768 aumac_init(struct ifnet *ifp) 769 { 770 struct aumac_softc *sc = ifp->if_softc; 771 int i, error = 0; 772 773 /* Cancel any pending I/O, reset MAC. */ 774 aumac_stop(ifp, 0); 775 776 /* Set up the transmit ring. */ 777 for (i = 0; i < AUMAC_NTXDESC; i++) { 778 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 779 MACDMA_TX_STAT(i), 0); 780 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 781 MACDMA_TX_LEN(i), 0); 782 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 783 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 784 } 785 sc->sc_txfree = AUMAC_NTXDESC; 786 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 787 MACDMA_TX_ADDR(0))); 788 sc->sc_txdirty = sc->sc_txnext; 789 790 /* Set up the receive ring. */ 791 for (i = 0; i < AUMAC_NRXDESC; i++) 792 AUMAC_INIT_RXDESC(sc, i); 793 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 794 MACDMA_RX_ADDR(0))); 795 796 /* 797 * Power up the MAC. 798 */ 799 aumac_powerup(sc); 800 801 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 802 #if _BYTE_ORDER == _BIG_ENDIAN 803 sc->sc_control |= CONTROL_EM; 804 #endif 805 806 /* Set the media. */ 807 if ((error = ether_mediachange(ifp)) != 0) 808 goto out; 809 810 /* 811 * Set the receive filter. This will actually start the transmit 812 * and receive processes. 813 */ 814 aumac_set_filter(sc); 815 816 /* Start the one second clock. */ 817 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 818 819 /* ...all done! */ 820 ifp->if_flags |= IFF_RUNNING; 821 ifp->if_flags &= ~IFF_OACTIVE; 822 823 out: 824 if (error) 825 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 826 return (error); 827 } 828 829 /* 830 * aumac_stop: [ifnet interface function] 831 * 832 * Stop transmission on the interface. 833 */ 834 static void 835 aumac_stop(struct ifnet *ifp, int disable) 836 { 837 struct aumac_softc *sc = ifp->if_softc; 838 839 /* Stop the one-second clock. */ 840 callout_stop(&sc->sc_tick_ch); 841 842 /* Down the MII. */ 843 mii_down(&sc->sc_mii); 844 845 /* Stop the transmit and receive processes. */ 846 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 847 848 /* Power down/reset the MAC. */ 849 aumac_powerdown(sc); 850 851 /* Mark the interface as down and cancel the watchdog timer. */ 852 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 853 ifp->if_timer = 0; 854 } 855 856 /* 857 * aumac_powerdown: 858 * 859 * Power down the MAC. 860 */ 861 static void 862 aumac_powerdown(struct aumac_softc *sc) 863 { 864 865 /* Disable the MAC clocks, and place the device in reset. */ 866 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 867 868 // delay(10000); 869 } 870 871 /* 872 * aumac_powerup: 873 * 874 * Bring the device out of reset. 875 */ 876 static void 877 aumac_powerup(struct aumac_softc *sc) 878 { 879 880 /* Enable clocks to the MAC. */ 881 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 882 883 /* Enable MAC, coherent transactions, pass only valid frames. */ 884 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 885 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 886 887 delay(20000); 888 } 889 890 /* 891 * aumac_set_filter: 892 * 893 * Set up the receive filter. 894 */ 895 static void 896 aumac_set_filter(struct aumac_softc *sc) 897 { 898 struct ethercom *ec = &sc->sc_ethercom; 899 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 900 struct ether_multi *enm; 901 struct ether_multistep step; 902 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 903 uint32_t mchash[2], crc; 904 905 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 906 907 /* Stop the receiver. */ 908 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 909 sc->sc_control & ~CONTROL_RE); 910 911 if (ifp->if_flags & IFF_PROMISC) { 912 sc->sc_control |= CONTROL_PR; 913 goto allmulti; 914 } 915 916 /* Set the station address. */ 917 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 918 enaddr[4] | (enaddr[5] << 8)); 919 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 920 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 921 (enaddr[3] << 24)); 922 923 sc->sc_control |= CONTROL_HP; 924 925 mchash[0] = mchash[1] = 0; 926 927 /* 928 * Set up the multicast address filter by passing all multicast 929 * addresses through a CRC generator, and then using the high 930 * order 6 bits as an index into the 64-bit multicast hash table. 931 * The high order bits select the word, while the rest of the bits 932 * select the bit within the word. 933 */ 934 ETHER_FIRST_MULTI(step, ec, enm); 935 while (enm != NULL) { 936 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 937 /* 938 * We must listen to a range of multicast addresses. 939 * For now, just accept all multicasts, rather than 940 * trying to set only those filter bits needed to match 941 * the range. (At this time, the only use of address 942 * ranges is for IP multicast routing, for which the 943 * range is large enough to require all bits set.) 944 */ 945 goto allmulti; 946 } 947 948 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 949 950 /* Just want the 6 most significant bits. */ 951 crc >>= 26; 952 953 /* Set the corresponding bit in the filter. */ 954 mchash[crc >> 5] |= 1U << (crc & 0x1f); 955 956 ETHER_NEXT_MULTI(step, enm); 957 } 958 959 ifp->if_flags &= ~IFF_ALLMULTI; 960 961 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 962 mchash[1]); 963 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 964 mchash[0]); 965 966 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 967 sc->sc_control); 968 return; 969 970 allmulti: 971 sc->sc_control |= CONTROL_PM; 972 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 973 sc->sc_control); 974 } 975 976 /* 977 * aumac_mii_wait: 978 * 979 * Wait for the MII interface to not be busy. 980 */ 981 static int 982 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 983 { 984 int i; 985 986 for (i = 0; i < 10000; i++) { 987 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 988 MAC_MIICTRL) & MIICTRL_MB) == 0) 989 return (0); 990 delay(10); 991 } 992 993 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 994 return (1); 995 } 996 997 /* 998 * aumac_mii_readreg: [mii interface function] 999 * 1000 * Read a PHY register on the MII. 1001 */ 1002 static int 1003 aumac_mii_readreg(struct device *self, int phy, int reg) 1004 { 1005 struct aumac_softc *sc = (void *) self; 1006 1007 if (aumac_mii_wait(sc, "become ready")) 1008 return (0); 1009 1010 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1011 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1012 1013 if (aumac_mii_wait(sc, "complete")) 1014 return (0); 1015 1016 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1017 MIIDATA_MASK); 1018 } 1019 1020 /* 1021 * aumac_mii_writereg: [mii interface function] 1022 * 1023 * Write a PHY register on the MII. 1024 */ 1025 static void 1026 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1027 { 1028 struct aumac_softc *sc = (void *) self; 1029 1030 if (aumac_mii_wait(sc, "become ready")) 1031 return; 1032 1033 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1034 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1035 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1036 1037 (void) aumac_mii_wait(sc, "complete"); 1038 } 1039 1040 /* 1041 * aumac_mii_statchg: [mii interface function] 1042 * 1043 * Callback from MII layer when media changes. 1044 */ 1045 static void 1046 aumac_mii_statchg(struct device *self) 1047 { 1048 struct aumac_softc *sc = (void *) self; 1049 1050 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1051 sc->sc_control |= CONTROL_F; 1052 else 1053 sc->sc_control &= ~CONTROL_F; 1054 1055 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1056 sc->sc_control); 1057 } 1058