1 /* $NetBSD: if_aumac.c,v 1.44 2018/06/26 06:47:58 msaitoh Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.44 2018/06/26 06:47:58 msaitoh Exp $"); 50 51 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/callout.h> 56 #include <sys/device.h> 57 #include <sys/endian.h> 58 #include <sys/errno.h> 59 #include <sys/intr.h> 60 #include <sys/ioctl.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/socket.h> 65 66 #include <uvm/uvm.h> /* for PAGE_SIZE */ 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #include <net/bpf.h> 74 #include <sys/rndsource.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <mips/alchemy/include/aureg.h> 80 #include <mips/alchemy/include/auvar.h> 81 #include <mips/alchemy/include/aubusvar.h> 82 #include <mips/alchemy/dev/if_aumacreg.h> 83 84 /* 85 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 86 * must consist of a single DMA segment, and must be aligned to a 2K 87 * boundary. Therefore, this driver does not perform DMA directly 88 * to/from mbufs. Instead, we copy the data to/from buffers allocated 89 * at device attach time. 90 * 91 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 92 * there's little point in not making assumptions based on the CPU type. 93 * We also program the Au1X00 cache to be DMA coherent, so the buffers 94 * are accessed via KSEG0 addresses. 95 */ 96 #define AUMAC_NTXDESC 4 97 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 98 99 #define AUMAC_NRXDESC 4 100 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 101 102 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 103 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 104 105 #define AUMAC_TXBUF_OFFSET 0 106 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 107 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 108 109 struct aumac_buf { 110 vaddr_t buf_vaddr; /* virtual address of buffer */ 111 bus_addr_t buf_paddr; /* DMA address of buffer */ 112 }; 113 114 /* 115 * Software state per device. 116 */ 117 struct aumac_softc { 118 device_t sc_dev; /* generic device information */ 119 bus_space_tag_t sc_st; /* bus space tag */ 120 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 121 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 122 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 123 struct ethercom sc_ethercom; /* Ethernet common data */ 124 void *sc_sdhook; /* shutdown hook */ 125 126 int sc_irq; 127 void *sc_ih; /* interrupt cookie */ 128 129 struct mii_data sc_mii; /* MII/media information */ 130 131 struct callout sc_tick_ch; /* tick callout */ 132 133 /* Transmit and receive buffers */ 134 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 135 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 136 void *sc_bufaddr; 137 138 int sc_txfree; /* number of free Tx descriptors */ 139 int sc_txnext; /* next Tx descriptor to use */ 140 int sc_txdirty; /* first dirty Tx descriptor */ 141 142 int sc_rxptr; /* next ready Rx descriptor */ 143 144 krndsource_t rnd_source; 145 146 #ifdef AUMAC_EVENT_COUNTERS 147 struct evcnt sc_ev_txstall; /* Tx stalled */ 148 struct evcnt sc_ev_rxstall; /* Rx stalled */ 149 struct evcnt sc_ev_txintr; /* Tx interrupts */ 150 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 151 #endif 152 153 uint32_t sc_control; /* MAC_CONTROL contents */ 154 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 155 }; 156 157 #ifdef AUMAC_EVENT_COUNTERS 158 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 159 #else 160 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 161 #endif 162 163 #define AUMAC_INIT_RXDESC(sc, x) \ 164 do { \ 165 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 166 MACDMA_RX_STAT((x)), 0); \ 167 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 168 MACDMA_RX_ADDR((x)), \ 169 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 170 } while (/*CONSTCOND*/0) 171 172 static void aumac_start(struct ifnet *); 173 static void aumac_watchdog(struct ifnet *); 174 static int aumac_ioctl(struct ifnet *, u_long, void *); 175 static int aumac_init(struct ifnet *); 176 static void aumac_stop(struct ifnet *, int); 177 178 static void aumac_shutdown(void *); 179 180 static void aumac_tick(void *); 181 182 static void aumac_set_filter(struct aumac_softc *); 183 184 static void aumac_powerup(struct aumac_softc *); 185 static void aumac_powerdown(struct aumac_softc *); 186 187 static int aumac_intr(void *); 188 static int aumac_txintr(struct aumac_softc *); 189 static int aumac_rxintr(struct aumac_softc *); 190 191 static int aumac_mii_readreg(device_t, int, int); 192 static void aumac_mii_writereg(device_t, int, int, int); 193 static void aumac_mii_statchg(struct ifnet *); 194 static int aumac_mii_wait(struct aumac_softc *, const char *); 195 196 static int aumac_match(device_t, struct cfdata *, void *); 197 static void aumac_attach(device_t, device_t, void *); 198 199 int aumac_copy_small = 0; 200 201 CFATTACH_DECL_NEW(aumac, sizeof(struct aumac_softc), 202 aumac_match, aumac_attach, NULL, NULL); 203 204 static int 205 aumac_match(device_t parent, struct cfdata *cf, void *aux) 206 { 207 struct aubus_attach_args *aa = aux; 208 209 if (strcmp(aa->aa_name, cf->cf_name) == 0) 210 return (1); 211 212 return (0); 213 } 214 215 static void 216 aumac_attach(device_t parent, device_t self, void *aux) 217 { 218 const uint8_t *enaddr; 219 prop_data_t ea; 220 struct aumac_softc *sc = device_private(self); 221 struct aubus_attach_args *aa = aux; 222 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 223 struct pglist pglist; 224 paddr_t bufaddr; 225 vaddr_t vbufaddr; 226 int i; 227 228 callout_init(&sc->sc_tick_ch, 0); 229 230 aprint_normal(": Au1X00 10/100 Ethernet\n"); 231 aprint_naive("\n"); 232 233 sc->sc_dev = self; 234 sc->sc_st = aa->aa_st; 235 236 /* Get the MAC address. */ 237 ea = prop_dictionary_get(device_properties(self), "mac-address"); 238 if (ea == NULL) { 239 aprint_error_dev(self, "unable to get mac-addr property\n"); 240 return; 241 } 242 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 243 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 244 enaddr = prop_data_data_nocopy(ea); 245 246 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 247 248 /* Map the device. */ 249 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 250 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 251 aprint_error_dev(self, "unable to map MAC registers\n"); 252 return; 253 } 254 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 255 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 256 aprint_error_dev(self, "unable to map MACEN registers\n"); 257 return; 258 } 259 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 260 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 261 aprint_error_dev(self, "unable to map MACDMA registers\n"); 262 return; 263 } 264 265 /* Make sure the MAC is powered off. */ 266 aumac_powerdown(sc); 267 268 /* Hook up the interrupt handler. */ 269 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 270 aumac_intr, sc); 271 if (sc->sc_ih == NULL) { 272 aprint_error_dev(self, 273 "unable to register interrupt handler\n"); 274 return; 275 } 276 sc->sc_irq = aa->aa_irq[0]; 277 au_intr_disable(sc->sc_irq); 278 279 /* 280 * Allocate space for the transmit and receive buffers. 281 */ 282 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 283 &pglist, 1, 0)) 284 return; 285 286 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 287 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 288 289 for (i = 0; i < AUMAC_NTXDESC; i++) { 290 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 291 292 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 293 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 294 } 295 296 for (i = 0; i < AUMAC_NRXDESC; i++) { 297 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 298 299 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 300 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 301 } 302 303 /* 304 * Power up the MAC before accessing any MAC registers (including 305 * MII configuration. 306 */ 307 aumac_powerup(sc); 308 309 /* 310 * Initialize the media structures and probe the MII. 311 */ 312 sc->sc_mii.mii_ifp = ifp; 313 sc->sc_mii.mii_readreg = aumac_mii_readreg; 314 sc->sc_mii.mii_writereg = aumac_mii_writereg; 315 sc->sc_mii.mii_statchg = aumac_mii_statchg; 316 sc->sc_ethercom.ec_mii = &sc->sc_mii; 317 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 318 ether_mediastatus); 319 320 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 321 MII_OFFSET_ANY, 0); 322 323 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 324 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 325 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 326 } else 327 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 328 329 strcpy(ifp->if_xname, device_xname(self)); 330 ifp->if_softc = sc; 331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332 ifp->if_ioctl = aumac_ioctl; 333 ifp->if_start = aumac_start; 334 ifp->if_watchdog = aumac_watchdog; 335 ifp->if_init = aumac_init; 336 ifp->if_stop = aumac_stop; 337 IFQ_SET_READY(&ifp->if_snd); 338 339 /* Attach the interface. */ 340 if_attach(ifp); 341 if_deferred_start_init(ifp, NULL); 342 ether_ifattach(ifp, enaddr); 343 344 rnd_attach_source(&sc->rnd_source, device_xname(self), 345 RND_TYPE_NET, RND_FLAG_DEFAULT); 346 347 #ifdef AUMAC_EVENT_COUNTERS 348 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 349 NULL, device_xname(self), "txstall"); 350 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 351 NULL, device_xname(self), "rxstall"); 352 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 353 NULL, device_xname(self), "txintr"); 354 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 355 NULL, device_xname(self), "rxintr"); 356 #endif 357 358 /* Make sure the interface is shutdown during reboot. */ 359 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 360 if (sc->sc_sdhook == NULL) 361 aprint_error_dev(self, 362 "WARNING: unable to establish shutdown hook\n"); 363 return; 364 } 365 366 /* 367 * aumac_shutdown: 368 * 369 * Make sure the interface is stopped at reboot time. 370 */ 371 static void 372 aumac_shutdown(void *arg) 373 { 374 struct aumac_softc *sc = arg; 375 376 aumac_stop(&sc->sc_ethercom.ec_if, 1); 377 378 /* 379 * XXX aumac_stop leaves device powered up at the moment 380 * XXX but this still isn't enough to keep yamon happy... :-( 381 */ 382 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 383 } 384 385 /* 386 * aumac_start: [ifnet interface function] 387 * 388 * Start packet transmission on the interface. 389 */ 390 static void 391 aumac_start(struct ifnet *ifp) 392 { 393 struct aumac_softc *sc = ifp->if_softc; 394 struct mbuf *m; 395 int nexttx; 396 397 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 398 return; 399 400 /* 401 * Loop through the send queue, setting up transmit descriptors 402 * unitl we drain the queue, or use up all available transmit 403 * descriptors. 404 */ 405 for (;;) { 406 /* Grab a packet off the queue. */ 407 IFQ_POLL(&ifp->if_snd, m); 408 if (m == NULL) 409 return; 410 411 /* Get a spare descriptor. */ 412 if (sc->sc_txfree == 0) { 413 /* No more slots left; notify upper layer. */ 414 ifp->if_flags |= IFF_OACTIVE; 415 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 416 return; 417 } 418 nexttx = sc->sc_txnext; 419 420 IFQ_DEQUEUE(&ifp->if_snd, m); 421 422 /* 423 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 424 */ 425 426 m_copydata(m, 0, m->m_pkthdr.len, 427 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 428 429 /* Zero out the remainder of any short packets. */ 430 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 431 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 432 m->m_pkthdr.len, 0, 433 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 434 435 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 436 MACDMA_TX_STAT(nexttx), 0); 437 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 438 MACDMA_TX_LEN(nexttx), 439 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 440 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 441 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 442 MACDMA_TX_ADDR(nexttx), 443 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 444 /* XXX - needed?? we should be coherent */ 445 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 446 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 447 448 /* Advance the Tx pointer. */ 449 sc->sc_txfree--; 450 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 451 452 /* Pass the packet to any BPF listeners. */ 453 bpf_mtap(ifp, m, BPF_D_OUT); 454 455 m_freem(m); 456 457 /* Set a watchdog timer in case the chip flakes out. */ 458 ifp->if_timer = 5; 459 } 460 /* NOTREACHED */ 461 } 462 463 /* 464 * aumac_watchdog: [ifnet interface function] 465 * 466 * Watchdog timer handler. 467 */ 468 static void 469 aumac_watchdog(struct ifnet *ifp) 470 { 471 struct aumac_softc *sc = ifp->if_softc; 472 473 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 474 (void) aumac_init(ifp); 475 476 /* Try to get more packets going. */ 477 aumac_start(ifp); 478 } 479 480 /* 481 * aumac_ioctl: [ifnet interface function] 482 * 483 * Handle control requests from the operator. 484 */ 485 static int 486 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 487 { 488 struct aumac_softc *sc = ifp->if_softc; 489 int s, error; 490 491 s = splnet(); 492 493 error = ether_ioctl(ifp, cmd, data); 494 if (error == ENETRESET) { 495 /* 496 * Multicast list has changed; set the hardware filter 497 * accordingly. 498 */ 499 if (ifp->if_flags & IFF_RUNNING) 500 aumac_set_filter(sc); 501 error = 0; 502 } 503 504 /* Try to get more packets going. */ 505 aumac_start(ifp); 506 507 splx(s); 508 return (error); 509 } 510 511 /* 512 * aumac_intr: 513 * 514 * Interrupt service routine. 515 */ 516 static int 517 aumac_intr(void *arg) 518 { 519 struct aumac_softc *sc = arg; 520 int status; 521 522 /* 523 * There aren't really any interrupt status bits on the 524 * Au1X00 MAC, and each MAC has a dedicated interrupt 525 * in the CPU's built-in interrupt controller. Just 526 * check for new incoming packets, and then Tx completions 527 * (for status updating). 528 */ 529 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 530 return (0); 531 532 status = aumac_rxintr(sc); 533 status += aumac_txintr(sc); 534 535 rnd_add_uint32(&sc->rnd_source, status); 536 537 return status; 538 } 539 540 /* 541 * aumac_txintr: 542 * 543 * Helper; handle transmit interrupts. 544 */ 545 static int 546 aumac_txintr(struct aumac_softc *sc) 547 { 548 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 549 uint32_t stat; 550 int i; 551 int pkts = 0; 552 553 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 554 i = AUMAC_NEXTTX(i)) { 555 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 556 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 557 break; 558 pkts++; 559 560 /* ACK interrupt. */ 561 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 562 MACDMA_TX_ADDR(i), 0); 563 564 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 565 MACDMA_TX_STAT(i)); 566 567 if (stat & TX_STAT_FA) { 568 /* XXX STATS */ 569 ifp->if_oerrors++; 570 } else 571 ifp->if_opackets++; 572 573 if (stat & TX_STAT_EC) 574 ifp->if_collisions += 16; 575 else 576 ifp->if_collisions += TX_STAT_CC(stat); 577 578 sc->sc_txfree++; 579 ifp->if_flags &= ~IFF_OACTIVE; 580 581 /* Try to queue more packets. */ 582 if_schedule_deferred_start(ifp); 583 } 584 585 if (pkts) 586 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 587 588 /* Update the dirty descriptor pointer. */ 589 sc->sc_txdirty = i; 590 591 /* 592 * If there are no more pending transmissions, cancel the watchdog 593 * timer. 594 */ 595 if (sc->sc_txfree == AUMAC_NTXDESC) 596 ifp->if_timer = 0; 597 598 return pkts; 599 } 600 601 /* 602 * aumac_rxintr: 603 * 604 * Helper; handle receive interrupts. 605 */ 606 static int 607 aumac_rxintr(struct aumac_softc *sc) 608 { 609 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 610 struct mbuf *m; 611 uint32_t stat; 612 int i, len; 613 int pkts = 0; 614 615 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 616 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 617 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 618 break; 619 pkts++; 620 621 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 622 MACDMA_RX_STAT(i)); 623 624 #define PRINTERR(str) \ 625 do { \ 626 error++; \ 627 printf("%s: %s\n", device_xname(sc->sc_dev), str); \ 628 } while (0) 629 630 if (stat & RX_STAT_ERRS) { 631 int error = 0; 632 633 #if 0 /* 634 * Missed frames are a semi-frequent occurence with this hardware, 635 * and reporting of them just makes everything run slower and fills 636 * the system log. Be silent. 637 * 638 * Additionally, this missed bit indicates an error with the previous 639 * packet, and not with this one! So PRINTERR is definitely wrong 640 * here. 641 * 642 * These should probably all be converted to evcnt counters anyway. 643 */ 644 if (stat & RX_STAT_MI) 645 PRINTERR("missed frame"); 646 #endif 647 if (stat & RX_STAT_UC) 648 PRINTERR("unknown control frame"); 649 if (stat & RX_STAT_LE) 650 PRINTERR("short frame"); 651 if (stat & RX_STAT_CR) 652 PRINTERR("CRC error"); 653 if (stat & RX_STAT_ME) 654 PRINTERR("medium error"); 655 if (stat & RX_STAT_CS) 656 PRINTERR("late collision"); 657 if (stat & RX_STAT_FL) 658 PRINTERR("frame too big"); 659 if (stat & RX_STAT_RF) 660 PRINTERR("runt frame (collision)"); 661 if (stat & RX_STAT_WT) 662 PRINTERR("watch dog"); 663 if (stat & RX_STAT_DB) { 664 if (stat & (RX_STAT_CS | RX_STAT_RF | 665 RX_STAT_CR)) { 666 if (!error) 667 goto pktok; 668 } else 669 PRINTERR("dribbling bit"); 670 } 671 #undef PRINTERR 672 ifp->if_ierrors++; 673 674 dropit: 675 /* reuse the current descriptor */ 676 AUMAC_INIT_RXDESC(sc, i); 677 continue; 678 } 679 pktok: 680 len = RX_STAT_L(stat); 681 682 /* 683 * The Au1X00 MAC includes the CRC with every packet; 684 * trim it off here. 685 */ 686 len -= ETHER_CRC_LEN; 687 688 /* 689 * Truncate the packet if it's too big to fit in 690 * a single mbuf cluster. 691 */ 692 if (len > MCLBYTES - 2) 693 len = MCLBYTES - 2; 694 695 MGETHDR(m, M_DONTWAIT, MT_DATA); 696 if (m == NULL) { 697 printf("%s: unable to allocate Rx mbuf\n", 698 device_xname(sc->sc_dev)); 699 goto dropit; 700 } 701 if (len > MHLEN - 2) { 702 MCLGET(m, M_DONTWAIT); 703 if ((m->m_flags & M_EXT) == 0) { 704 printf("%s: unable to allocate Rx cluster\n", 705 device_xname(sc->sc_dev)); 706 m_freem(m); 707 goto dropit; 708 } 709 } 710 711 m->m_data += 2; /* align payload */ 712 memcpy(mtod(m, void *), 713 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 714 AUMAC_INIT_RXDESC(sc, i); 715 716 m_set_rcvif(m, ifp); 717 m->m_pkthdr.len = m->m_len = len; 718 719 /* Pass it on. */ 720 if_percpuq_enqueue(ifp->if_percpuq, m); 721 } 722 if (pkts) 723 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 724 if (pkts == AUMAC_NRXDESC) 725 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 726 727 /* Update the receive pointer. */ 728 sc->sc_rxptr = i; 729 730 return pkts; 731 } 732 733 /* 734 * aumac_tick: 735 * 736 * One second timer, used to tick the MII. 737 */ 738 static void 739 aumac_tick(void *arg) 740 { 741 struct aumac_softc *sc = arg; 742 int s; 743 744 s = splnet(); 745 mii_tick(&sc->sc_mii); 746 splx(s); 747 748 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 749 } 750 751 /* 752 * aumac_init: [ifnet interface function] 753 * 754 * Initialize the interface. Must be called at splnet(). 755 */ 756 static int 757 aumac_init(struct ifnet *ifp) 758 { 759 struct aumac_softc *sc = ifp->if_softc; 760 int i, error = 0; 761 762 /* Cancel any pending I/O, reset MAC. */ 763 aumac_stop(ifp, 0); 764 765 /* Set up the transmit ring. */ 766 for (i = 0; i < AUMAC_NTXDESC; i++) { 767 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 768 MACDMA_TX_STAT(i), 0); 769 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 770 MACDMA_TX_LEN(i), 0); 771 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 772 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 773 } 774 sc->sc_txfree = AUMAC_NTXDESC; 775 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 776 MACDMA_TX_ADDR(0))); 777 sc->sc_txdirty = sc->sc_txnext; 778 779 /* Set up the receive ring. */ 780 for (i = 0; i < AUMAC_NRXDESC; i++) 781 AUMAC_INIT_RXDESC(sc, i); 782 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 783 MACDMA_RX_ADDR(0))); 784 785 /* 786 * Power up the MAC. 787 */ 788 aumac_powerup(sc); 789 790 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 791 #if _BYTE_ORDER == _BIG_ENDIAN 792 sc->sc_control |= CONTROL_EM; 793 #endif 794 795 /* Set the media. */ 796 if ((error = ether_mediachange(ifp)) != 0) 797 goto out; 798 799 /* 800 * Set the receive filter. This will actually start the transmit 801 * and receive processes. 802 */ 803 aumac_set_filter(sc); 804 805 /* Start the one second clock. */ 806 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 807 808 /* ...all done! */ 809 ifp->if_flags |= IFF_RUNNING; 810 ifp->if_flags &= ~IFF_OACTIVE; 811 812 au_intr_enable(sc->sc_irq); 813 out: 814 if (error) 815 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 816 return (error); 817 } 818 819 /* 820 * aumac_stop: [ifnet interface function] 821 * 822 * Stop transmission on the interface. 823 */ 824 static void 825 aumac_stop(struct ifnet *ifp, int disable) 826 { 827 struct aumac_softc *sc = ifp->if_softc; 828 829 /* Stop the one-second clock. */ 830 callout_stop(&sc->sc_tick_ch); 831 832 /* Down the MII. */ 833 mii_down(&sc->sc_mii); 834 835 /* Stop the transmit and receive processes. */ 836 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 837 838 /* Power down/reset the MAC. */ 839 aumac_powerdown(sc); 840 841 au_intr_disable(sc->sc_irq); 842 843 /* Mark the interface as down and cancel the watchdog timer. */ 844 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 845 ifp->if_timer = 0; 846 } 847 848 /* 849 * aumac_powerdown: 850 * 851 * Power down the MAC. 852 */ 853 static void 854 aumac_powerdown(struct aumac_softc *sc) 855 { 856 857 /* Disable the MAC clocks, and place the device in reset. */ 858 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 859 860 // delay(10000); 861 } 862 863 /* 864 * aumac_powerup: 865 * 866 * Bring the device out of reset. 867 */ 868 static void 869 aumac_powerup(struct aumac_softc *sc) 870 { 871 872 /* Enable clocks to the MAC. */ 873 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 874 875 /* Enable MAC, coherent transactions, pass only valid frames. */ 876 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 877 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 878 879 delay(20000); 880 } 881 882 /* 883 * aumac_set_filter: 884 * 885 * Set up the receive filter. 886 */ 887 static void 888 aumac_set_filter(struct aumac_softc *sc) 889 { 890 struct ethercom *ec = &sc->sc_ethercom; 891 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 892 struct ether_multi *enm; 893 struct ether_multistep step; 894 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 895 uint32_t mchash[2], crc; 896 897 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 898 899 /* Stop the receiver. */ 900 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 901 sc->sc_control & ~CONTROL_RE); 902 903 if (ifp->if_flags & IFF_PROMISC) { 904 sc->sc_control |= CONTROL_PR; 905 goto allmulti; 906 } 907 908 /* Set the station address. */ 909 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 910 enaddr[4] | (enaddr[5] << 8)); 911 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 912 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 913 (enaddr[3] << 24)); 914 915 sc->sc_control |= CONTROL_HP; 916 917 mchash[0] = mchash[1] = 0; 918 919 /* 920 * Set up the multicast address filter by passing all multicast 921 * addresses through a CRC generator, and then using the high 922 * order 6 bits as an index into the 64-bit multicast hash table. 923 * The high order bits select the word, while the rest of the bits 924 * select the bit within the word. 925 */ 926 ETHER_FIRST_MULTI(step, ec, enm); 927 while (enm != NULL) { 928 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 929 /* 930 * We must listen to a range of multicast addresses. 931 * For now, just accept all multicasts, rather than 932 * trying to set only those filter bits needed to match 933 * the range. (At this time, the only use of address 934 * ranges is for IP multicast routing, for which the 935 * range is large enough to require all bits set.) 936 */ 937 goto allmulti; 938 } 939 940 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 941 942 /* Just want the 6 most significant bits. */ 943 crc >>= 26; 944 945 /* Set the corresponding bit in the filter. */ 946 mchash[crc >> 5] |= 1U << (crc & 0x1f); 947 948 ETHER_NEXT_MULTI(step, enm); 949 } 950 951 ifp->if_flags &= ~IFF_ALLMULTI; 952 953 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 954 mchash[1]); 955 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 956 mchash[0]); 957 958 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 959 sc->sc_control); 960 return; 961 962 allmulti: 963 sc->sc_control |= CONTROL_PM; 964 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 965 sc->sc_control); 966 } 967 968 /* 969 * aumac_mii_wait: 970 * 971 * Wait for the MII interface to not be busy. 972 */ 973 static int 974 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 975 { 976 int i; 977 978 for (i = 0; i < 10000; i++) { 979 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 980 MAC_MIICTRL) & MIICTRL_MB) == 0) 981 return (0); 982 delay(10); 983 } 984 985 printf("%s: MII failed to %s\n", device_xname(sc->sc_dev), msg); 986 return (1); 987 } 988 989 /* 990 * aumac_mii_readreg: [mii interface function] 991 * 992 * Read a PHY register on the MII. 993 */ 994 static int 995 aumac_mii_readreg(device_t self, int phy, int reg) 996 { 997 struct aumac_softc *sc = device_private(self); 998 999 if (aumac_mii_wait(sc, "become ready")) 1000 return (0); 1001 1002 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1003 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1004 1005 if (aumac_mii_wait(sc, "complete")) 1006 return (0); 1007 1008 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1009 MIIDATA_MASK); 1010 } 1011 1012 /* 1013 * aumac_mii_writereg: [mii interface function] 1014 * 1015 * Write a PHY register on the MII. 1016 */ 1017 static void 1018 aumac_mii_writereg(device_t self, int phy, int reg, int val) 1019 { 1020 struct aumac_softc *sc = device_private(self); 1021 1022 if (aumac_mii_wait(sc, "become ready")) 1023 return; 1024 1025 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1026 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1027 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1028 1029 (void) aumac_mii_wait(sc, "complete"); 1030 } 1031 1032 /* 1033 * aumac_mii_statchg: [mii interface function] 1034 * 1035 * Callback from MII layer when media changes. 1036 */ 1037 static void 1038 aumac_mii_statchg(struct ifnet *ifp) 1039 { 1040 struct aumac_softc *sc = ifp->if_softc; 1041 1042 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1043 sc->sc_control |= CONTROL_F; 1044 else 1045 sc->sc_control &= ~CONTROL_F; 1046 1047 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1048 sc->sc_control); 1049 } 1050