1 /* $NetBSD: if_aumac.c,v 1.34 2012/02/02 19:42:59 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.34 2012/02/02 19:42:59 tls Exp $"); 50 51 52 53 #include <sys/param.h> 54 #include <sys/bus.h> 55 #include <sys/callout.h> 56 #include <sys/device.h> 57 #include <sys/endian.h> 58 #include <sys/errno.h> 59 #include <sys/intr.h> 60 #include <sys/ioctl.h> 61 #include <sys/kernel.h> 62 #include <sys/mbuf.h> 63 #include <sys/malloc.h> 64 #include <sys/socket.h> 65 66 #include <uvm/uvm.h> /* for PAGE_SIZE */ 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #include <net/bpf.h> 74 #include <sys/rnd.h> 75 76 #include <dev/mii/mii.h> 77 #include <dev/mii/miivar.h> 78 79 #include <mips/alchemy/include/aureg.h> 80 #include <mips/alchemy/include/auvar.h> 81 #include <mips/alchemy/include/aubusvar.h> 82 #include <mips/alchemy/dev/if_aumacreg.h> 83 84 /* 85 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 86 * must consist of a single DMA segment, and must be aligned to a 2K 87 * boundary. Therefore, this driver does not perform DMA directly 88 * to/from mbufs. Instead, we copy the data to/from buffers allocated 89 * at device attach time. 90 * 91 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 92 * there's little point in not making assumptions based on the CPU type. 93 * We also program the Au1X00 cache to be DMA coherent, so the buffers 94 * are accessed via KSEG0 addresses. 95 */ 96 #define AUMAC_NTXDESC 4 97 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 98 99 #define AUMAC_NRXDESC 4 100 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 101 102 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 103 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 104 105 #define AUMAC_TXBUF_OFFSET 0 106 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 107 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 108 109 struct aumac_buf { 110 vaddr_t buf_vaddr; /* virtual address of buffer */ 111 bus_addr_t buf_paddr; /* DMA address of buffer */ 112 }; 113 114 /* 115 * Software state per device. 116 */ 117 struct aumac_softc { 118 device_t sc_dev; /* generic device information */ 119 bus_space_tag_t sc_st; /* bus space tag */ 120 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 121 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 122 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 123 struct ethercom sc_ethercom; /* Ethernet common data */ 124 void *sc_sdhook; /* shutdown hook */ 125 126 void *sc_ih; /* interrupt cookie */ 127 128 struct mii_data sc_mii; /* MII/media information */ 129 130 struct callout sc_tick_ch; /* tick callout */ 131 132 /* Transmit and receive buffers */ 133 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 134 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 135 void *sc_bufaddr; 136 137 int sc_txfree; /* number of free Tx descriptors */ 138 int sc_txnext; /* next Tx descriptor to use */ 139 int sc_txdirty; /* first dirty Tx descriptor */ 140 141 int sc_rxptr; /* next ready Rx descriptor */ 142 143 krndsource_t rnd_source; 144 145 #ifdef AUMAC_EVENT_COUNTERS 146 struct evcnt sc_ev_txstall; /* Tx stalled */ 147 struct evcnt sc_ev_rxstall; /* Rx stalled */ 148 struct evcnt sc_ev_txintr; /* Tx interrupts */ 149 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 150 #endif 151 152 uint32_t sc_control; /* MAC_CONTROL contents */ 153 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 154 }; 155 156 #ifdef AUMAC_EVENT_COUNTERS 157 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 158 #else 159 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 160 #endif 161 162 #define AUMAC_INIT_RXDESC(sc, x) \ 163 do { \ 164 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 165 MACDMA_RX_STAT((x)), 0); \ 166 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 167 MACDMA_RX_ADDR((x)), \ 168 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 169 } while (/*CONSTCOND*/0) 170 171 static void aumac_start(struct ifnet *); 172 static void aumac_watchdog(struct ifnet *); 173 static int aumac_ioctl(struct ifnet *, u_long, void *); 174 static int aumac_init(struct ifnet *); 175 static void aumac_stop(struct ifnet *, int); 176 177 static void aumac_shutdown(void *); 178 179 static void aumac_tick(void *); 180 181 static void aumac_set_filter(struct aumac_softc *); 182 183 static void aumac_powerup(struct aumac_softc *); 184 static void aumac_powerdown(struct aumac_softc *); 185 186 static int aumac_intr(void *); 187 static int aumac_txintr(struct aumac_softc *); 188 static int aumac_rxintr(struct aumac_softc *); 189 190 static int aumac_mii_readreg(device_t, int, int); 191 static void aumac_mii_writereg(device_t, int, int, int); 192 static void aumac_mii_statchg(device_t); 193 static int aumac_mii_wait(struct aumac_softc *, const char *); 194 195 static int aumac_match(device_t, struct cfdata *, void *); 196 static void aumac_attach(device_t, device_t, void *); 197 198 int aumac_copy_small = 0; 199 200 CFATTACH_DECL_NEW(aumac, sizeof(struct aumac_softc), 201 aumac_match, aumac_attach, NULL, NULL); 202 203 static int 204 aumac_match(device_t parent, struct cfdata *cf, void *aux) 205 { 206 struct aubus_attach_args *aa = aux; 207 208 if (strcmp(aa->aa_name, cf->cf_name) == 0) 209 return (1); 210 211 return (0); 212 } 213 214 static void 215 aumac_attach(device_t parent, device_t self, void *aux) 216 { 217 const uint8_t *enaddr; 218 prop_data_t ea; 219 struct aumac_softc *sc = device_private(self); 220 struct aubus_attach_args *aa = aux; 221 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 222 struct pglist pglist; 223 paddr_t bufaddr; 224 vaddr_t vbufaddr; 225 int i; 226 227 callout_init(&sc->sc_tick_ch, 0); 228 229 aprint_normal(": Au1X00 10/100 Ethernet\n"); 230 aprint_naive("\n"); 231 232 sc->sc_dev = self; 233 sc->sc_st = aa->aa_st; 234 235 /* Get the MAC address. */ 236 ea = prop_dictionary_get(device_properties(self), "mac-address"); 237 if (ea == NULL) { 238 aprint_error_dev(self, "unable to get mac-addr property\n"); 239 return; 240 } 241 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 242 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 243 enaddr = prop_data_data_nocopy(ea); 244 245 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(enaddr)); 246 247 /* Map the device. */ 248 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 249 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 250 aprint_error_dev(self, "unable to map MAC registers\n"); 251 return; 252 } 253 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 254 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 255 aprint_error_dev(self, "unable to map MACEN registers\n"); 256 return; 257 } 258 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 259 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 260 aprint_error_dev(self, "unable to map MACDMA registers\n"); 261 return; 262 } 263 264 /* Make sure the MAC is powered off. */ 265 aumac_powerdown(sc); 266 267 /* Hook up the interrupt handler. */ 268 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 269 aumac_intr, sc); 270 if (sc->sc_ih == NULL) { 271 aprint_error_dev(self, 272 "unable to register interrupt handler\n"); 273 return; 274 } 275 276 /* 277 * Allocate space for the transmit and receive buffers. 278 */ 279 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 280 &pglist, 1, 0)) 281 return; 282 283 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 284 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 285 286 for (i = 0; i < AUMAC_NTXDESC; i++) { 287 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 288 289 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 290 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 291 } 292 293 for (i = 0; i < AUMAC_NRXDESC; i++) { 294 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 295 296 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 297 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 298 } 299 300 /* 301 * Power up the MAC before accessing any MAC registers (including 302 * MII configuration. 303 */ 304 aumac_powerup(sc); 305 306 /* 307 * Initialize the media structures and probe the MII. 308 */ 309 sc->sc_mii.mii_ifp = ifp; 310 sc->sc_mii.mii_readreg = aumac_mii_readreg; 311 sc->sc_mii.mii_writereg = aumac_mii_writereg; 312 sc->sc_mii.mii_statchg = aumac_mii_statchg; 313 sc->sc_ethercom.ec_mii = &sc->sc_mii; 314 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 315 ether_mediastatus); 316 317 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 318 MII_OFFSET_ANY, 0); 319 320 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 321 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 322 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 323 } else 324 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 325 326 strcpy(ifp->if_xname, device_xname(self)); 327 ifp->if_softc = sc; 328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 329 ifp->if_ioctl = aumac_ioctl; 330 ifp->if_start = aumac_start; 331 ifp->if_watchdog = aumac_watchdog; 332 ifp->if_init = aumac_init; 333 ifp->if_stop = aumac_stop; 334 IFQ_SET_READY(&ifp->if_snd); 335 336 /* Attach the interface. */ 337 if_attach(ifp); 338 ether_ifattach(ifp, enaddr); 339 340 rnd_attach_source(&sc->rnd_source, device_xname(self), 341 RND_TYPE_NET, 0); 342 343 #ifdef AUMAC_EVENT_COUNTERS 344 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 345 NULL, device_xname(self), "txstall"); 346 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 347 NULL, device_xname(self), "rxstall"); 348 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 349 NULL, device_xname(self), "txintr"); 350 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 351 NULL, device_xname(self), "rxintr"); 352 #endif 353 354 /* Make sure the interface is shutdown during reboot. */ 355 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 356 if (sc->sc_sdhook == NULL) 357 aprint_error_dev(self, 358 "WARNING: unable to establish shutdown hook\n"); 359 return; 360 } 361 362 /* 363 * aumac_shutdown: 364 * 365 * Make sure the interface is stopped at reboot time. 366 */ 367 static void 368 aumac_shutdown(void *arg) 369 { 370 struct aumac_softc *sc = arg; 371 372 aumac_stop(&sc->sc_ethercom.ec_if, 1); 373 374 /* 375 * XXX aumac_stop leaves device powered up at the moment 376 * XXX but this still isn't enough to keep yamon happy... :-( 377 */ 378 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 379 } 380 381 /* 382 * aumac_start: [ifnet interface function] 383 * 384 * Start packet transmission on the interface. 385 */ 386 static void 387 aumac_start(struct ifnet *ifp) 388 { 389 struct aumac_softc *sc = ifp->if_softc; 390 struct mbuf *m; 391 int nexttx; 392 393 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 394 return; 395 396 /* 397 * Loop through the send queue, setting up transmit descriptors 398 * unitl we drain the queue, or use up all available transmit 399 * descriptors. 400 */ 401 for (;;) { 402 /* Grab a packet off the queue. */ 403 IFQ_POLL(&ifp->if_snd, m); 404 if (m == NULL) 405 return; 406 407 /* Get a spare descriptor. */ 408 if (sc->sc_txfree == 0) { 409 /* No more slots left; notify upper layer. */ 410 ifp->if_flags |= IFF_OACTIVE; 411 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 412 return; 413 } 414 nexttx = sc->sc_txnext; 415 416 IFQ_DEQUEUE(&ifp->if_snd, m); 417 418 /* 419 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 420 */ 421 422 m_copydata(m, 0, m->m_pkthdr.len, 423 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 424 425 /* Zero out the remainder of any short packets. */ 426 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 427 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 428 m->m_pkthdr.len, 0, 429 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 430 431 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 432 MACDMA_TX_STAT(nexttx), 0); 433 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 434 MACDMA_TX_LEN(nexttx), 435 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 436 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 437 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 438 MACDMA_TX_ADDR(nexttx), 439 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 440 /* XXX - needed?? we should be coherent */ 441 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 442 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 443 444 /* Advance the Tx pointer. */ 445 sc->sc_txfree--; 446 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 447 448 /* Pass the packet to any BPF listeners. */ 449 bpf_mtap(ifp, m); 450 451 m_freem(m); 452 453 /* Set a watchdog timer in case the chip flakes out. */ 454 ifp->if_timer = 5; 455 } 456 /* NOTREACHED */ 457 } 458 459 /* 460 * aumac_watchdog: [ifnet interface function] 461 * 462 * Watchdog timer handler. 463 */ 464 static void 465 aumac_watchdog(struct ifnet *ifp) 466 { 467 struct aumac_softc *sc = ifp->if_softc; 468 469 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 470 (void) aumac_init(ifp); 471 472 /* Try to get more packets going. */ 473 aumac_start(ifp); 474 } 475 476 /* 477 * aumac_ioctl: [ifnet interface function] 478 * 479 * Handle control requests from the operator. 480 */ 481 static int 482 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 483 { 484 struct aumac_softc *sc = ifp->if_softc; 485 int s, error; 486 487 s = splnet(); 488 489 error = ether_ioctl(ifp, cmd, data); 490 if (error == ENETRESET) { 491 /* 492 * Multicast list has changed; set the hardware filter 493 * accordingly. 494 */ 495 if (ifp->if_flags & IFF_RUNNING) 496 aumac_set_filter(sc); 497 } 498 499 /* Try to get more packets going. */ 500 aumac_start(ifp); 501 502 splx(s); 503 return (error); 504 } 505 506 /* 507 * aumac_intr: 508 * 509 * Interrupt service routine. 510 */ 511 static int 512 aumac_intr(void *arg) 513 { 514 struct aumac_softc *sc = arg; 515 int status; 516 517 /* 518 * There aren't really any interrupt status bits on the 519 * Au1X00 MAC, and each MAC has a dedicated interrupt 520 * in the CPU's built-in interrupt controller. Just 521 * check for new incoming packets, and then Tx completions 522 * (for status updating). 523 */ 524 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 525 return (0); 526 527 status = aumac_rxintr(sc); 528 status += aumac_txintr(sc); 529 530 rnd_add_uint32(&sc->rnd_source, status); 531 532 return status; 533 } 534 535 /* 536 * aumac_txintr: 537 * 538 * Helper; handle transmit interrupts. 539 */ 540 static int 541 aumac_txintr(struct aumac_softc *sc) 542 { 543 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 544 uint32_t stat; 545 int i; 546 int pkts = 0; 547 548 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 549 i = AUMAC_NEXTTX(i)) { 550 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 551 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 552 break; 553 pkts++; 554 555 /* ACK interrupt. */ 556 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 557 MACDMA_TX_ADDR(i), 0); 558 559 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 560 MACDMA_TX_STAT(i)); 561 562 if (stat & TX_STAT_FA) { 563 /* XXX STATS */ 564 ifp->if_oerrors++; 565 } else 566 ifp->if_opackets++; 567 568 if (stat & TX_STAT_EC) 569 ifp->if_collisions += 16; 570 else 571 ifp->if_collisions += TX_STAT_CC(stat); 572 573 sc->sc_txfree++; 574 ifp->if_flags &= ~IFF_OACTIVE; 575 576 /* Try to queue more packets. */ 577 aumac_start(ifp); 578 } 579 580 if (pkts) 581 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 582 583 /* Update the dirty descriptor pointer. */ 584 sc->sc_txdirty = i; 585 586 /* 587 * If there are no more pending transmissions, cancel the watchdog 588 * timer. 589 */ 590 if (sc->sc_txfree == AUMAC_NTXDESC) 591 ifp->if_timer = 0; 592 593 return pkts; 594 } 595 596 /* 597 * aumac_rxintr: 598 * 599 * Helper; handle receive interrupts. 600 */ 601 static int 602 aumac_rxintr(struct aumac_softc *sc) 603 { 604 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 605 struct mbuf *m; 606 uint32_t stat; 607 int i, len; 608 int pkts = 0; 609 610 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 611 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 612 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 613 break; 614 pkts++; 615 616 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 617 MACDMA_RX_STAT(i)); 618 619 #define PRINTERR(str) \ 620 do { \ 621 error++; \ 622 printf("%s: %s\n", device_xname(sc->sc_dev), str); \ 623 } while (0) 624 625 if (stat & RX_STAT_ERRS) { 626 int error = 0; 627 628 #if 0 /* 629 * Missed frames are a semi-frequent occurence with this hardware, 630 * and reporting of them just makes everything run slower and fills 631 * the system log. Be silent. 632 * 633 * Additionally, this missed bit indicates an error with the previous 634 * packet, and not with this one! So PRINTERR is definitely wrong 635 * here. 636 * 637 * These should probably all be converted to evcnt counters anyway. 638 */ 639 if (stat & RX_STAT_MI) 640 PRINTERR("missed frame"); 641 #endif 642 if (stat & RX_STAT_UC) 643 PRINTERR("unknown control frame"); 644 if (stat & RX_STAT_LE) 645 PRINTERR("short frame"); 646 if (stat & RX_STAT_CR) 647 PRINTERR("CRC error"); 648 if (stat & RX_STAT_ME) 649 PRINTERR("medium error"); 650 if (stat & RX_STAT_CS) 651 PRINTERR("late collision"); 652 if (stat & RX_STAT_FL) 653 PRINTERR("frame too big"); 654 if (stat & RX_STAT_RF) 655 PRINTERR("runt frame (collision)"); 656 if (stat & RX_STAT_WT) 657 PRINTERR("watch dog"); 658 if (stat & RX_STAT_DB) { 659 if (stat & (RX_STAT_CS | RX_STAT_RF | 660 RX_STAT_CR)) { 661 if (!error) 662 goto pktok; 663 } else 664 PRINTERR("dribbling bit"); 665 } 666 #undef PRINTERR 667 ifp->if_ierrors++; 668 669 dropit: 670 /* reuse the current descriptor */ 671 AUMAC_INIT_RXDESC(sc, i); 672 continue; 673 } 674 pktok: 675 len = RX_STAT_L(stat); 676 677 /* 678 * The Au1X00 MAC includes the CRC with every packet; 679 * trim it off here. 680 */ 681 len -= ETHER_CRC_LEN; 682 683 /* 684 * Truncate the packet if it's too big to fit in 685 * a single mbuf cluster. 686 */ 687 if (len > MCLBYTES - 2) 688 len = MCLBYTES - 2; 689 690 MGETHDR(m, M_DONTWAIT, MT_DATA); 691 if (m == NULL) { 692 printf("%s: unable to allocate Rx mbuf\n", 693 device_xname(sc->sc_dev)); 694 goto dropit; 695 } 696 if (len > MHLEN - 2) { 697 MCLGET(m, M_DONTWAIT); 698 if ((m->m_flags & M_EXT) == 0) { 699 printf("%s: unable to allocate Rx cluster\n", 700 device_xname(sc->sc_dev)); 701 m_freem(m); 702 goto dropit; 703 } 704 } 705 706 m->m_data += 2; /* align payload */ 707 memcpy(mtod(m, void *), 708 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 709 AUMAC_INIT_RXDESC(sc, i); 710 711 m->m_pkthdr.rcvif = ifp; 712 m->m_pkthdr.len = m->m_len = len; 713 714 /* Pass this up to any BPF listeners. */ 715 bpf_mtap(ifp, m); 716 717 /* Pass it on. */ 718 (*ifp->if_input)(ifp, m); 719 ifp->if_ipackets++; 720 } 721 if (pkts) 722 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 723 if (pkts == AUMAC_NRXDESC) 724 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 725 726 /* Update the receive pointer. */ 727 sc->sc_rxptr = i; 728 729 return pkts; 730 } 731 732 /* 733 * aumac_tick: 734 * 735 * One second timer, used to tick the MII. 736 */ 737 static void 738 aumac_tick(void *arg) 739 { 740 struct aumac_softc *sc = arg; 741 int s; 742 743 s = splnet(); 744 mii_tick(&sc->sc_mii); 745 splx(s); 746 747 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 748 } 749 750 /* 751 * aumac_init: [ifnet interface function] 752 * 753 * Initialize the interface. Must be called at splnet(). 754 */ 755 static int 756 aumac_init(struct ifnet *ifp) 757 { 758 struct aumac_softc *sc = ifp->if_softc; 759 int i, error = 0; 760 761 /* Cancel any pending I/O, reset MAC. */ 762 aumac_stop(ifp, 0); 763 764 /* Set up the transmit ring. */ 765 for (i = 0; i < AUMAC_NTXDESC; i++) { 766 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 767 MACDMA_TX_STAT(i), 0); 768 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 769 MACDMA_TX_LEN(i), 0); 770 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 771 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 772 } 773 sc->sc_txfree = AUMAC_NTXDESC; 774 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 775 MACDMA_TX_ADDR(0))); 776 sc->sc_txdirty = sc->sc_txnext; 777 778 /* Set up the receive ring. */ 779 for (i = 0; i < AUMAC_NRXDESC; i++) 780 AUMAC_INIT_RXDESC(sc, i); 781 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 782 MACDMA_RX_ADDR(0))); 783 784 /* 785 * Power up the MAC. 786 */ 787 aumac_powerup(sc); 788 789 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 790 #if _BYTE_ORDER == _BIG_ENDIAN 791 sc->sc_control |= CONTROL_EM; 792 #endif 793 794 /* Set the media. */ 795 if ((error = ether_mediachange(ifp)) != 0) 796 goto out; 797 798 /* 799 * Set the receive filter. This will actually start the transmit 800 * and receive processes. 801 */ 802 aumac_set_filter(sc); 803 804 /* Start the one second clock. */ 805 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 806 807 /* ...all done! */ 808 ifp->if_flags |= IFF_RUNNING; 809 ifp->if_flags &= ~IFF_OACTIVE; 810 811 out: 812 if (error) 813 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 814 return (error); 815 } 816 817 /* 818 * aumac_stop: [ifnet interface function] 819 * 820 * Stop transmission on the interface. 821 */ 822 static void 823 aumac_stop(struct ifnet *ifp, int disable) 824 { 825 struct aumac_softc *sc = ifp->if_softc; 826 827 /* Stop the one-second clock. */ 828 callout_stop(&sc->sc_tick_ch); 829 830 /* Down the MII. */ 831 mii_down(&sc->sc_mii); 832 833 /* Stop the transmit and receive processes. */ 834 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 835 836 /* Power down/reset the MAC. */ 837 aumac_powerdown(sc); 838 839 /* Mark the interface as down and cancel the watchdog timer. */ 840 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 841 ifp->if_timer = 0; 842 } 843 844 /* 845 * aumac_powerdown: 846 * 847 * Power down the MAC. 848 */ 849 static void 850 aumac_powerdown(struct aumac_softc *sc) 851 { 852 853 /* Disable the MAC clocks, and place the device in reset. */ 854 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 855 856 // delay(10000); 857 } 858 859 /* 860 * aumac_powerup: 861 * 862 * Bring the device out of reset. 863 */ 864 static void 865 aumac_powerup(struct aumac_softc *sc) 866 { 867 868 /* Enable clocks to the MAC. */ 869 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 870 871 /* Enable MAC, coherent transactions, pass only valid frames. */ 872 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 873 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 874 875 delay(20000); 876 } 877 878 /* 879 * aumac_set_filter: 880 * 881 * Set up the receive filter. 882 */ 883 static void 884 aumac_set_filter(struct aumac_softc *sc) 885 { 886 struct ethercom *ec = &sc->sc_ethercom; 887 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 888 struct ether_multi *enm; 889 struct ether_multistep step; 890 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 891 uint32_t mchash[2], crc; 892 893 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 894 895 /* Stop the receiver. */ 896 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 897 sc->sc_control & ~CONTROL_RE); 898 899 if (ifp->if_flags & IFF_PROMISC) { 900 sc->sc_control |= CONTROL_PR; 901 goto allmulti; 902 } 903 904 /* Set the station address. */ 905 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 906 enaddr[4] | (enaddr[5] << 8)); 907 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 908 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 909 (enaddr[3] << 24)); 910 911 sc->sc_control |= CONTROL_HP; 912 913 mchash[0] = mchash[1] = 0; 914 915 /* 916 * Set up the multicast address filter by passing all multicast 917 * addresses through a CRC generator, and then using the high 918 * order 6 bits as an index into the 64-bit multicast hash table. 919 * The high order bits select the word, while the rest of the bits 920 * select the bit within the word. 921 */ 922 ETHER_FIRST_MULTI(step, ec, enm); 923 while (enm != NULL) { 924 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 925 /* 926 * We must listen to a range of multicast addresses. 927 * For now, just accept all multicasts, rather than 928 * trying to set only those filter bits needed to match 929 * the range. (At this time, the only use of address 930 * ranges is for IP multicast routing, for which the 931 * range is large enough to require all bits set.) 932 */ 933 goto allmulti; 934 } 935 936 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 937 938 /* Just want the 6 most significant bits. */ 939 crc >>= 26; 940 941 /* Set the corresponding bit in the filter. */ 942 mchash[crc >> 5] |= 1U << (crc & 0x1f); 943 944 ETHER_NEXT_MULTI(step, enm); 945 } 946 947 ifp->if_flags &= ~IFF_ALLMULTI; 948 949 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 950 mchash[1]); 951 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 952 mchash[0]); 953 954 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 955 sc->sc_control); 956 return; 957 958 allmulti: 959 sc->sc_control |= CONTROL_PM; 960 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 961 sc->sc_control); 962 } 963 964 /* 965 * aumac_mii_wait: 966 * 967 * Wait for the MII interface to not be busy. 968 */ 969 static int 970 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 971 { 972 int i; 973 974 for (i = 0; i < 10000; i++) { 975 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 976 MAC_MIICTRL) & MIICTRL_MB) == 0) 977 return (0); 978 delay(10); 979 } 980 981 printf("%s: MII failed to %s\n", device_xname(sc->sc_dev), msg); 982 return (1); 983 } 984 985 /* 986 * aumac_mii_readreg: [mii interface function] 987 * 988 * Read a PHY register on the MII. 989 */ 990 static int 991 aumac_mii_readreg(device_t self, int phy, int reg) 992 { 993 struct aumac_softc *sc = device_private(self); 994 995 if (aumac_mii_wait(sc, "become ready")) 996 return (0); 997 998 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 999 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1000 1001 if (aumac_mii_wait(sc, "complete")) 1002 return (0); 1003 1004 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1005 MIIDATA_MASK); 1006 } 1007 1008 /* 1009 * aumac_mii_writereg: [mii interface function] 1010 * 1011 * Write a PHY register on the MII. 1012 */ 1013 static void 1014 aumac_mii_writereg(device_t self, int phy, int reg, int val) 1015 { 1016 struct aumac_softc *sc = device_private(self); 1017 1018 if (aumac_mii_wait(sc, "become ready")) 1019 return; 1020 1021 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1022 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1023 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1024 1025 (void) aumac_mii_wait(sc, "complete"); 1026 } 1027 1028 /* 1029 * aumac_mii_statchg: [mii interface function] 1030 * 1031 * Callback from MII layer when media changes. 1032 */ 1033 static void 1034 aumac_mii_statchg(device_t self) 1035 { 1036 struct aumac_softc *sc = device_private(self); 1037 1038 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1039 sc->sc_control |= CONTROL_F; 1040 else 1041 sc->sc_control &= ~CONTROL_F; 1042 1043 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1044 sc->sc_control); 1045 } 1046