1 /* $NetBSD: if_aumac.c,v 1.28 2010/04/05 07:19:30 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.28 2010/04/05 07:19:30 joerg Exp $"); 50 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/queue.h> 64 65 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #include <net/bpf.h> 73 #if NRND > 0 74 #include <sys/rnd.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 #include <machine/endian.h> 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <mips/alchemy/include/aureg.h> 85 #include <mips/alchemy/include/auvar.h> 86 #include <mips/alchemy/include/aubusvar.h> 87 #include <mips/alchemy/dev/if_aumacreg.h> 88 89 /* 90 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 91 * must consist of a single DMA segment, and must be aligned to a 2K 92 * boundary. Therefore, this driver does not perform DMA directly 93 * to/from mbufs. Instead, we copy the data to/from buffers allocated 94 * at device attach time. 95 * 96 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 97 * there's little point in not making assumptions based on the CPU type. 98 * We also program the Au1X00 cache to be DMA coherent, so the buffers 99 * are accessed via KSEG0 addresses. 100 */ 101 #define AUMAC_NTXDESC 4 102 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 103 104 #define AUMAC_NRXDESC 4 105 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 106 107 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 108 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 109 110 #define AUMAC_TXBUF_OFFSET 0 111 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 112 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 113 114 struct aumac_buf { 115 vaddr_t buf_vaddr; /* virtual address of buffer */ 116 bus_addr_t buf_paddr; /* DMA address of buffer */ 117 }; 118 119 /* 120 * Software state per device. 121 */ 122 struct aumac_softc { 123 struct device sc_dev; /* generic device information */ 124 bus_space_tag_t sc_st; /* bus space tag */ 125 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 126 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 127 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 128 struct ethercom sc_ethercom; /* Ethernet common data */ 129 void *sc_sdhook; /* shutdown hook */ 130 131 void *sc_ih; /* interrupt cookie */ 132 133 struct mii_data sc_mii; /* MII/media information */ 134 135 struct callout sc_tick_ch; /* tick callout */ 136 137 /* Transmit and receive buffers */ 138 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 139 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 140 void *sc_bufaddr; 141 142 int sc_txfree; /* number of free Tx descriptors */ 143 int sc_txnext; /* next Tx descriptor to use */ 144 int sc_txdirty; /* first dirty Tx descriptor */ 145 146 int sc_rxptr; /* next ready Rx descriptor */ 147 148 #if NRND > 0 149 rndsource_element_t rnd_source; 150 #endif 151 152 #ifdef AUMAC_EVENT_COUNTERS 153 struct evcnt sc_ev_txstall; /* Tx stalled */ 154 struct evcnt sc_ev_rxstall; /* Rx stalled */ 155 struct evcnt sc_ev_txintr; /* Tx interrupts */ 156 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 157 #endif 158 159 uint32_t sc_control; /* MAC_CONTROL contents */ 160 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 161 }; 162 163 #ifdef AUMAC_EVENT_COUNTERS 164 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 165 #else 166 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 167 #endif 168 169 #define AUMAC_INIT_RXDESC(sc, x) \ 170 do { \ 171 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 172 MACDMA_RX_STAT((x)), 0); \ 173 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 174 MACDMA_RX_ADDR((x)), \ 175 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 176 } while (/*CONSTCOND*/0) 177 178 static void aumac_start(struct ifnet *); 179 static void aumac_watchdog(struct ifnet *); 180 static int aumac_ioctl(struct ifnet *, u_long, void *); 181 static int aumac_init(struct ifnet *); 182 static void aumac_stop(struct ifnet *, int); 183 184 static void aumac_shutdown(void *); 185 186 static void aumac_tick(void *); 187 188 static void aumac_set_filter(struct aumac_softc *); 189 190 static void aumac_powerup(struct aumac_softc *); 191 static void aumac_powerdown(struct aumac_softc *); 192 193 static int aumac_intr(void *); 194 static int aumac_txintr(struct aumac_softc *); 195 static int aumac_rxintr(struct aumac_softc *); 196 197 static int aumac_mii_readreg(struct device *, int, int); 198 static void aumac_mii_writereg(struct device *, int, int, int); 199 static void aumac_mii_statchg(struct device *); 200 static int aumac_mii_wait(struct aumac_softc *, const char *); 201 202 static int aumac_match(struct device *, struct cfdata *, void *); 203 static void aumac_attach(struct device *, struct device *, void *); 204 205 int aumac_copy_small = 0; 206 207 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 208 aumac_match, aumac_attach, NULL, NULL); 209 210 static int 211 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 212 { 213 struct aubus_attach_args *aa = aux; 214 215 if (strcmp(aa->aa_name, cf->cf_name) == 0) 216 return (1); 217 218 return (0); 219 } 220 221 static void 222 aumac_attach(struct device *parent, struct device *self, void *aux) 223 { 224 const uint8_t *enaddr; 225 prop_data_t ea; 226 struct aumac_softc *sc = (void *) self; 227 struct aubus_attach_args *aa = aux; 228 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 229 struct pglist pglist; 230 paddr_t bufaddr; 231 vaddr_t vbufaddr; 232 int i; 233 234 callout_init(&sc->sc_tick_ch, 0); 235 236 printf(": Au1X00 10/100 Ethernet\n"); 237 238 sc->sc_st = aa->aa_st; 239 240 /* Get the MAC address. */ 241 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-address"); 242 if (ea == NULL) { 243 printf("%s: unable to get mac-addr property\n", 244 sc->sc_dev.dv_xname); 245 return; 246 } 247 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 248 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 249 enaddr = prop_data_data_nocopy(ea); 250 251 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 252 ether_sprintf(enaddr)); 253 254 /* Map the device. */ 255 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 256 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 257 printf("%s: unable to map MAC registers\n", 258 sc->sc_dev.dv_xname); 259 return; 260 } 261 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 262 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 263 printf("%s: unable to map MACEN registers\n", 264 sc->sc_dev.dv_xname); 265 return; 266 } 267 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 268 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 269 printf("%s: unable to map MACDMA registers\n", 270 sc->sc_dev.dv_xname); 271 return; 272 } 273 274 /* Make sure the MAC is powered off. */ 275 aumac_powerdown(sc); 276 277 /* Hook up the interrupt handler. */ 278 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 279 aumac_intr, sc); 280 if (sc->sc_ih == NULL) { 281 printf("%s: unable to register interrupt handler\n", 282 sc->sc_dev.dv_xname); 283 return; 284 } 285 286 /* 287 * Allocate space for the transmit and receive buffers. 288 */ 289 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 290 &pglist, 1, 0)) 291 return; 292 293 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 294 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 295 296 for (i = 0; i < AUMAC_NTXDESC; i++) { 297 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 298 299 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 300 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 301 } 302 303 for (i = 0; i < AUMAC_NRXDESC; i++) { 304 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 305 306 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 307 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 308 } 309 310 /* 311 * Power up the MAC before accessing any MAC registers (including 312 * MII configuration. 313 */ 314 aumac_powerup(sc); 315 316 /* 317 * Initialize the media structures and probe the MII. 318 */ 319 sc->sc_mii.mii_ifp = ifp; 320 sc->sc_mii.mii_readreg = aumac_mii_readreg; 321 sc->sc_mii.mii_writereg = aumac_mii_writereg; 322 sc->sc_mii.mii_statchg = aumac_mii_statchg; 323 sc->sc_ethercom.ec_mii = &sc->sc_mii; 324 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 325 ether_mediastatus); 326 327 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 328 MII_OFFSET_ANY, 0); 329 330 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 331 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 332 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 333 } else 334 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 335 336 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 337 ifp->if_softc = sc; 338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 339 ifp->if_ioctl = aumac_ioctl; 340 ifp->if_start = aumac_start; 341 ifp->if_watchdog = aumac_watchdog; 342 ifp->if_init = aumac_init; 343 ifp->if_stop = aumac_stop; 344 IFQ_SET_READY(&ifp->if_snd); 345 346 /* Attach the interface. */ 347 if_attach(ifp); 348 ether_ifattach(ifp, enaddr); 349 350 #if NRND > 0 351 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 352 RND_TYPE_NET, 0); 353 #endif 354 355 #ifdef AUMAC_EVENT_COUNTERS 356 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 357 NULL, sc->sc_dev.dv_xname, "txstall"); 358 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 359 NULL, sc->sc_dev.dv_xname, "rxstall"); 360 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 361 NULL, sc->sc_dev.dv_xname, "txintr"); 362 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 363 NULL, sc->sc_dev.dv_xname, "rxintr"); 364 #endif 365 366 /* Make sure the interface is shutdown during reboot. */ 367 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 368 if (sc->sc_sdhook == NULL) 369 printf("%s: WARNING: unable to establish shutdown hook\n", 370 sc->sc_dev.dv_xname); 371 return; 372 } 373 374 /* 375 * aumac_shutdown: 376 * 377 * Make sure the interface is stopped at reboot time. 378 */ 379 static void 380 aumac_shutdown(void *arg) 381 { 382 struct aumac_softc *sc = arg; 383 384 aumac_stop(&sc->sc_ethercom.ec_if, 1); 385 386 /* 387 * XXX aumac_stop leaves device powered up at the moment 388 * XXX but this still isn't enough to keep yamon happy... :-( 389 */ 390 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 391 } 392 393 /* 394 * aumac_start: [ifnet interface function] 395 * 396 * Start packet transmission on the interface. 397 */ 398 static void 399 aumac_start(struct ifnet *ifp) 400 { 401 struct aumac_softc *sc = ifp->if_softc; 402 struct mbuf *m; 403 int nexttx; 404 405 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 406 return; 407 408 /* 409 * Loop through the send queue, setting up transmit descriptors 410 * unitl we drain the queue, or use up all available transmit 411 * descriptors. 412 */ 413 for (;;) { 414 /* Grab a packet off the queue. */ 415 IFQ_POLL(&ifp->if_snd, m); 416 if (m == NULL) 417 return; 418 419 /* Get a spare descriptor. */ 420 if (sc->sc_txfree == 0) { 421 /* No more slots left; notify upper layer. */ 422 ifp->if_flags |= IFF_OACTIVE; 423 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 424 return; 425 } 426 nexttx = sc->sc_txnext; 427 428 IFQ_DEQUEUE(&ifp->if_snd, m); 429 430 /* 431 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 432 */ 433 434 m_copydata(m, 0, m->m_pkthdr.len, 435 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 436 437 /* Zero out the remainder of any short packets. */ 438 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 439 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 440 m->m_pkthdr.len, 0, 441 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 442 443 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 444 MACDMA_TX_STAT(nexttx), 0); 445 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 446 MACDMA_TX_LEN(nexttx), 447 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 448 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 449 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 450 MACDMA_TX_ADDR(nexttx), 451 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 452 /* XXX - needed?? we should be coherent */ 453 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 454 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 455 456 /* Advance the Tx pointer. */ 457 sc->sc_txfree--; 458 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 459 460 /* Pass the packet to any BPF listeners. */ 461 bpf_mtap(ifp, m); 462 463 m_freem(m); 464 465 /* Set a watchdog timer in case the chip flakes out. */ 466 ifp->if_timer = 5; 467 } 468 /* NOTREACHED */ 469 } 470 471 /* 472 * aumac_watchdog: [ifnet interface function] 473 * 474 * Watchdog timer handler. 475 */ 476 static void 477 aumac_watchdog(struct ifnet *ifp) 478 { 479 struct aumac_softc *sc = ifp->if_softc; 480 481 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 482 (void) aumac_init(ifp); 483 484 /* Try to get more packets going. */ 485 aumac_start(ifp); 486 } 487 488 /* 489 * aumac_ioctl: [ifnet interface function] 490 * 491 * Handle control requests from the operator. 492 */ 493 static int 494 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 495 { 496 struct aumac_softc *sc = ifp->if_softc; 497 int s, error; 498 499 s = splnet(); 500 501 error = ether_ioctl(ifp, cmd, data); 502 if (error == ENETRESET) { 503 /* 504 * Multicast list has changed; set the hardware filter 505 * accordingly. 506 */ 507 if (ifp->if_flags & IFF_RUNNING) 508 aumac_set_filter(sc); 509 } 510 511 /* Try to get more packets going. */ 512 aumac_start(ifp); 513 514 splx(s); 515 return (error); 516 } 517 518 /* 519 * aumac_intr: 520 * 521 * Interrupt service routine. 522 */ 523 static int 524 aumac_intr(void *arg) 525 { 526 struct aumac_softc *sc = arg; 527 int status; 528 529 /* 530 * There aren't really any interrupt status bits on the 531 * Au1X00 MAC, and each MAC has a dedicated interrupt 532 * in the CPU's built-in interrupt controller. Just 533 * check for new incoming packets, and then Tx completions 534 * (for status updating). 535 */ 536 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 537 return (0); 538 539 status = aumac_rxintr(sc); 540 status += aumac_txintr(sc); 541 542 #if NRND > 0 543 if (RND_ENABLED(&sc->rnd_source)) 544 rnd_add_uint32(&sc->rnd_source, status); 545 #endif 546 547 return status; 548 } 549 550 /* 551 * aumac_txintr: 552 * 553 * Helper; handle transmit interrupts. 554 */ 555 static int 556 aumac_txintr(struct aumac_softc *sc) 557 { 558 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 559 uint32_t stat; 560 int i; 561 int pkts = 0; 562 563 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 564 i = AUMAC_NEXTTX(i)) { 565 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 566 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 567 break; 568 pkts++; 569 570 /* ACK interrupt. */ 571 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 572 MACDMA_TX_ADDR(i), 0); 573 574 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 575 MACDMA_TX_STAT(i)); 576 577 if (stat & TX_STAT_FA) { 578 /* XXX STATS */ 579 ifp->if_oerrors++; 580 } else 581 ifp->if_opackets++; 582 583 if (stat & TX_STAT_EC) 584 ifp->if_collisions += 16; 585 else 586 ifp->if_collisions += TX_STAT_CC(stat); 587 588 sc->sc_txfree++; 589 ifp->if_flags &= ~IFF_OACTIVE; 590 591 /* Try to queue more packets. */ 592 aumac_start(ifp); 593 } 594 595 if (pkts) 596 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 597 598 /* Update the dirty descriptor pointer. */ 599 sc->sc_txdirty = i; 600 601 /* 602 * If there are no more pending transmissions, cancel the watchdog 603 * timer. 604 */ 605 if (sc->sc_txfree == AUMAC_NTXDESC) 606 ifp->if_timer = 0; 607 608 return pkts; 609 } 610 611 /* 612 * aumac_rxintr: 613 * 614 * Helper; handle receive interrupts. 615 */ 616 static int 617 aumac_rxintr(struct aumac_softc *sc) 618 { 619 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 620 struct mbuf *m; 621 uint32_t stat; 622 int i, len; 623 int pkts = 0; 624 625 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 626 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 627 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 628 break; 629 pkts++; 630 631 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 632 MACDMA_RX_STAT(i)); 633 634 #define PRINTERR(str) \ 635 do { \ 636 error++; \ 637 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 638 } while (0) 639 640 if (stat & RX_STAT_ERRS) { 641 int error = 0; 642 643 #if 0 /* 644 * Missed frames are a semi-frequent occurence with this hardware, 645 * and reporting of them just makes everything run slower and fills 646 * the system log. Be silent. 647 * 648 * Additionally, this missed bit indicates an error with the previous 649 * packet, and not with this one! So PRINTERR is definitely wrong 650 * here. 651 * 652 * These should probably all be converted to evcnt counters anyway. 653 */ 654 if (stat & RX_STAT_MI) 655 PRINTERR("missed frame"); 656 #endif 657 if (stat & RX_STAT_UC) 658 PRINTERR("unknown control frame"); 659 if (stat & RX_STAT_LE) 660 PRINTERR("short frame"); 661 if (stat & RX_STAT_CR) 662 PRINTERR("CRC error"); 663 if (stat & RX_STAT_ME) 664 PRINTERR("medium error"); 665 if (stat & RX_STAT_CS) 666 PRINTERR("late collision"); 667 if (stat & RX_STAT_FL) 668 PRINTERR("frame too big"); 669 if (stat & RX_STAT_RF) 670 PRINTERR("runt frame (collision)"); 671 if (stat & RX_STAT_WT) 672 PRINTERR("watch dog"); 673 if (stat & RX_STAT_DB) { 674 if (stat & (RX_STAT_CS | RX_STAT_RF | 675 RX_STAT_CR)) { 676 if (!error) 677 goto pktok; 678 } else 679 PRINTERR("dribbling bit"); 680 } 681 #undef PRINTERR 682 ifp->if_ierrors++; 683 684 dropit: 685 /* reuse the current descriptor */ 686 AUMAC_INIT_RXDESC(sc, i); 687 continue; 688 } 689 pktok: 690 len = RX_STAT_L(stat); 691 692 /* 693 * The Au1X00 MAC includes the CRC with every packet; 694 * trim it off here. 695 */ 696 len -= ETHER_CRC_LEN; 697 698 /* 699 * Truncate the packet if it's too big to fit in 700 * a single mbuf cluster. 701 */ 702 if (len > MCLBYTES - 2) 703 len = MCLBYTES - 2; 704 705 MGETHDR(m, M_DONTWAIT, MT_DATA); 706 if (m == NULL) { 707 printf("%s: unable to allocate Rx mbuf\n", 708 sc->sc_dev.dv_xname); 709 goto dropit; 710 } 711 if (len > MHLEN - 2) { 712 MCLGET(m, M_DONTWAIT); 713 if ((m->m_flags & M_EXT) == 0) { 714 printf("%s: unable to allocate Rx cluster\n", 715 sc->sc_dev.dv_xname); 716 m_freem(m); 717 goto dropit; 718 } 719 } 720 721 m->m_data += 2; /* align payload */ 722 memcpy(mtod(m, void *), 723 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 724 AUMAC_INIT_RXDESC(sc, i); 725 726 m->m_pkthdr.rcvif = ifp; 727 m->m_pkthdr.len = m->m_len = len; 728 729 /* Pass this up to any BPF listeners. */ 730 bpf_mtap(ifp, m); 731 732 /* Pass it on. */ 733 (*ifp->if_input)(ifp, m); 734 ifp->if_ipackets++; 735 } 736 if (pkts) 737 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 738 if (pkts == AUMAC_NRXDESC) 739 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 740 741 /* Update the receive pointer. */ 742 sc->sc_rxptr = i; 743 744 return pkts; 745 } 746 747 /* 748 * aumac_tick: 749 * 750 * One second timer, used to tick the MII. 751 */ 752 static void 753 aumac_tick(void *arg) 754 { 755 struct aumac_softc *sc = arg; 756 int s; 757 758 s = splnet(); 759 mii_tick(&sc->sc_mii); 760 splx(s); 761 762 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 763 } 764 765 /* 766 * aumac_init: [ifnet interface function] 767 * 768 * Initialize the interface. Must be called at splnet(). 769 */ 770 static int 771 aumac_init(struct ifnet *ifp) 772 { 773 struct aumac_softc *sc = ifp->if_softc; 774 int i, error = 0; 775 776 /* Cancel any pending I/O, reset MAC. */ 777 aumac_stop(ifp, 0); 778 779 /* Set up the transmit ring. */ 780 for (i = 0; i < AUMAC_NTXDESC; i++) { 781 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 782 MACDMA_TX_STAT(i), 0); 783 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 784 MACDMA_TX_LEN(i), 0); 785 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 786 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 787 } 788 sc->sc_txfree = AUMAC_NTXDESC; 789 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 790 MACDMA_TX_ADDR(0))); 791 sc->sc_txdirty = sc->sc_txnext; 792 793 /* Set up the receive ring. */ 794 for (i = 0; i < AUMAC_NRXDESC; i++) 795 AUMAC_INIT_RXDESC(sc, i); 796 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 797 MACDMA_RX_ADDR(0))); 798 799 /* 800 * Power up the MAC. 801 */ 802 aumac_powerup(sc); 803 804 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 805 #if _BYTE_ORDER == _BIG_ENDIAN 806 sc->sc_control |= CONTROL_EM; 807 #endif 808 809 /* Set the media. */ 810 if ((error = ether_mediachange(ifp)) != 0) 811 goto out; 812 813 /* 814 * Set the receive filter. This will actually start the transmit 815 * and receive processes. 816 */ 817 aumac_set_filter(sc); 818 819 /* Start the one second clock. */ 820 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 821 822 /* ...all done! */ 823 ifp->if_flags |= IFF_RUNNING; 824 ifp->if_flags &= ~IFF_OACTIVE; 825 826 out: 827 if (error) 828 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 829 return (error); 830 } 831 832 /* 833 * aumac_stop: [ifnet interface function] 834 * 835 * Stop transmission on the interface. 836 */ 837 static void 838 aumac_stop(struct ifnet *ifp, int disable) 839 { 840 struct aumac_softc *sc = ifp->if_softc; 841 842 /* Stop the one-second clock. */ 843 callout_stop(&sc->sc_tick_ch); 844 845 /* Down the MII. */ 846 mii_down(&sc->sc_mii); 847 848 /* Stop the transmit and receive processes. */ 849 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 850 851 /* Power down/reset the MAC. */ 852 aumac_powerdown(sc); 853 854 /* Mark the interface as down and cancel the watchdog timer. */ 855 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 856 ifp->if_timer = 0; 857 } 858 859 /* 860 * aumac_powerdown: 861 * 862 * Power down the MAC. 863 */ 864 static void 865 aumac_powerdown(struct aumac_softc *sc) 866 { 867 868 /* Disable the MAC clocks, and place the device in reset. */ 869 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 870 871 // delay(10000); 872 } 873 874 /* 875 * aumac_powerup: 876 * 877 * Bring the device out of reset. 878 */ 879 static void 880 aumac_powerup(struct aumac_softc *sc) 881 { 882 883 /* Enable clocks to the MAC. */ 884 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 885 886 /* Enable MAC, coherent transactions, pass only valid frames. */ 887 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 888 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 889 890 delay(20000); 891 } 892 893 /* 894 * aumac_set_filter: 895 * 896 * Set up the receive filter. 897 */ 898 static void 899 aumac_set_filter(struct aumac_softc *sc) 900 { 901 struct ethercom *ec = &sc->sc_ethercom; 902 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 903 struct ether_multi *enm; 904 struct ether_multistep step; 905 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 906 uint32_t mchash[2], crc; 907 908 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 909 910 /* Stop the receiver. */ 911 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 912 sc->sc_control & ~CONTROL_RE); 913 914 if (ifp->if_flags & IFF_PROMISC) { 915 sc->sc_control |= CONTROL_PR; 916 goto allmulti; 917 } 918 919 /* Set the station address. */ 920 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 921 enaddr[4] | (enaddr[5] << 8)); 922 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 923 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 924 (enaddr[3] << 24)); 925 926 sc->sc_control |= CONTROL_HP; 927 928 mchash[0] = mchash[1] = 0; 929 930 /* 931 * Set up the multicast address filter by passing all multicast 932 * addresses through a CRC generator, and then using the high 933 * order 6 bits as an index into the 64-bit multicast hash table. 934 * The high order bits select the word, while the rest of the bits 935 * select the bit within the word. 936 */ 937 ETHER_FIRST_MULTI(step, ec, enm); 938 while (enm != NULL) { 939 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 940 /* 941 * We must listen to a range of multicast addresses. 942 * For now, just accept all multicasts, rather than 943 * trying to set only those filter bits needed to match 944 * the range. (At this time, the only use of address 945 * ranges is for IP multicast routing, for which the 946 * range is large enough to require all bits set.) 947 */ 948 goto allmulti; 949 } 950 951 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 952 953 /* Just want the 6 most significant bits. */ 954 crc >>= 26; 955 956 /* Set the corresponding bit in the filter. */ 957 mchash[crc >> 5] |= 1U << (crc & 0x1f); 958 959 ETHER_NEXT_MULTI(step, enm); 960 } 961 962 ifp->if_flags &= ~IFF_ALLMULTI; 963 964 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 965 mchash[1]); 966 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 967 mchash[0]); 968 969 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 970 sc->sc_control); 971 return; 972 973 allmulti: 974 sc->sc_control |= CONTROL_PM; 975 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 976 sc->sc_control); 977 } 978 979 /* 980 * aumac_mii_wait: 981 * 982 * Wait for the MII interface to not be busy. 983 */ 984 static int 985 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 986 { 987 int i; 988 989 for (i = 0; i < 10000; i++) { 990 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 991 MAC_MIICTRL) & MIICTRL_MB) == 0) 992 return (0); 993 delay(10); 994 } 995 996 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 997 return (1); 998 } 999 1000 /* 1001 * aumac_mii_readreg: [mii interface function] 1002 * 1003 * Read a PHY register on the MII. 1004 */ 1005 static int 1006 aumac_mii_readreg(struct device *self, int phy, int reg) 1007 { 1008 struct aumac_softc *sc = (void *) self; 1009 1010 if (aumac_mii_wait(sc, "become ready")) 1011 return (0); 1012 1013 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1014 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1015 1016 if (aumac_mii_wait(sc, "complete")) 1017 return (0); 1018 1019 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1020 MIIDATA_MASK); 1021 } 1022 1023 /* 1024 * aumac_mii_writereg: [mii interface function] 1025 * 1026 * Write a PHY register on the MII. 1027 */ 1028 static void 1029 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1030 { 1031 struct aumac_softc *sc = (void *) self; 1032 1033 if (aumac_mii_wait(sc, "become ready")) 1034 return; 1035 1036 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1037 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1038 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1039 1040 (void) aumac_mii_wait(sc, "complete"); 1041 } 1042 1043 /* 1044 * aumac_mii_statchg: [mii interface function] 1045 * 1046 * Callback from MII layer when media changes. 1047 */ 1048 static void 1049 aumac_mii_statchg(struct device *self) 1050 { 1051 struct aumac_softc *sc = (void *) self; 1052 1053 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1054 sc->sc_control |= CONTROL_F; 1055 else 1056 sc->sc_control &= ~CONTROL_F; 1057 1058 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1059 sc->sc_control); 1060 } 1061