1 /* $NetBSD: if_aumac.c,v 1.27 2010/01/22 08:56:05 martin Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.27 2010/01/22 08:56:05 martin Exp $"); 50 51 #include "rnd.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/queue.h> 64 65 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #include <net/bpf.h> 73 #if NRND > 0 74 #include <sys/rnd.h> 75 #endif 76 77 #include <machine/bus.h> 78 #include <machine/intr.h> 79 #include <machine/endian.h> 80 81 #include <dev/mii/mii.h> 82 #include <dev/mii/miivar.h> 83 84 #include <mips/alchemy/include/aureg.h> 85 #include <mips/alchemy/include/auvar.h> 86 #include <mips/alchemy/include/aubusvar.h> 87 #include <mips/alchemy/dev/if_aumacreg.h> 88 89 /* 90 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 91 * must consist of a single DMA segment, and must be aligned to a 2K 92 * boundary. Therefore, this driver does not perform DMA directly 93 * to/from mbufs. Instead, we copy the data to/from buffers allocated 94 * at device attach time. 95 * 96 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 97 * there's little point in not making assumptions based on the CPU type. 98 * We also program the Au1X00 cache to be DMA coherent, so the buffers 99 * are accessed via KSEG0 addresses. 100 */ 101 #define AUMAC_NTXDESC 4 102 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 103 104 #define AUMAC_NRXDESC 4 105 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 106 107 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 108 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 109 110 #define AUMAC_TXBUF_OFFSET 0 111 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 112 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 113 114 struct aumac_buf { 115 vaddr_t buf_vaddr; /* virtual address of buffer */ 116 bus_addr_t buf_paddr; /* DMA address of buffer */ 117 }; 118 119 /* 120 * Software state per device. 121 */ 122 struct aumac_softc { 123 struct device sc_dev; /* generic device information */ 124 bus_space_tag_t sc_st; /* bus space tag */ 125 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 126 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 127 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 128 struct ethercom sc_ethercom; /* Ethernet common data */ 129 void *sc_sdhook; /* shutdown hook */ 130 131 void *sc_ih; /* interrupt cookie */ 132 133 struct mii_data sc_mii; /* MII/media information */ 134 135 struct callout sc_tick_ch; /* tick callout */ 136 137 /* Transmit and receive buffers */ 138 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 139 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 140 void *sc_bufaddr; 141 142 int sc_txfree; /* number of free Tx descriptors */ 143 int sc_txnext; /* next Tx descriptor to use */ 144 int sc_txdirty; /* first dirty Tx descriptor */ 145 146 int sc_rxptr; /* next ready Rx descriptor */ 147 148 #if NRND > 0 149 rndsource_element_t rnd_source; 150 #endif 151 152 #ifdef AUMAC_EVENT_COUNTERS 153 struct evcnt sc_ev_txstall; /* Tx stalled */ 154 struct evcnt sc_ev_rxstall; /* Rx stalled */ 155 struct evcnt sc_ev_txintr; /* Tx interrupts */ 156 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 157 #endif 158 159 uint32_t sc_control; /* MAC_CONTROL contents */ 160 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 161 }; 162 163 #ifdef AUMAC_EVENT_COUNTERS 164 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 165 #else 166 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 167 #endif 168 169 #define AUMAC_INIT_RXDESC(sc, x) \ 170 do { \ 171 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 172 MACDMA_RX_STAT((x)), 0); \ 173 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 174 MACDMA_RX_ADDR((x)), \ 175 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 176 } while (/*CONSTCOND*/0) 177 178 static void aumac_start(struct ifnet *); 179 static void aumac_watchdog(struct ifnet *); 180 static int aumac_ioctl(struct ifnet *, u_long, void *); 181 static int aumac_init(struct ifnet *); 182 static void aumac_stop(struct ifnet *, int); 183 184 static void aumac_shutdown(void *); 185 186 static void aumac_tick(void *); 187 188 static void aumac_set_filter(struct aumac_softc *); 189 190 static void aumac_powerup(struct aumac_softc *); 191 static void aumac_powerdown(struct aumac_softc *); 192 193 static int aumac_intr(void *); 194 static int aumac_txintr(struct aumac_softc *); 195 static int aumac_rxintr(struct aumac_softc *); 196 197 static int aumac_mii_readreg(struct device *, int, int); 198 static void aumac_mii_writereg(struct device *, int, int, int); 199 static void aumac_mii_statchg(struct device *); 200 static int aumac_mii_wait(struct aumac_softc *, const char *); 201 202 static int aumac_match(struct device *, struct cfdata *, void *); 203 static void aumac_attach(struct device *, struct device *, void *); 204 205 int aumac_copy_small = 0; 206 207 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 208 aumac_match, aumac_attach, NULL, NULL); 209 210 static int 211 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 212 { 213 struct aubus_attach_args *aa = aux; 214 215 if (strcmp(aa->aa_name, cf->cf_name) == 0) 216 return (1); 217 218 return (0); 219 } 220 221 static void 222 aumac_attach(struct device *parent, struct device *self, void *aux) 223 { 224 const uint8_t *enaddr; 225 prop_data_t ea; 226 struct aumac_softc *sc = (void *) self; 227 struct aubus_attach_args *aa = aux; 228 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 229 struct pglist pglist; 230 paddr_t bufaddr; 231 vaddr_t vbufaddr; 232 int i; 233 234 callout_init(&sc->sc_tick_ch, 0); 235 236 printf(": Au1X00 10/100 Ethernet\n"); 237 238 sc->sc_st = aa->aa_st; 239 240 /* Get the MAC address. */ 241 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-address"); 242 if (ea == NULL) { 243 printf("%s: unable to get mac-addr property\n", 244 sc->sc_dev.dv_xname); 245 return; 246 } 247 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 248 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 249 enaddr = prop_data_data_nocopy(ea); 250 251 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 252 ether_sprintf(enaddr)); 253 254 /* Map the device. */ 255 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 256 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 257 printf("%s: unable to map MAC registers\n", 258 sc->sc_dev.dv_xname); 259 return; 260 } 261 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 262 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 263 printf("%s: unable to map MACEN registers\n", 264 sc->sc_dev.dv_xname); 265 return; 266 } 267 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 268 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 269 printf("%s: unable to map MACDMA registers\n", 270 sc->sc_dev.dv_xname); 271 return; 272 } 273 274 /* Make sure the MAC is powered off. */ 275 aumac_powerdown(sc); 276 277 /* Hook up the interrupt handler. */ 278 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 279 aumac_intr, sc); 280 if (sc->sc_ih == NULL) { 281 printf("%s: unable to register interrupt handler\n", 282 sc->sc_dev.dv_xname); 283 return; 284 } 285 286 /* 287 * Allocate space for the transmit and receive buffers. 288 */ 289 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 290 &pglist, 1, 0)) 291 return; 292 293 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 294 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 295 296 for (i = 0; i < AUMAC_NTXDESC; i++) { 297 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 298 299 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 300 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 301 } 302 303 for (i = 0; i < AUMAC_NRXDESC; i++) { 304 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 305 306 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 307 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 308 } 309 310 /* 311 * Power up the MAC before accessing any MAC registers (including 312 * MII configuration. 313 */ 314 aumac_powerup(sc); 315 316 /* 317 * Initialize the media structures and probe the MII. 318 */ 319 sc->sc_mii.mii_ifp = ifp; 320 sc->sc_mii.mii_readreg = aumac_mii_readreg; 321 sc->sc_mii.mii_writereg = aumac_mii_writereg; 322 sc->sc_mii.mii_statchg = aumac_mii_statchg; 323 sc->sc_ethercom.ec_mii = &sc->sc_mii; 324 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 325 ether_mediastatus); 326 327 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 328 MII_OFFSET_ANY, 0); 329 330 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 331 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 332 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 333 } else 334 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 335 336 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 337 ifp->if_softc = sc; 338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 339 ifp->if_ioctl = aumac_ioctl; 340 ifp->if_start = aumac_start; 341 ifp->if_watchdog = aumac_watchdog; 342 ifp->if_init = aumac_init; 343 ifp->if_stop = aumac_stop; 344 IFQ_SET_READY(&ifp->if_snd); 345 346 /* Attach the interface. */ 347 if_attach(ifp); 348 ether_ifattach(ifp, enaddr); 349 350 #if NRND > 0 351 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 352 RND_TYPE_NET, 0); 353 #endif 354 355 #ifdef AUMAC_EVENT_COUNTERS 356 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 357 NULL, sc->sc_dev.dv_xname, "txstall"); 358 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 359 NULL, sc->sc_dev.dv_xname, "rxstall"); 360 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 361 NULL, sc->sc_dev.dv_xname, "txintr"); 362 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 363 NULL, sc->sc_dev.dv_xname, "rxintr"); 364 #endif 365 366 /* Make sure the interface is shutdown during reboot. */ 367 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 368 if (sc->sc_sdhook == NULL) 369 printf("%s: WARNING: unable to establish shutdown hook\n", 370 sc->sc_dev.dv_xname); 371 return; 372 } 373 374 /* 375 * aumac_shutdown: 376 * 377 * Make sure the interface is stopped at reboot time. 378 */ 379 static void 380 aumac_shutdown(void *arg) 381 { 382 struct aumac_softc *sc = arg; 383 384 aumac_stop(&sc->sc_ethercom.ec_if, 1); 385 386 /* 387 * XXX aumac_stop leaves device powered up at the moment 388 * XXX but this still isn't enough to keep yamon happy... :-( 389 */ 390 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 391 } 392 393 /* 394 * aumac_start: [ifnet interface function] 395 * 396 * Start packet transmission on the interface. 397 */ 398 static void 399 aumac_start(struct ifnet *ifp) 400 { 401 struct aumac_softc *sc = ifp->if_softc; 402 struct mbuf *m; 403 int nexttx; 404 405 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 406 return; 407 408 /* 409 * Loop through the send queue, setting up transmit descriptors 410 * unitl we drain the queue, or use up all available transmit 411 * descriptors. 412 */ 413 for (;;) { 414 /* Grab a packet off the queue. */ 415 IFQ_POLL(&ifp->if_snd, m); 416 if (m == NULL) 417 return; 418 419 /* Get a spare descriptor. */ 420 if (sc->sc_txfree == 0) { 421 /* No more slots left; notify upper layer. */ 422 ifp->if_flags |= IFF_OACTIVE; 423 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 424 return; 425 } 426 nexttx = sc->sc_txnext; 427 428 IFQ_DEQUEUE(&ifp->if_snd, m); 429 430 /* 431 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 432 */ 433 434 m_copydata(m, 0, m->m_pkthdr.len, 435 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 436 437 /* Zero out the remainder of any short packets. */ 438 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 439 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 440 m->m_pkthdr.len, 0, 441 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 442 443 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 444 MACDMA_TX_STAT(nexttx), 0); 445 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 446 MACDMA_TX_LEN(nexttx), 447 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 448 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 449 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 450 MACDMA_TX_ADDR(nexttx), 451 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 452 /* XXX - needed?? we should be coherent */ 453 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 454 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 455 456 /* Advance the Tx pointer. */ 457 sc->sc_txfree--; 458 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 459 460 /* Pass the packet to any BPF listeners. */ 461 if (ifp->if_bpf) 462 bpf_ops->bpf_mtap(ifp->if_bpf, m); 463 464 m_freem(m); 465 466 /* Set a watchdog timer in case the chip flakes out. */ 467 ifp->if_timer = 5; 468 } 469 /* NOTREACHED */ 470 } 471 472 /* 473 * aumac_watchdog: [ifnet interface function] 474 * 475 * Watchdog timer handler. 476 */ 477 static void 478 aumac_watchdog(struct ifnet *ifp) 479 { 480 struct aumac_softc *sc = ifp->if_softc; 481 482 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 483 (void) aumac_init(ifp); 484 485 /* Try to get more packets going. */ 486 aumac_start(ifp); 487 } 488 489 /* 490 * aumac_ioctl: [ifnet interface function] 491 * 492 * Handle control requests from the operator. 493 */ 494 static int 495 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 496 { 497 struct aumac_softc *sc = ifp->if_softc; 498 int s, error; 499 500 s = splnet(); 501 502 error = ether_ioctl(ifp, cmd, data); 503 if (error == ENETRESET) { 504 /* 505 * Multicast list has changed; set the hardware filter 506 * accordingly. 507 */ 508 if (ifp->if_flags & IFF_RUNNING) 509 aumac_set_filter(sc); 510 } 511 512 /* Try to get more packets going. */ 513 aumac_start(ifp); 514 515 splx(s); 516 return (error); 517 } 518 519 /* 520 * aumac_intr: 521 * 522 * Interrupt service routine. 523 */ 524 static int 525 aumac_intr(void *arg) 526 { 527 struct aumac_softc *sc = arg; 528 int status; 529 530 /* 531 * There aren't really any interrupt status bits on the 532 * Au1X00 MAC, and each MAC has a dedicated interrupt 533 * in the CPU's built-in interrupt controller. Just 534 * check for new incoming packets, and then Tx completions 535 * (for status updating). 536 */ 537 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 538 return (0); 539 540 status = aumac_rxintr(sc); 541 status += aumac_txintr(sc); 542 543 #if NRND > 0 544 if (RND_ENABLED(&sc->rnd_source)) 545 rnd_add_uint32(&sc->rnd_source, status); 546 #endif 547 548 return status; 549 } 550 551 /* 552 * aumac_txintr: 553 * 554 * Helper; handle transmit interrupts. 555 */ 556 static int 557 aumac_txintr(struct aumac_softc *sc) 558 { 559 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 560 uint32_t stat; 561 int i; 562 int pkts = 0; 563 564 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 565 i = AUMAC_NEXTTX(i)) { 566 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 567 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 568 break; 569 pkts++; 570 571 /* ACK interrupt. */ 572 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 573 MACDMA_TX_ADDR(i), 0); 574 575 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 576 MACDMA_TX_STAT(i)); 577 578 if (stat & TX_STAT_FA) { 579 /* XXX STATS */ 580 ifp->if_oerrors++; 581 } else 582 ifp->if_opackets++; 583 584 if (stat & TX_STAT_EC) 585 ifp->if_collisions += 16; 586 else 587 ifp->if_collisions += TX_STAT_CC(stat); 588 589 sc->sc_txfree++; 590 ifp->if_flags &= ~IFF_OACTIVE; 591 592 /* Try to queue more packets. */ 593 aumac_start(ifp); 594 } 595 596 if (pkts) 597 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 598 599 /* Update the dirty descriptor pointer. */ 600 sc->sc_txdirty = i; 601 602 /* 603 * If there are no more pending transmissions, cancel the watchdog 604 * timer. 605 */ 606 if (sc->sc_txfree == AUMAC_NTXDESC) 607 ifp->if_timer = 0; 608 609 return pkts; 610 } 611 612 /* 613 * aumac_rxintr: 614 * 615 * Helper; handle receive interrupts. 616 */ 617 static int 618 aumac_rxintr(struct aumac_softc *sc) 619 { 620 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 621 struct mbuf *m; 622 uint32_t stat; 623 int i, len; 624 int pkts = 0; 625 626 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 627 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 628 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 629 break; 630 pkts++; 631 632 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 633 MACDMA_RX_STAT(i)); 634 635 #define PRINTERR(str) \ 636 do { \ 637 error++; \ 638 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 639 } while (0) 640 641 if (stat & RX_STAT_ERRS) { 642 int error = 0; 643 644 #if 0 /* 645 * Missed frames are a semi-frequent occurence with this hardware, 646 * and reporting of them just makes everything run slower and fills 647 * the system log. Be silent. 648 * 649 * Additionally, this missed bit indicates an error with the previous 650 * packet, and not with this one! So PRINTERR is definitely wrong 651 * here. 652 * 653 * These should probably all be converted to evcnt counters anyway. 654 */ 655 if (stat & RX_STAT_MI) 656 PRINTERR("missed frame"); 657 #endif 658 if (stat & RX_STAT_UC) 659 PRINTERR("unknown control frame"); 660 if (stat & RX_STAT_LE) 661 PRINTERR("short frame"); 662 if (stat & RX_STAT_CR) 663 PRINTERR("CRC error"); 664 if (stat & RX_STAT_ME) 665 PRINTERR("medium error"); 666 if (stat & RX_STAT_CS) 667 PRINTERR("late collision"); 668 if (stat & RX_STAT_FL) 669 PRINTERR("frame too big"); 670 if (stat & RX_STAT_RF) 671 PRINTERR("runt frame (collision)"); 672 if (stat & RX_STAT_WT) 673 PRINTERR("watch dog"); 674 if (stat & RX_STAT_DB) { 675 if (stat & (RX_STAT_CS | RX_STAT_RF | 676 RX_STAT_CR)) { 677 if (!error) 678 goto pktok; 679 } else 680 PRINTERR("dribbling bit"); 681 } 682 #undef PRINTERR 683 ifp->if_ierrors++; 684 685 dropit: 686 /* reuse the current descriptor */ 687 AUMAC_INIT_RXDESC(sc, i); 688 continue; 689 } 690 pktok: 691 len = RX_STAT_L(stat); 692 693 /* 694 * The Au1X00 MAC includes the CRC with every packet; 695 * trim it off here. 696 */ 697 len -= ETHER_CRC_LEN; 698 699 /* 700 * Truncate the packet if it's too big to fit in 701 * a single mbuf cluster. 702 */ 703 if (len > MCLBYTES - 2) 704 len = MCLBYTES - 2; 705 706 MGETHDR(m, M_DONTWAIT, MT_DATA); 707 if (m == NULL) { 708 printf("%s: unable to allocate Rx mbuf\n", 709 sc->sc_dev.dv_xname); 710 goto dropit; 711 } 712 if (len > MHLEN - 2) { 713 MCLGET(m, M_DONTWAIT); 714 if ((m->m_flags & M_EXT) == 0) { 715 printf("%s: unable to allocate Rx cluster\n", 716 sc->sc_dev.dv_xname); 717 m_freem(m); 718 goto dropit; 719 } 720 } 721 722 m->m_data += 2; /* align payload */ 723 memcpy(mtod(m, void *), 724 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 725 AUMAC_INIT_RXDESC(sc, i); 726 727 m->m_pkthdr.rcvif = ifp; 728 m->m_pkthdr.len = m->m_len = len; 729 730 /* Pass this up to any BPF listeners. */ 731 if (ifp->if_bpf) 732 bpf_ops->bpf_mtap(ifp->if_bpf, m); 733 734 /* Pass it on. */ 735 (*ifp->if_input)(ifp, m); 736 ifp->if_ipackets++; 737 } 738 if (pkts) 739 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 740 if (pkts == AUMAC_NRXDESC) 741 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 742 743 /* Update the receive pointer. */ 744 sc->sc_rxptr = i; 745 746 return pkts; 747 } 748 749 /* 750 * aumac_tick: 751 * 752 * One second timer, used to tick the MII. 753 */ 754 static void 755 aumac_tick(void *arg) 756 { 757 struct aumac_softc *sc = arg; 758 int s; 759 760 s = splnet(); 761 mii_tick(&sc->sc_mii); 762 splx(s); 763 764 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 765 } 766 767 /* 768 * aumac_init: [ifnet interface function] 769 * 770 * Initialize the interface. Must be called at splnet(). 771 */ 772 static int 773 aumac_init(struct ifnet *ifp) 774 { 775 struct aumac_softc *sc = ifp->if_softc; 776 int i, error = 0; 777 778 /* Cancel any pending I/O, reset MAC. */ 779 aumac_stop(ifp, 0); 780 781 /* Set up the transmit ring. */ 782 for (i = 0; i < AUMAC_NTXDESC; i++) { 783 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 784 MACDMA_TX_STAT(i), 0); 785 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 786 MACDMA_TX_LEN(i), 0); 787 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 788 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 789 } 790 sc->sc_txfree = AUMAC_NTXDESC; 791 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 792 MACDMA_TX_ADDR(0))); 793 sc->sc_txdirty = sc->sc_txnext; 794 795 /* Set up the receive ring. */ 796 for (i = 0; i < AUMAC_NRXDESC; i++) 797 AUMAC_INIT_RXDESC(sc, i); 798 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 799 MACDMA_RX_ADDR(0))); 800 801 /* 802 * Power up the MAC. 803 */ 804 aumac_powerup(sc); 805 806 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 807 #if _BYTE_ORDER == _BIG_ENDIAN 808 sc->sc_control |= CONTROL_EM; 809 #endif 810 811 /* Set the media. */ 812 if ((error = ether_mediachange(ifp)) != 0) 813 goto out; 814 815 /* 816 * Set the receive filter. This will actually start the transmit 817 * and receive processes. 818 */ 819 aumac_set_filter(sc); 820 821 /* Start the one second clock. */ 822 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 823 824 /* ...all done! */ 825 ifp->if_flags |= IFF_RUNNING; 826 ifp->if_flags &= ~IFF_OACTIVE; 827 828 out: 829 if (error) 830 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 831 return (error); 832 } 833 834 /* 835 * aumac_stop: [ifnet interface function] 836 * 837 * Stop transmission on the interface. 838 */ 839 static void 840 aumac_stop(struct ifnet *ifp, int disable) 841 { 842 struct aumac_softc *sc = ifp->if_softc; 843 844 /* Stop the one-second clock. */ 845 callout_stop(&sc->sc_tick_ch); 846 847 /* Down the MII. */ 848 mii_down(&sc->sc_mii); 849 850 /* Stop the transmit and receive processes. */ 851 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 852 853 /* Power down/reset the MAC. */ 854 aumac_powerdown(sc); 855 856 /* Mark the interface as down and cancel the watchdog timer. */ 857 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 858 ifp->if_timer = 0; 859 } 860 861 /* 862 * aumac_powerdown: 863 * 864 * Power down the MAC. 865 */ 866 static void 867 aumac_powerdown(struct aumac_softc *sc) 868 { 869 870 /* Disable the MAC clocks, and place the device in reset. */ 871 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 872 873 // delay(10000); 874 } 875 876 /* 877 * aumac_powerup: 878 * 879 * Bring the device out of reset. 880 */ 881 static void 882 aumac_powerup(struct aumac_softc *sc) 883 { 884 885 /* Enable clocks to the MAC. */ 886 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 887 888 /* Enable MAC, coherent transactions, pass only valid frames. */ 889 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 890 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 891 892 delay(20000); 893 } 894 895 /* 896 * aumac_set_filter: 897 * 898 * Set up the receive filter. 899 */ 900 static void 901 aumac_set_filter(struct aumac_softc *sc) 902 { 903 struct ethercom *ec = &sc->sc_ethercom; 904 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 905 struct ether_multi *enm; 906 struct ether_multistep step; 907 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 908 uint32_t mchash[2], crc; 909 910 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 911 912 /* Stop the receiver. */ 913 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 914 sc->sc_control & ~CONTROL_RE); 915 916 if (ifp->if_flags & IFF_PROMISC) { 917 sc->sc_control |= CONTROL_PR; 918 goto allmulti; 919 } 920 921 /* Set the station address. */ 922 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 923 enaddr[4] | (enaddr[5] << 8)); 924 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 925 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 926 (enaddr[3] << 24)); 927 928 sc->sc_control |= CONTROL_HP; 929 930 mchash[0] = mchash[1] = 0; 931 932 /* 933 * Set up the multicast address filter by passing all multicast 934 * addresses through a CRC generator, and then using the high 935 * order 6 bits as an index into the 64-bit multicast hash table. 936 * The high order bits select the word, while the rest of the bits 937 * select the bit within the word. 938 */ 939 ETHER_FIRST_MULTI(step, ec, enm); 940 while (enm != NULL) { 941 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 942 /* 943 * We must listen to a range of multicast addresses. 944 * For now, just accept all multicasts, rather than 945 * trying to set only those filter bits needed to match 946 * the range. (At this time, the only use of address 947 * ranges is for IP multicast routing, for which the 948 * range is large enough to require all bits set.) 949 */ 950 goto allmulti; 951 } 952 953 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 954 955 /* Just want the 6 most significant bits. */ 956 crc >>= 26; 957 958 /* Set the corresponding bit in the filter. */ 959 mchash[crc >> 5] |= 1U << (crc & 0x1f); 960 961 ETHER_NEXT_MULTI(step, enm); 962 } 963 964 ifp->if_flags &= ~IFF_ALLMULTI; 965 966 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 967 mchash[1]); 968 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 969 mchash[0]); 970 971 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 972 sc->sc_control); 973 return; 974 975 allmulti: 976 sc->sc_control |= CONTROL_PM; 977 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 978 sc->sc_control); 979 } 980 981 /* 982 * aumac_mii_wait: 983 * 984 * Wait for the MII interface to not be busy. 985 */ 986 static int 987 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 988 { 989 int i; 990 991 for (i = 0; i < 10000; i++) { 992 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 993 MAC_MIICTRL) & MIICTRL_MB) == 0) 994 return (0); 995 delay(10); 996 } 997 998 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 999 return (1); 1000 } 1001 1002 /* 1003 * aumac_mii_readreg: [mii interface function] 1004 * 1005 * Read a PHY register on the MII. 1006 */ 1007 static int 1008 aumac_mii_readreg(struct device *self, int phy, int reg) 1009 { 1010 struct aumac_softc *sc = (void *) self; 1011 1012 if (aumac_mii_wait(sc, "become ready")) 1013 return (0); 1014 1015 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1016 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1017 1018 if (aumac_mii_wait(sc, "complete")) 1019 return (0); 1020 1021 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1022 MIIDATA_MASK); 1023 } 1024 1025 /* 1026 * aumac_mii_writereg: [mii interface function] 1027 * 1028 * Write a PHY register on the MII. 1029 */ 1030 static void 1031 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1032 { 1033 struct aumac_softc *sc = (void *) self; 1034 1035 if (aumac_mii_wait(sc, "become ready")) 1036 return; 1037 1038 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1039 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1040 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1041 1042 (void) aumac_mii_wait(sc, "complete"); 1043 } 1044 1045 /* 1046 * aumac_mii_statchg: [mii interface function] 1047 * 1048 * Callback from MII layer when media changes. 1049 */ 1050 static void 1051 aumac_mii_statchg(struct device *self) 1052 { 1053 struct aumac_softc *sc = (void *) self; 1054 1055 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1056 sc->sc_control |= CONTROL_F; 1057 else 1058 sc->sc_control &= ~CONTROL_F; 1059 1060 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1061 sc->sc_control); 1062 } 1063