1 /* $NetBSD: if_aumac.c,v 1.11 2003/07/04 01:19:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.11 2003/07/04 01:19:58 thorpej Exp $"); 50 51 #include "bpfilter.h" 52 53 #include <sys/param.h> 54 #include <sys/systm.h> 55 #include <sys/callout.h> 56 #include <sys/mbuf.h> 57 #include <sys/malloc.h> 58 #include <sys/kernel.h> 59 #include <sys/socket.h> 60 #include <sys/ioctl.h> 61 #include <sys/errno.h> 62 #include <sys/device.h> 63 #include <sys/queue.h> 64 65 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_ether.h> 71 72 #if NBPFILTER > 0 73 #include <net/bpf.h> 74 #endif 75 76 #include <machine/bus.h> 77 #include <machine/intr.h> 78 #include <machine/endian.h> 79 80 #include <dev/mii/mii.h> 81 #include <dev/mii/miivar.h> 82 83 #include <mips/alchemy/include/aureg.h> 84 #include <mips/alchemy/include/auvar.h> 85 #include <mips/alchemy/include/aubusvar.h> 86 #include <mips/alchemy/dev/if_aumacreg.h> 87 88 /* 89 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 90 * must consist of a single DMA segment, and must be aligned to a 2K 91 * boundary. Therefore, this driver does not perform DMA directly 92 * to/from mbufs. Instead, we copy the data to/from buffers allocated 93 * at device attach time. 94 * 95 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 96 * there's little point in not making assumptions based on the CPU type. 97 * We also program the Au1X00 cache to be DMA coherent, so the buffers 98 * are accessed via KSEG0 addresses. 99 */ 100 #define AUMAC_NTXDESC 4 101 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 102 103 #define AUMAC_NRXDESC 4 104 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 105 106 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 107 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 108 109 #define AUMAC_TXBUF_OFFSET 0 110 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 111 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 112 113 struct aumac_buf { 114 caddr_t buf_vaddr; /* virtual address of buffer */ 115 bus_addr_t buf_paddr; /* DMA address of buffer */ 116 }; 117 118 /* 119 * Software state per device. 120 */ 121 struct aumac_softc { 122 struct device sc_dev; /* generic device information */ 123 bus_space_tag_t sc_st; /* bus space tag */ 124 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 125 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 126 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 127 struct ethercom sc_ethercom; /* Ethernet common data */ 128 void *sc_sdhook; /* shutdown hook */ 129 130 void *sc_ih; /* interrupt cookie */ 131 132 struct mii_data sc_mii; /* MII/media information */ 133 134 struct callout sc_tick_ch; /* tick callout */ 135 136 /* Transmit and receive buffers */ 137 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 138 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 139 caddr_t sc_bufaddr; 140 141 int sc_txfree; /* number of free Tx descriptors */ 142 int sc_txnext; /* next Tx descriptor to use */ 143 int sc_txdirty; /* first dirty Tx descriptor */ 144 145 int sc_rxptr; /* next ready Rx descriptor */ 146 147 #ifdef AUMAC_EVENT_COUNTERS 148 struct evcnt sc_ev_txstall; /* Tx stalled */ 149 struct evcnt sc_ev_rxstall; /* Rx stalled */ 150 struct evcnt sc_ev_txintr; /* Tx interrupts */ 151 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 152 #endif 153 154 uint32_t sc_control; /* MAC_CONTROL contents */ 155 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 156 }; 157 158 #ifdef AUMAC_EVENT_COUNTERS 159 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 160 #else 161 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 162 #endif 163 164 #define AUMAC_INIT_RXDESC(sc, x) \ 165 do { \ 166 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 167 MACDMA_RX_STAT((x)), 0); \ 168 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 169 MACDMA_RX_ADDR((x)), \ 170 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 171 } while (/*CONSTCOND*/0) 172 173 static void aumac_start(struct ifnet *); 174 static void aumac_watchdog(struct ifnet *); 175 static int aumac_ioctl(struct ifnet *, u_long, caddr_t); 176 static int aumac_init(struct ifnet *); 177 static void aumac_stop(struct ifnet *, int); 178 179 static void aumac_shutdown(void *); 180 181 static void aumac_tick(void *); 182 183 static void aumac_set_filter(struct aumac_softc *); 184 185 static void aumac_powerup(struct aumac_softc *); 186 static void aumac_powerdown(struct aumac_softc *); 187 188 static int aumac_intr(void *); 189 static void aumac_txintr(struct aumac_softc *); 190 static void aumac_rxintr(struct aumac_softc *); 191 192 static int aumac_mii_readreg(struct device *, int, int); 193 static void aumac_mii_writereg(struct device *, int, int, int); 194 static void aumac_mii_statchg(struct device *); 195 static int aumac_mii_wait(struct aumac_softc *, const char *); 196 197 static int aumac_mediachange(struct ifnet *); 198 static void aumac_mediastatus(struct ifnet *, struct ifmediareq *); 199 200 static int aumac_match(struct device *, struct cfdata *, void *); 201 static void aumac_attach(struct device *, struct device *, void *); 202 203 int aumac_copy_small = 0; 204 205 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 206 aumac_match, aumac_attach, NULL, NULL); 207 208 static int 209 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 210 { 211 struct aubus_attach_args *aa = aux; 212 213 if (strcmp(aa->aa_name, cf->cf_name) == 0) 214 return (1); 215 216 return (0); 217 } 218 219 static void 220 aumac_attach(struct device *parent, struct device *self, void *aux) 221 { 222 uint8_t enaddr[ETHER_ADDR_LEN]; 223 struct aumac_softc *sc = (void *) self; 224 struct aubus_attach_args *aa = aux; 225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 226 struct pglist pglist; 227 paddr_t bufaddr; 228 caddr_t vbufaddr; 229 int i; 230 231 callout_init(&sc->sc_tick_ch); 232 233 printf(": Au1X00 10/100 Ethernet\n"); 234 235 sc->sc_st = aa->aa_st; 236 237 /* Get the MAC address. */ 238 if (prop_get(dev_propdb, &sc->sc_dev, "mac-addr", enaddr, 239 sizeof(enaddr), NULL) != sizeof(enaddr)) { 240 printf("%s: unable to get mac-addr property\n", 241 sc->sc_dev.dv_xname); 242 return; 243 } 244 245 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 246 ether_sprintf(enaddr)); 247 248 /* Map the device. */ 249 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 250 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 251 printf("%s: unable to map MAC registers\n", 252 sc->sc_dev.dv_xname); 253 return; 254 } 255 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 256 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 257 printf("%s: unable to map MACEN registers\n", 258 sc->sc_dev.dv_xname); 259 return; 260 } 261 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 262 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 263 printf("%s: unable to map MACDMA registers\n", 264 sc->sc_dev.dv_xname); 265 return; 266 } 267 268 /* Make sure the MAC is powered off. */ 269 aumac_powerdown(sc); 270 271 /* Hook up the interrupt handler. */ 272 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 273 aumac_intr, sc); 274 if (sc->sc_ih == NULL) { 275 printf("%s: unable to register interrupt handler\n", 276 sc->sc_dev.dv_xname); 277 return; 278 } 279 280 /* 281 * Allocate space for the transmit and receive buffers. 282 */ 283 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 284 &pglist, 1, 0)) 285 return; 286 287 bufaddr = TAILQ_FIRST(&pglist)->phys_addr; 288 vbufaddr = (void *)MIPS_PHYS_TO_KSEG0(bufaddr); 289 290 for (i = 0; i < AUMAC_NTXDESC; i++) { 291 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 292 293 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 294 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 295 } 296 297 for (i = 0; i < AUMAC_NRXDESC; i++) { 298 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 299 300 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 301 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 302 } 303 304 /* 305 * Power up the MAC before accessing any MAC registers (including 306 * MII configuration. 307 */ 308 aumac_powerup(sc); 309 310 /* 311 * Initialize the media structures and probe the MII. 312 */ 313 sc->sc_mii.mii_ifp = ifp; 314 sc->sc_mii.mii_readreg = aumac_mii_readreg; 315 sc->sc_mii.mii_writereg = aumac_mii_writereg; 316 sc->sc_mii.mii_statchg = aumac_mii_statchg; 317 ifmedia_init(&sc->sc_mii.mii_media, 0, aumac_mediachange, 318 aumac_mediastatus); 319 320 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 321 MII_OFFSET_ANY, 0); 322 323 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 324 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 325 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 326 } else 327 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 328 329 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 330 ifp->if_softc = sc; 331 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 332 ifp->if_ioctl = aumac_ioctl; 333 ifp->if_start = aumac_start; 334 ifp->if_watchdog = aumac_watchdog; 335 ifp->if_init = aumac_init; 336 ifp->if_stop = aumac_stop; 337 IFQ_SET_READY(&ifp->if_snd); 338 339 /* Attach the interface. */ 340 if_attach(ifp); 341 ether_ifattach(ifp, enaddr); 342 343 #ifdef AUMAC_EVENT_COUNTERS 344 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 345 NULL, sc->sc_dev.dv_xname, "txstall"); 346 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 347 NULL, sc->sc_dev.dv_xname, "rxstall"); 348 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 349 NULL, sc->sc_dev.dv_xname, "txintr"); 350 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 351 NULL, sc->sc_dev.dv_xname, "rxintr"); 352 #endif 353 354 /* Make sure the interface is shutdown during reboot. */ 355 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 356 if (sc->sc_sdhook == NULL) 357 printf("%s: WARNING: unable to establish shutdown hook\n", 358 sc->sc_dev.dv_xname); 359 return; 360 } 361 362 /* 363 * aumac_shutdown: 364 * 365 * Make sure the interface is stopped at reboot time. 366 */ 367 static void 368 aumac_shutdown(void *arg) 369 { 370 struct aumac_softc *sc = arg; 371 372 aumac_stop(&sc->sc_ethercom.ec_if, 1); 373 374 /* 375 * XXX aumac_stop leaves device powered up at the moment 376 * XXX but this still isn't enough to keep yamon happy... :-( 377 */ 378 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 379 } 380 381 /* 382 * aumac_start: [ifnet interface function] 383 * 384 * Start packet transmission on the interface. 385 */ 386 static void 387 aumac_start(struct ifnet *ifp) 388 { 389 struct aumac_softc *sc = ifp->if_softc; 390 struct mbuf *m; 391 int nexttx; 392 393 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 394 return; 395 396 /* 397 * Loop through the send queue, setting up transmit descriptors 398 * unitl we drain the queue, or use up all available transmit 399 * descriptors. 400 */ 401 for (;;) { 402 /* Grab a packet off the queue. */ 403 IFQ_POLL(&ifp->if_snd, m); 404 if (m == NULL) 405 return; 406 407 /* Get a spare descriptor. */ 408 if (sc->sc_txfree == 0) { 409 /* No more slots left; notify upper layer. */ 410 ifp->if_flags |= IFF_OACTIVE; 411 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 412 return; 413 } 414 nexttx = sc->sc_txnext; 415 416 IFQ_DEQUEUE(&ifp->if_snd, m); 417 418 /* 419 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 420 */ 421 422 m_copydata(m, 0, m->m_pkthdr.len, 423 sc->sc_txbufs[nexttx].buf_vaddr); 424 425 /* Zero out the remainder of any short packets. */ 426 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 427 memset(sc->sc_txbufs[nexttx].buf_vaddr + 428 m->m_pkthdr.len, 0, 429 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 430 431 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 432 MACDMA_TX_STAT(nexttx), 0); 433 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 434 MACDMA_TX_LEN(nexttx), 435 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 436 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 437 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 438 MACDMA_TX_ADDR(nexttx), 439 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 440 /* XXX - needed?? we should be coherent */ 441 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 442 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 443 444 /* Advance the Tx pointer. */ 445 sc->sc_txfree--; 446 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 447 448 #if NBPFILTER > 0 449 /* Pass the packet to any BPF listeners. */ 450 if (ifp->if_bpf) 451 bpf_mtap(ifp->if_bpf, m); 452 #endif /* NBPFILTER */ 453 454 m_freem(m); 455 456 /* Set a watchdog timer in case the chip flakes out. */ 457 ifp->if_timer = 5; 458 } 459 /* NOTREACHED */ 460 } 461 462 /* 463 * aumac_watchdog: [ifnet interface function] 464 * 465 * Watchdog timer handler. 466 */ 467 static void 468 aumac_watchdog(struct ifnet *ifp) 469 { 470 struct aumac_softc *sc = ifp->if_softc; 471 472 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 473 (void) aumac_init(ifp); 474 475 /* Try to get more packets going. */ 476 aumac_start(ifp); 477 } 478 479 /* 480 * aumac_ioctl: [ifnet interface function] 481 * 482 * Handle control requests from the operator. 483 */ 484 static int 485 aumac_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 486 { 487 struct aumac_softc *sc = ifp->if_softc; 488 struct ifreq *ifr = (struct ifreq *) data; 489 int s, error; 490 491 s = splnet(); 492 493 switch (cmd) { 494 case SIOCSIFMEDIA: 495 case SIOCGIFMEDIA: 496 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 497 break; 498 499 default: 500 error = ether_ioctl(ifp, cmd, data); 501 if (error == ENETRESET) { 502 /* 503 * Multicast list has changed; set the hardware filter 504 * accordingly. 505 */ 506 aumac_set_filter(sc); 507 } 508 break; 509 } 510 511 /* Try to get more packets going. */ 512 aumac_start(ifp); 513 514 splx(s); 515 return (error); 516 } 517 518 /* 519 * aumac_intr: 520 * 521 * Interrupt service routine. 522 */ 523 static int 524 aumac_intr(void *arg) 525 { 526 struct aumac_softc *sc = arg; 527 528 /* 529 * There aren't really any interrupt status bits on the 530 * Au1X00 MAC, and each MAC has a dedicated interrupt 531 * in the CPU's built-in interrupt controller. Just 532 * check for new incoming packets, and then Tx completions 533 * (for status updating). 534 */ 535 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 536 return (0); 537 538 aumac_rxintr(sc); 539 aumac_txintr(sc); 540 541 return (1); 542 } 543 544 /* 545 * aumac_txintr: 546 * 547 * Helper; handle transmit interrupts. 548 */ 549 static void 550 aumac_txintr(struct aumac_softc *sc) 551 { 552 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 553 uint32_t stat; 554 int i; 555 #ifdef AUMAC_EVENT_COUNTERS 556 int gotone = 0; 557 #endif 558 559 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 560 i = AUMAC_NEXTTX(i)) { 561 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 562 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 563 break; 564 #ifdef AUMAC_EVENT_COUNTERS 565 gotone = 1; 566 #endif 567 568 /* ACK interrupt. */ 569 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 570 MACDMA_TX_ADDR(i), 0); 571 572 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 573 MACDMA_TX_STAT(i)); 574 575 if (stat & TX_STAT_FA) { 576 /* XXX STATS */ 577 ifp->if_oerrors++; 578 } else 579 ifp->if_opackets++; 580 581 if (stat & TX_STAT_EC) 582 ifp->if_collisions += 16; 583 else 584 ifp->if_collisions += TX_STAT_CC(stat); 585 586 sc->sc_txfree++; 587 ifp->if_flags &= ~IFF_OACTIVE; 588 589 /* Try to queue more packets. */ 590 aumac_start(ifp); 591 } 592 593 if (gotone) 594 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 595 596 /* Update the dirty descriptor pointer. */ 597 sc->sc_txdirty = i; 598 599 /* 600 * If there are no more pending transmissions, cancel the watchdog 601 * timer. 602 */ 603 if (sc->sc_txfree == AUMAC_NTXDESC) 604 ifp->if_timer = 0; 605 } 606 607 /* 608 * aumac_rxintr: 609 * 610 * Helper; handle receive interrupts. 611 */ 612 static void 613 aumac_rxintr(struct aumac_softc *sc) 614 { 615 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 616 struct mbuf *m; 617 uint32_t stat; 618 int i, len; 619 #ifdef AUMAC_EVENT_COUNTERS 620 int pkts = 0; 621 #endif 622 623 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 624 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 625 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 626 break; 627 #ifdef AUMAC_EVENT_COUNTERS 628 pkts++; 629 #endif 630 631 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 632 MACDMA_RX_STAT(i)); 633 634 #define PRINTERR(str) \ 635 do { \ 636 error++; \ 637 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 638 } while (0) 639 640 if (stat & RX_STAT_ERRS) { 641 int error = 0; 642 643 if (stat & RX_STAT_MI) 644 PRINTERR("missed frame"); 645 if (stat & RX_STAT_UC) 646 PRINTERR("unknown control frame"); 647 if (stat & RX_STAT_LE) 648 PRINTERR("short frame"); 649 if (stat & RX_STAT_CR) 650 PRINTERR("CRC error"); 651 if (stat & RX_STAT_ME) 652 PRINTERR("medium error"); 653 if (stat & RX_STAT_CS) 654 PRINTERR("late collision"); 655 if (stat & RX_STAT_FL) 656 PRINTERR("frame too big"); 657 if (stat & RX_STAT_RF) 658 PRINTERR("runt frame (collision)"); 659 if (stat & RX_STAT_WT) 660 PRINTERR("watch dog"); 661 if (stat & RX_STAT_DB) { 662 if (stat & (RX_STAT_CS | RX_STAT_RF | 663 RX_STAT_CR)) { 664 if (!error) 665 goto pktok; 666 } else 667 PRINTERR("dribbling bit"); 668 } 669 #undef PRINTERR 670 ifp->if_ierrors++; 671 672 dropit: 673 /* reuse the current descriptor */ 674 AUMAC_INIT_RXDESC(sc, i); 675 continue; 676 } 677 pktok: 678 len = RX_STAT_L(stat); 679 680 /* 681 * The Au1X00 MAC includes the CRC with every packet; 682 * trim it off here. 683 */ 684 len -= ETHER_CRC_LEN; 685 686 /* 687 * Truncate the packet if it's too big to fit in 688 * a single mbuf cluster. 689 */ 690 if (len > MCLBYTES - 2) 691 len = MCLBYTES - 2; 692 693 MGETHDR(m, M_DONTWAIT, MT_DATA); 694 if (m == NULL) { 695 printf("%s: unable to allocate Rx mbuf\n", 696 sc->sc_dev.dv_xname); 697 goto dropit; 698 } 699 if (len > MHLEN - 2) { 700 MCLGET(m, M_DONTWAIT); 701 if ((m->m_flags & M_EXT) == 0) { 702 printf("%s: unable to allocate Rx cluster\n", 703 sc->sc_dev.dv_xname); 704 m_freem(m); 705 goto dropit; 706 } 707 } 708 709 m->m_data += 2; /* align payload */ 710 memcpy(mtod(m, caddr_t), 711 sc->sc_rxbufs[i].buf_vaddr, len); 712 AUMAC_INIT_RXDESC(sc, i); 713 714 m->m_pkthdr.rcvif = ifp; 715 m->m_pkthdr.len = m->m_len = len; 716 717 #if NBPFILTER > 0 718 /* Pass this up to any BPF listeners. */ 719 if (ifp->if_bpf) 720 bpf_mtap(ifp->if_bpf, m); 721 #endif /* NBPFILTER > 0 */ 722 723 /* Pass it on. */ 724 (*ifp->if_input)(ifp, m); 725 ifp->if_ipackets++; 726 } 727 if (pkts) 728 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 729 if (pkts == AUMAC_NRXDESC) 730 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 731 732 /* Update the receive pointer. */ 733 sc->sc_rxptr = i; 734 } 735 736 /* 737 * aumac_tick: 738 * 739 * One second timer, used to tick the MII. 740 */ 741 static void 742 aumac_tick(void *arg) 743 { 744 struct aumac_softc *sc = arg; 745 int s; 746 747 s = splnet(); 748 mii_tick(&sc->sc_mii); 749 splx(s); 750 751 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 752 } 753 754 /* 755 * aumac_init: [ifnet interface function] 756 * 757 * Initialize the interface. Must be called at splnet(). 758 */ 759 static int 760 aumac_init(struct ifnet *ifp) 761 { 762 struct aumac_softc *sc = ifp->if_softc; 763 int i, error = 0; 764 765 /* Cancel any pending I/O, reset MAC. */ 766 aumac_stop(ifp, 0); 767 768 /* Set up the transmit ring. */ 769 for (i = 0; i < AUMAC_NTXDESC; i++) { 770 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 771 MACDMA_TX_STAT(i), 0); 772 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 773 MACDMA_TX_LEN(i), 0); 774 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 775 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 776 } 777 sc->sc_txfree = AUMAC_NTXDESC; 778 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 779 MACDMA_TX_ADDR(0))); 780 sc->sc_txdirty = sc->sc_txnext; 781 782 /* Set up the receive ring. */ 783 for (i = 0; i < AUMAC_NRXDESC; i++) 784 AUMAC_INIT_RXDESC(sc, i); 785 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 786 MACDMA_RX_ADDR(0))); 787 788 /* 789 * Power up the MAC. 790 */ 791 aumac_powerup(sc); 792 793 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 794 #if _BYTE_ORDER == _BIG_ENDIAN 795 sc->sc_control |= CONTROL_EM; 796 #endif 797 798 /* Set the media. */ 799 aumac_mediachange(ifp); 800 801 /* 802 * Set the receive filter. This will actually start the transmit 803 * and receive processes. 804 */ 805 aumac_set_filter(sc); 806 807 /* Start the one second clock. */ 808 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 809 810 /* ...all done! */ 811 ifp->if_flags |= IFF_RUNNING; 812 ifp->if_flags &= ~IFF_OACTIVE; 813 814 if (error) 815 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 816 return (error); 817 } 818 819 /* 820 * aumac_stop: [ifnet interface function] 821 * 822 * Stop transmission on the interface. 823 */ 824 static void 825 aumac_stop(struct ifnet *ifp, int disable) 826 { 827 struct aumac_softc *sc = ifp->if_softc; 828 829 /* Stop the one-second clock. */ 830 callout_stop(&sc->sc_tick_ch); 831 832 /* Down the MII. */ 833 mii_down(&sc->sc_mii); 834 835 /* Stop the transmit and receive processes. */ 836 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 837 838 /* Power down/reset the MAC. */ 839 aumac_powerdown(sc); 840 841 /* Mark the interface as down and cancel the watchdog timer. */ 842 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 843 ifp->if_timer = 0; 844 } 845 846 /* 847 * aumac_powerdown: 848 * 849 * Power down the MAC. 850 */ 851 static void 852 aumac_powerdown(struct aumac_softc *sc) 853 { 854 855 /* Disable the MAC clocks, and place the device in reset. */ 856 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 857 858 // delay(10000); 859 } 860 861 /* 862 * aumac_powerup: 863 * 864 * Bring the device out of reset. 865 */ 866 static void 867 aumac_powerup(struct aumac_softc *sc) 868 { 869 870 /* Enable clocks to the MAC. */ 871 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 872 873 /* Enable MAC, coherent transactions, pass only valid frames. */ 874 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 875 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 876 877 delay(20000); 878 } 879 880 /* 881 * aumac_set_filter: 882 * 883 * Set up the receive filter. 884 */ 885 static void 886 aumac_set_filter(struct aumac_softc *sc) 887 { 888 struct ethercom *ec = &sc->sc_ethercom; 889 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 890 struct ether_multi *enm; 891 struct ether_multistep step; 892 const uint8_t *enaddr = LLADDR(ifp->if_sadl); 893 uint32_t mchash[2], crc; 894 895 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 896 897 /* Stop the receiver. */ 898 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 899 sc->sc_control & ~CONTROL_RE); 900 901 if (ifp->if_flags & IFF_PROMISC) { 902 sc->sc_control |= CONTROL_PR; 903 goto allmulti; 904 } 905 906 /* Set the station address. */ 907 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 908 enaddr[4] | (enaddr[5] << 8)); 909 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 910 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 911 (enaddr[3] << 24)); 912 913 sc->sc_control |= CONTROL_HP; 914 915 mchash[0] = mchash[1] = 0; 916 917 /* 918 * Set up the multicast address filter by passing all multicast 919 * addresses through a CRC generator, and then using the high 920 * order 6 bits as an index into the 64-bit multicast hash table. 921 * The high order bits select the word, while the rest of the bits 922 * select the bit within the word. 923 */ 924 ETHER_FIRST_MULTI(step, ec, enm); 925 while (enm != NULL) { 926 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 927 /* 928 * We must listen to a range of multicast addresses. 929 * For now, just accept all multicasts, rather than 930 * trying to set only those filter bits needed to match 931 * the range. (At this time, the only use of address 932 * ranges is for IP multicast routing, for which the 933 * range is large enough to require all bits set.) 934 */ 935 goto allmulti; 936 } 937 938 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 939 940 /* Just want the 6 most significant bits. */ 941 crc >>= 26; 942 943 /* Set the corresponding bit in the filter. */ 944 mchash[crc >> 5] |= 1U << (crc & 0x1f); 945 946 ETHER_NEXT_MULTI(step, enm); 947 } 948 949 ifp->if_flags &= ~IFF_ALLMULTI; 950 951 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 952 mchash[1]); 953 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 954 mchash[0]); 955 956 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 957 sc->sc_control); 958 return; 959 960 allmulti: 961 sc->sc_control |= CONTROL_PM; 962 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 963 sc->sc_control); 964 } 965 966 /* 967 * aumac_mediastatus: [ifmedia interface function] 968 * 969 * Get the current interface media status. 970 */ 971 static void 972 aumac_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 973 { 974 struct aumac_softc *sc = ifp->if_softc; 975 976 mii_pollstat(&sc->sc_mii); 977 ifmr->ifm_status = sc->sc_mii.mii_media_status; 978 ifmr->ifm_active = sc->sc_mii.mii_media_active; 979 } 980 981 /* 982 * aumac_mediachange: [ifmedia interface function] 983 * 984 * Set hardware to newly selected media. 985 */ 986 static int 987 aumac_mediachange(struct ifnet *ifp) 988 { 989 struct aumac_softc *sc = ifp->if_softc; 990 991 if (ifp->if_flags & IFF_UP) 992 mii_mediachg(&sc->sc_mii); 993 return (0); 994 } 995 996 /* 997 * aumac_mii_wait: 998 * 999 * Wait for the MII interface to not be busy. 1000 */ 1001 static int 1002 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 1003 { 1004 int i; 1005 1006 for (i = 0; i < 10000; i++) { 1007 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 1008 MAC_MIICTRL) & MIICTRL_MB) == 0) 1009 return (0); 1010 delay(10); 1011 } 1012 1013 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 1014 return (1); 1015 } 1016 1017 /* 1018 * aumac_mii_readreg: [mii interface function] 1019 * 1020 * Read a PHY register on the MII. 1021 */ 1022 static int 1023 aumac_mii_readreg(struct device *self, int phy, int reg) 1024 { 1025 struct aumac_softc *sc = (void *) self; 1026 1027 if (aumac_mii_wait(sc, "become ready")) 1028 return (0); 1029 1030 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1031 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1032 1033 if (aumac_mii_wait(sc, "complete")) 1034 return (0); 1035 1036 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1037 MIIDATA_MASK); 1038 } 1039 1040 /* 1041 * aumac_mii_writereg: [mii interface function] 1042 * 1043 * Write a PHY register on the MII. 1044 */ 1045 static void 1046 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1047 { 1048 struct aumac_softc *sc = (void *) self; 1049 1050 if (aumac_mii_wait(sc, "become ready")) 1051 return; 1052 1053 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1054 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1055 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1056 1057 (void) aumac_mii_wait(sc, "complete"); 1058 } 1059 1060 /* 1061 * aumac_mii_statchg: [mii interface function] 1062 * 1063 * Callback from MII layer when media changes. 1064 */ 1065 static void 1066 aumac_mii_statchg(struct device *self) 1067 { 1068 struct aumac_softc *sc = (void *) self; 1069 1070 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1071 sc->sc_control |= CONTROL_F; 1072 else 1073 sc->sc_control &= ~CONTROL_F; 1074 1075 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1076 sc->sc_control); 1077 } 1078