1 /* $NetBSD: if_aumac.c,v 1.25 2008/01/20 14:18:05 dogcow Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* 39 * Device driver for Alchemy Semiconductor Au1x00 Ethernet Media 40 * Access Controller. 41 * 42 * TODO: 43 * 44 * Better Rx buffer management; we want to get new Rx buffers 45 * to the chip more quickly than we currently do. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_aumac.c,v 1.25 2008/01/20 14:18:05 dogcow Exp $"); 50 51 #include "bpfilter.h" 52 #include "rnd.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/callout.h> 57 #include <sys/mbuf.h> 58 #include <sys/malloc.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/ioctl.h> 62 #include <sys/errno.h> 63 #include <sys/device.h> 64 #include <sys/queue.h> 65 66 #include <uvm/uvm_extern.h> /* for PAGE_SIZE */ 67 68 #include <net/if.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_ether.h> 72 73 #if NBPFILTER > 0 74 #include <net/bpf.h> 75 #endif 76 #if NRND > 0 77 #include <sys/rnd.h> 78 #endif 79 80 #include <machine/bus.h> 81 #include <machine/intr.h> 82 #include <machine/endian.h> 83 84 #include <dev/mii/mii.h> 85 #include <dev/mii/miivar.h> 86 87 #include <mips/alchemy/include/aureg.h> 88 #include <mips/alchemy/include/auvar.h> 89 #include <mips/alchemy/include/aubusvar.h> 90 #include <mips/alchemy/dev/if_aumacreg.h> 91 92 /* 93 * The Au1X00 MAC has 4 transmit and receive descriptors. Each buffer 94 * must consist of a single DMA segment, and must be aligned to a 2K 95 * boundary. Therefore, this driver does not perform DMA directly 96 * to/from mbufs. Instead, we copy the data to/from buffers allocated 97 * at device attach time. 98 * 99 * We also skip the bus_dma dance. The MAC is built in to the CPU, so 100 * there's little point in not making assumptions based on the CPU type. 101 * We also program the Au1X00 cache to be DMA coherent, so the buffers 102 * are accessed via KSEG0 addresses. 103 */ 104 #define AUMAC_NTXDESC 4 105 #define AUMAC_NTXDESC_MASK (AUMAC_NTXDESC - 1) 106 107 #define AUMAC_NRXDESC 4 108 #define AUMAC_NRXDESC_MASK (AUMAC_NRXDESC - 1) 109 110 #define AUMAC_NEXTTX(x) (((x) + 1) & AUMAC_NTXDESC_MASK) 111 #define AUMAC_NEXTRX(x) (((x) + 1) & AUMAC_NRXDESC_MASK) 112 113 #define AUMAC_TXBUF_OFFSET 0 114 #define AUMAC_RXBUF_OFFSET (MAC_BUFLEN * AUMAC_NTXDESC) 115 #define AUMAC_BUFSIZE (MAC_BUFLEN * (AUMAC_NTXDESC + AUMAC_NRXDESC)) 116 117 struct aumac_buf { 118 vaddr_t buf_vaddr; /* virtual address of buffer */ 119 bus_addr_t buf_paddr; /* DMA address of buffer */ 120 }; 121 122 /* 123 * Software state per device. 124 */ 125 struct aumac_softc { 126 struct device sc_dev; /* generic device information */ 127 bus_space_tag_t sc_st; /* bus space tag */ 128 bus_space_handle_t sc_mac_sh; /* MAC space handle */ 129 bus_space_handle_t sc_macen_sh; /* MAC enable space handle */ 130 bus_space_handle_t sc_dma_sh; /* DMA space handle */ 131 struct ethercom sc_ethercom; /* Ethernet common data */ 132 void *sc_sdhook; /* shutdown hook */ 133 134 void *sc_ih; /* interrupt cookie */ 135 136 struct mii_data sc_mii; /* MII/media information */ 137 138 struct callout sc_tick_ch; /* tick callout */ 139 140 /* Transmit and receive buffers */ 141 struct aumac_buf sc_txbufs[AUMAC_NTXDESC]; 142 struct aumac_buf sc_rxbufs[AUMAC_NRXDESC]; 143 void *sc_bufaddr; 144 145 int sc_txfree; /* number of free Tx descriptors */ 146 int sc_txnext; /* next Tx descriptor to use */ 147 int sc_txdirty; /* first dirty Tx descriptor */ 148 149 int sc_rxptr; /* next ready Rx descriptor */ 150 151 #if NRND > 0 152 rndsource_element_t rnd_source; 153 #endif 154 155 #ifdef AUMAC_EVENT_COUNTERS 156 struct evcnt sc_ev_txstall; /* Tx stalled */ 157 struct evcnt sc_ev_rxstall; /* Rx stalled */ 158 struct evcnt sc_ev_txintr; /* Tx interrupts */ 159 struct evcnt sc_ev_rxintr; /* Rx interrupts */ 160 #endif 161 162 uint32_t sc_control; /* MAC_CONTROL contents */ 163 uint32_t sc_flowctrl; /* MAC_FLOWCTRL contents */ 164 }; 165 166 #ifdef AUMAC_EVENT_COUNTERS 167 #define AUMAC_EVCNT_INCR(ev) (ev)->ev_count++ 168 #else 169 #define AUMAC_EVCNT_INCR(ev) /* nothing */ 170 #endif 171 172 #define AUMAC_INIT_RXDESC(sc, x) \ 173 do { \ 174 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 175 MACDMA_RX_STAT((x)), 0); \ 176 bus_space_write_4((sc)->sc_st, (sc)->sc_dma_sh, \ 177 MACDMA_RX_ADDR((x)), \ 178 (sc)->sc_rxbufs[(x)].buf_paddr | RX_ADDR_EN); \ 179 } while (/*CONSTCOND*/0) 180 181 static void aumac_start(struct ifnet *); 182 static void aumac_watchdog(struct ifnet *); 183 static int aumac_ioctl(struct ifnet *, u_long, void *); 184 static int aumac_init(struct ifnet *); 185 static void aumac_stop(struct ifnet *, int); 186 187 static void aumac_shutdown(void *); 188 189 static void aumac_tick(void *); 190 191 static void aumac_set_filter(struct aumac_softc *); 192 193 static void aumac_powerup(struct aumac_softc *); 194 static void aumac_powerdown(struct aumac_softc *); 195 196 static int aumac_intr(void *); 197 static int aumac_txintr(struct aumac_softc *); 198 static int aumac_rxintr(struct aumac_softc *); 199 200 static int aumac_mii_readreg(struct device *, int, int); 201 static void aumac_mii_writereg(struct device *, int, int, int); 202 static void aumac_mii_statchg(struct device *); 203 static int aumac_mii_wait(struct aumac_softc *, const char *); 204 205 static int aumac_match(struct device *, struct cfdata *, void *); 206 static void aumac_attach(struct device *, struct device *, void *); 207 208 int aumac_copy_small = 0; 209 210 CFATTACH_DECL(aumac, sizeof(struct aumac_softc), 211 aumac_match, aumac_attach, NULL, NULL); 212 213 static int 214 aumac_match(struct device *parent, struct cfdata *cf, void *aux) 215 { 216 struct aubus_attach_args *aa = aux; 217 218 if (strcmp(aa->aa_name, cf->cf_name) == 0) 219 return (1); 220 221 return (0); 222 } 223 224 static void 225 aumac_attach(struct device *parent, struct device *self, void *aux) 226 { 227 const uint8_t *enaddr; 228 prop_data_t ea; 229 struct aumac_softc *sc = (void *) self; 230 struct aubus_attach_args *aa = aux; 231 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 232 struct pglist pglist; 233 paddr_t bufaddr; 234 vaddr_t vbufaddr; 235 int i; 236 237 callout_init(&sc->sc_tick_ch, 0); 238 239 printf(": Au1X00 10/100 Ethernet\n"); 240 241 sc->sc_st = aa->aa_st; 242 243 /* Get the MAC address. */ 244 ea = prop_dictionary_get(device_properties(&sc->sc_dev), "mac-addr"); 245 if (ea == NULL) { 246 printf("%s: unable to get mac-addr property\n", 247 sc->sc_dev.dv_xname); 248 return; 249 } 250 KASSERT(prop_object_type(ea) == PROP_TYPE_DATA); 251 KASSERT(prop_data_size(ea) == ETHER_ADDR_LEN); 252 enaddr = prop_data_data_nocopy(ea); 253 254 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 255 ether_sprintf(enaddr)); 256 257 /* Map the device. */ 258 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_BASE], 259 MACx_SIZE, 0, &sc->sc_mac_sh) != 0) { 260 printf("%s: unable to map MAC registers\n", 261 sc->sc_dev.dv_xname); 262 return; 263 } 264 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_ENABLE], 265 MACENx_SIZE, 0, &sc->sc_macen_sh) != 0) { 266 printf("%s: unable to map MACEN registers\n", 267 sc->sc_dev.dv_xname); 268 return; 269 } 270 if (bus_space_map(sc->sc_st, aa->aa_addrs[AA_MAC_DMA_BASE], 271 MACx_DMA_SIZE, 0, &sc->sc_dma_sh) != 0) { 272 printf("%s: unable to map MACDMA registers\n", 273 sc->sc_dev.dv_xname); 274 return; 275 } 276 277 /* Make sure the MAC is powered off. */ 278 aumac_powerdown(sc); 279 280 /* Hook up the interrupt handler. */ 281 sc->sc_ih = au_intr_establish(aa->aa_irq[0], 1, IPL_NET, IST_LEVEL, 282 aumac_intr, sc); 283 if (sc->sc_ih == NULL) { 284 printf("%s: unable to register interrupt handler\n", 285 sc->sc_dev.dv_xname); 286 return; 287 } 288 289 /* 290 * Allocate space for the transmit and receive buffers. 291 */ 292 if (uvm_pglistalloc(AUMAC_BUFSIZE, 0, ctob(physmem), PAGE_SIZE, 0, 293 &pglist, 1, 0)) 294 return; 295 296 bufaddr = VM_PAGE_TO_PHYS(TAILQ_FIRST(&pglist)); 297 vbufaddr = MIPS_PHYS_TO_KSEG0(bufaddr); 298 299 for (i = 0; i < AUMAC_NTXDESC; i++) { 300 int offset = AUMAC_TXBUF_OFFSET + (i * MAC_BUFLEN); 301 302 sc->sc_txbufs[i].buf_vaddr = vbufaddr + offset; 303 sc->sc_txbufs[i].buf_paddr = bufaddr + offset; 304 } 305 306 for (i = 0; i < AUMAC_NRXDESC; i++) { 307 int offset = AUMAC_RXBUF_OFFSET + (i * MAC_BUFLEN); 308 309 sc->sc_rxbufs[i].buf_vaddr = vbufaddr + offset; 310 sc->sc_rxbufs[i].buf_paddr = bufaddr + offset; 311 } 312 313 /* 314 * Power up the MAC before accessing any MAC registers (including 315 * MII configuration. 316 */ 317 aumac_powerup(sc); 318 319 /* 320 * Initialize the media structures and probe the MII. 321 */ 322 sc->sc_mii.mii_ifp = ifp; 323 sc->sc_mii.mii_readreg = aumac_mii_readreg; 324 sc->sc_mii.mii_writereg = aumac_mii_writereg; 325 sc->sc_mii.mii_statchg = aumac_mii_statchg; 326 sc->sc_ethercom.ec_mii = &sc->sc_mii; 327 ifmedia_init(&sc->sc_mii.mii_media, 0, ether_mediachange, 328 ether_mediastatus); 329 330 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 331 MII_OFFSET_ANY, 0); 332 333 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 334 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 335 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 336 } else 337 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 338 339 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 340 ifp->if_softc = sc; 341 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 342 ifp->if_ioctl = aumac_ioctl; 343 ifp->if_start = aumac_start; 344 ifp->if_watchdog = aumac_watchdog; 345 ifp->if_init = aumac_init; 346 ifp->if_stop = aumac_stop; 347 IFQ_SET_READY(&ifp->if_snd); 348 349 /* Attach the interface. */ 350 if_attach(ifp); 351 ether_ifattach(ifp, enaddr); 352 353 #if NRND > 0 354 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 355 RND_TYPE_NET, 0); 356 #endif 357 358 #ifdef AUMAC_EVENT_COUNTERS 359 evcnt_attach_dynamic(&sc->sc_ev_txstall, EVCNT_TYPE_MISC, 360 NULL, sc->sc_dev.dv_xname, "txstall"); 361 evcnt_attach_dynamic(&sc->sc_ev_rxstall, EVCNT_TYPE_MISC, 362 NULL, sc->sc_dev.dv_xname, "rxstall"); 363 evcnt_attach_dynamic(&sc->sc_ev_txintr, EVCNT_TYPE_MISC, 364 NULL, sc->sc_dev.dv_xname, "txintr"); 365 evcnt_attach_dynamic(&sc->sc_ev_rxintr, EVCNT_TYPE_MISC, 366 NULL, sc->sc_dev.dv_xname, "rxintr"); 367 #endif 368 369 /* Make sure the interface is shutdown during reboot. */ 370 sc->sc_sdhook = shutdownhook_establish(aumac_shutdown, sc); 371 if (sc->sc_sdhook == NULL) 372 printf("%s: WARNING: unable to establish shutdown hook\n", 373 sc->sc_dev.dv_xname); 374 return; 375 } 376 377 /* 378 * aumac_shutdown: 379 * 380 * Make sure the interface is stopped at reboot time. 381 */ 382 static void 383 aumac_shutdown(void *arg) 384 { 385 struct aumac_softc *sc = arg; 386 387 aumac_stop(&sc->sc_ethercom.ec_if, 1); 388 389 /* 390 * XXX aumac_stop leaves device powered up at the moment 391 * XXX but this still isn't enough to keep yamon happy... :-( 392 */ 393 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 0); 394 } 395 396 /* 397 * aumac_start: [ifnet interface function] 398 * 399 * Start packet transmission on the interface. 400 */ 401 static void 402 aumac_start(struct ifnet *ifp) 403 { 404 struct aumac_softc *sc = ifp->if_softc; 405 struct mbuf *m; 406 int nexttx; 407 408 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 409 return; 410 411 /* 412 * Loop through the send queue, setting up transmit descriptors 413 * unitl we drain the queue, or use up all available transmit 414 * descriptors. 415 */ 416 for (;;) { 417 /* Grab a packet off the queue. */ 418 IFQ_POLL(&ifp->if_snd, m); 419 if (m == NULL) 420 return; 421 422 /* Get a spare descriptor. */ 423 if (sc->sc_txfree == 0) { 424 /* No more slots left; notify upper layer. */ 425 ifp->if_flags |= IFF_OACTIVE; 426 AUMAC_EVCNT_INCR(&sc->sc_ev_txstall); 427 return; 428 } 429 nexttx = sc->sc_txnext; 430 431 IFQ_DEQUEUE(&ifp->if_snd, m); 432 433 /* 434 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. 435 */ 436 437 m_copydata(m, 0, m->m_pkthdr.len, 438 (void *)sc->sc_txbufs[nexttx].buf_vaddr); 439 440 /* Zero out the remainder of any short packets. */ 441 if (m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 442 memset((char *)sc->sc_txbufs[nexttx].buf_vaddr + 443 m->m_pkthdr.len, 0, 444 ETHER_MIN_LEN - ETHER_CRC_LEN - m->m_pkthdr.len); 445 446 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 447 MACDMA_TX_STAT(nexttx), 0); 448 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 449 MACDMA_TX_LEN(nexttx), 450 m->m_pkthdr.len < (ETHER_MIN_LEN - ETHER_CRC_LEN) ? 451 ETHER_MIN_LEN - ETHER_CRC_LEN : m->m_pkthdr.len); 452 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 453 MACDMA_TX_ADDR(nexttx), 454 sc->sc_txbufs[nexttx].buf_paddr | TX_ADDR_EN); 455 /* XXX - needed?? we should be coherent */ 456 bus_space_barrier(sc->sc_st, sc->sc_dma_sh, 0 /* XXX */, 457 0 /* XXX */, BUS_SPACE_BARRIER_WRITE); 458 459 /* Advance the Tx pointer. */ 460 sc->sc_txfree--; 461 sc->sc_txnext = AUMAC_NEXTTX(nexttx); 462 463 #if NBPFILTER > 0 464 /* Pass the packet to any BPF listeners. */ 465 if (ifp->if_bpf) 466 bpf_mtap(ifp->if_bpf, m); 467 #endif /* NBPFILTER */ 468 469 m_freem(m); 470 471 /* Set a watchdog timer in case the chip flakes out. */ 472 ifp->if_timer = 5; 473 } 474 /* NOTREACHED */ 475 } 476 477 /* 478 * aumac_watchdog: [ifnet interface function] 479 * 480 * Watchdog timer handler. 481 */ 482 static void 483 aumac_watchdog(struct ifnet *ifp) 484 { 485 struct aumac_softc *sc = ifp->if_softc; 486 487 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 488 (void) aumac_init(ifp); 489 490 /* Try to get more packets going. */ 491 aumac_start(ifp); 492 } 493 494 /* 495 * aumac_ioctl: [ifnet interface function] 496 * 497 * Handle control requests from the operator. 498 */ 499 static int 500 aumac_ioctl(struct ifnet *ifp, u_long cmd, void *data) 501 { 502 struct aumac_softc *sc = ifp->if_softc; 503 int s, error; 504 505 s = splnet(); 506 507 error = ether_ioctl(ifp, cmd, data); 508 if (error == ENETRESET) { 509 /* 510 * Multicast list has changed; set the hardware filter 511 * accordingly. 512 */ 513 if (ifp->if_flags & IFF_RUNNING) 514 aumac_set_filter(sc); 515 } 516 517 /* Try to get more packets going. */ 518 aumac_start(ifp); 519 520 splx(s); 521 return (error); 522 } 523 524 /* 525 * aumac_intr: 526 * 527 * Interrupt service routine. 528 */ 529 static int 530 aumac_intr(void *arg) 531 { 532 struct aumac_softc *sc = arg; 533 int status; 534 535 /* 536 * There aren't really any interrupt status bits on the 537 * Au1X00 MAC, and each MAC has a dedicated interrupt 538 * in the CPU's built-in interrupt controller. Just 539 * check for new incoming packets, and then Tx completions 540 * (for status updating). 541 */ 542 if ((sc->sc_ethercom.ec_if.if_flags & IFF_RUNNING) == 0) 543 return (0); 544 545 status = aumac_rxintr(sc); 546 status += aumac_txintr(sc); 547 548 #if NRND > 0 549 if (RND_ENABLED(&sc->rnd_source)) 550 rnd_add_uint32(&sc->rnd_source, status); 551 #endif 552 553 return status; 554 } 555 556 /* 557 * aumac_txintr: 558 * 559 * Helper; handle transmit interrupts. 560 */ 561 static int 562 aumac_txintr(struct aumac_softc *sc) 563 { 564 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 565 uint32_t stat; 566 int i; 567 int pkts = 0; 568 569 for (i = sc->sc_txdirty; sc->sc_txfree != AUMAC_NTXDESC; 570 i = AUMAC_NEXTTX(i)) { 571 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 572 MACDMA_TX_ADDR(i)) & TX_ADDR_DN) == 0) 573 break; 574 pkts++; 575 576 /* ACK interrupt. */ 577 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 578 MACDMA_TX_ADDR(i), 0); 579 580 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 581 MACDMA_TX_STAT(i)); 582 583 if (stat & TX_STAT_FA) { 584 /* XXX STATS */ 585 ifp->if_oerrors++; 586 } else 587 ifp->if_opackets++; 588 589 if (stat & TX_STAT_EC) 590 ifp->if_collisions += 16; 591 else 592 ifp->if_collisions += TX_STAT_CC(stat); 593 594 sc->sc_txfree++; 595 ifp->if_flags &= ~IFF_OACTIVE; 596 597 /* Try to queue more packets. */ 598 aumac_start(ifp); 599 } 600 601 if (pkts) 602 AUMAC_EVCNT_INCR(&sc->sc_ev_txintr); 603 604 /* Update the dirty descriptor pointer. */ 605 sc->sc_txdirty = i; 606 607 /* 608 * If there are no more pending transmissions, cancel the watchdog 609 * timer. 610 */ 611 if (sc->sc_txfree == AUMAC_NTXDESC) 612 ifp->if_timer = 0; 613 614 return pkts; 615 } 616 617 /* 618 * aumac_rxintr: 619 * 620 * Helper; handle receive interrupts. 621 */ 622 static int 623 aumac_rxintr(struct aumac_softc *sc) 624 { 625 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 626 struct mbuf *m; 627 uint32_t stat; 628 int i, len; 629 int pkts = 0; 630 631 for (i = sc->sc_rxptr;; i = AUMAC_NEXTRX(i)) { 632 if ((bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 633 MACDMA_RX_ADDR(i)) & RX_ADDR_DN) == 0) 634 break; 635 pkts++; 636 637 stat = bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 638 MACDMA_RX_STAT(i)); 639 640 #define PRINTERR(str) \ 641 do { \ 642 error++; \ 643 printf("%s: %s\n", sc->sc_dev.dv_xname, str); \ 644 } while (0) 645 646 if (stat & RX_STAT_ERRS) { 647 int error = 0; 648 649 #if 0 /* 650 * Missed frames are a semi-frequent occurence with this hardware, 651 * and reporting of them just makes everything run slower and fills 652 * the system log. Be silent. 653 * 654 * Additionally, this missed bit indicates an error with the previous 655 * packet, and not with this one! So PRINTERR is definitely wrong 656 * here. 657 * 658 * These should probably all be converted to evcnt counters anyway. 659 */ 660 if (stat & RX_STAT_MI) 661 PRINTERR("missed frame"); 662 #endif 663 if (stat & RX_STAT_UC) 664 PRINTERR("unknown control frame"); 665 if (stat & RX_STAT_LE) 666 PRINTERR("short frame"); 667 if (stat & RX_STAT_CR) 668 PRINTERR("CRC error"); 669 if (stat & RX_STAT_ME) 670 PRINTERR("medium error"); 671 if (stat & RX_STAT_CS) 672 PRINTERR("late collision"); 673 if (stat & RX_STAT_FL) 674 PRINTERR("frame too big"); 675 if (stat & RX_STAT_RF) 676 PRINTERR("runt frame (collision)"); 677 if (stat & RX_STAT_WT) 678 PRINTERR("watch dog"); 679 if (stat & RX_STAT_DB) { 680 if (stat & (RX_STAT_CS | RX_STAT_RF | 681 RX_STAT_CR)) { 682 if (!error) 683 goto pktok; 684 } else 685 PRINTERR("dribbling bit"); 686 } 687 #undef PRINTERR 688 ifp->if_ierrors++; 689 690 dropit: 691 /* reuse the current descriptor */ 692 AUMAC_INIT_RXDESC(sc, i); 693 continue; 694 } 695 pktok: 696 len = RX_STAT_L(stat); 697 698 /* 699 * The Au1X00 MAC includes the CRC with every packet; 700 * trim it off here. 701 */ 702 len -= ETHER_CRC_LEN; 703 704 /* 705 * Truncate the packet if it's too big to fit in 706 * a single mbuf cluster. 707 */ 708 if (len > MCLBYTES - 2) 709 len = MCLBYTES - 2; 710 711 MGETHDR(m, M_DONTWAIT, MT_DATA); 712 if (m == NULL) { 713 printf("%s: unable to allocate Rx mbuf\n", 714 sc->sc_dev.dv_xname); 715 goto dropit; 716 } 717 if (len > MHLEN - 2) { 718 MCLGET(m, M_DONTWAIT); 719 if ((m->m_flags & M_EXT) == 0) { 720 printf("%s: unable to allocate Rx cluster\n", 721 sc->sc_dev.dv_xname); 722 m_freem(m); 723 goto dropit; 724 } 725 } 726 727 m->m_data += 2; /* align payload */ 728 memcpy(mtod(m, void *), 729 (void *)sc->sc_rxbufs[i].buf_vaddr, len); 730 AUMAC_INIT_RXDESC(sc, i); 731 732 m->m_pkthdr.rcvif = ifp; 733 m->m_pkthdr.len = m->m_len = len; 734 735 #if NBPFILTER > 0 736 /* Pass this up to any BPF listeners. */ 737 if (ifp->if_bpf) 738 bpf_mtap(ifp->if_bpf, m); 739 #endif /* NBPFILTER > 0 */ 740 741 /* Pass it on. */ 742 (*ifp->if_input)(ifp, m); 743 ifp->if_ipackets++; 744 } 745 if (pkts) 746 AUMAC_EVCNT_INCR(&sc->sc_ev_rxintr); 747 if (pkts == AUMAC_NRXDESC) 748 AUMAC_EVCNT_INCR(&sc->sc_ev_rxstall); 749 750 /* Update the receive pointer. */ 751 sc->sc_rxptr = i; 752 753 return pkts; 754 } 755 756 /* 757 * aumac_tick: 758 * 759 * One second timer, used to tick the MII. 760 */ 761 static void 762 aumac_tick(void *arg) 763 { 764 struct aumac_softc *sc = arg; 765 int s; 766 767 s = splnet(); 768 mii_tick(&sc->sc_mii); 769 splx(s); 770 771 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 772 } 773 774 /* 775 * aumac_init: [ifnet interface function] 776 * 777 * Initialize the interface. Must be called at splnet(). 778 */ 779 static int 780 aumac_init(struct ifnet *ifp) 781 { 782 struct aumac_softc *sc = ifp->if_softc; 783 int i, error = 0; 784 785 /* Cancel any pending I/O, reset MAC. */ 786 aumac_stop(ifp, 0); 787 788 /* Set up the transmit ring. */ 789 for (i = 0; i < AUMAC_NTXDESC; i++) { 790 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 791 MACDMA_TX_STAT(i), 0); 792 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 793 MACDMA_TX_LEN(i), 0); 794 bus_space_write_4(sc->sc_st, sc->sc_dma_sh, 795 MACDMA_TX_ADDR(i), sc->sc_txbufs[i].buf_paddr); 796 } 797 sc->sc_txfree = AUMAC_NTXDESC; 798 sc->sc_txnext = TX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 799 MACDMA_TX_ADDR(0))); 800 sc->sc_txdirty = sc->sc_txnext; 801 802 /* Set up the receive ring. */ 803 for (i = 0; i < AUMAC_NRXDESC; i++) 804 AUMAC_INIT_RXDESC(sc, i); 805 sc->sc_rxptr = RX_ADDR_CB(bus_space_read_4(sc->sc_st, sc->sc_dma_sh, 806 MACDMA_RX_ADDR(0))); 807 808 /* 809 * Power up the MAC. 810 */ 811 aumac_powerup(sc); 812 813 sc->sc_control |= CONTROL_DO | CONTROL_TE | CONTROL_RE; 814 #if _BYTE_ORDER == _BIG_ENDIAN 815 sc->sc_control |= CONTROL_EM; 816 #endif 817 818 /* Set the media. */ 819 if ((error = ether_mediachange(ifp)) != 0) 820 goto out; 821 822 /* 823 * Set the receive filter. This will actually start the transmit 824 * and receive processes. 825 */ 826 aumac_set_filter(sc); 827 828 /* Start the one second clock. */ 829 callout_reset(&sc->sc_tick_ch, hz, aumac_tick, sc); 830 831 /* ...all done! */ 832 ifp->if_flags |= IFF_RUNNING; 833 ifp->if_flags &= ~IFF_OACTIVE; 834 835 out: 836 if (error) 837 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 838 return (error); 839 } 840 841 /* 842 * aumac_stop: [ifnet interface function] 843 * 844 * Stop transmission on the interface. 845 */ 846 static void 847 aumac_stop(struct ifnet *ifp, int disable) 848 { 849 struct aumac_softc *sc = ifp->if_softc; 850 851 /* Stop the one-second clock. */ 852 callout_stop(&sc->sc_tick_ch); 853 854 /* Down the MII. */ 855 mii_down(&sc->sc_mii); 856 857 /* Stop the transmit and receive processes. */ 858 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 0); 859 860 /* Power down/reset the MAC. */ 861 aumac_powerdown(sc); 862 863 /* Mark the interface as down and cancel the watchdog timer. */ 864 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 865 ifp->if_timer = 0; 866 } 867 868 /* 869 * aumac_powerdown: 870 * 871 * Power down the MAC. 872 */ 873 static void 874 aumac_powerdown(struct aumac_softc *sc) 875 { 876 877 /* Disable the MAC clocks, and place the device in reset. */ 878 // bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP); 879 880 // delay(10000); 881 } 882 883 /* 884 * aumac_powerup: 885 * 886 * Bring the device out of reset. 887 */ 888 static void 889 aumac_powerup(struct aumac_softc *sc) 890 { 891 892 /* Enable clocks to the MAC. */ 893 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, MACEN_JP|MACEN_CE); 894 895 /* Enable MAC, coherent transactions, pass only valid frames. */ 896 bus_space_write_4(sc->sc_st, sc->sc_macen_sh, 0, 897 MACEN_E2|MACEN_E1|MACEN_E0|MACEN_CE); 898 899 delay(20000); 900 } 901 902 /* 903 * aumac_set_filter: 904 * 905 * Set up the receive filter. 906 */ 907 static void 908 aumac_set_filter(struct aumac_softc *sc) 909 { 910 struct ethercom *ec = &sc->sc_ethercom; 911 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 912 struct ether_multi *enm; 913 struct ether_multistep step; 914 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 915 uint32_t mchash[2], crc; 916 917 sc->sc_control &= ~(CONTROL_PM | CONTROL_PR); 918 919 /* Stop the receiver. */ 920 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 921 sc->sc_control & ~CONTROL_RE); 922 923 if (ifp->if_flags & IFF_PROMISC) { 924 sc->sc_control |= CONTROL_PR; 925 goto allmulti; 926 } 927 928 /* Set the station address. */ 929 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRHIGH, 930 enaddr[4] | (enaddr[5] << 8)); 931 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_ADDRLOW, 932 enaddr[0] | (enaddr[1] << 8) | (enaddr[2] << 16) | 933 (enaddr[3] << 24)); 934 935 sc->sc_control |= CONTROL_HP; 936 937 mchash[0] = mchash[1] = 0; 938 939 /* 940 * Set up the multicast address filter by passing all multicast 941 * addresses through a CRC generator, and then using the high 942 * order 6 bits as an index into the 64-bit multicast hash table. 943 * The high order bits select the word, while the rest of the bits 944 * select the bit within the word. 945 */ 946 ETHER_FIRST_MULTI(step, ec, enm); 947 while (enm != NULL) { 948 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 949 /* 950 * We must listen to a range of multicast addresses. 951 * For now, just accept all multicasts, rather than 952 * trying to set only those filter bits needed to match 953 * the range. (At this time, the only use of address 954 * ranges is for IP multicast routing, for which the 955 * range is large enough to require all bits set.) 956 */ 957 goto allmulti; 958 } 959 960 crc = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 961 962 /* Just want the 6 most significant bits. */ 963 crc >>= 26; 964 965 /* Set the corresponding bit in the filter. */ 966 mchash[crc >> 5] |= 1U << (crc & 0x1f); 967 968 ETHER_NEXT_MULTI(step, enm); 969 } 970 971 ifp->if_flags &= ~IFF_ALLMULTI; 972 973 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHHIGH, 974 mchash[1]); 975 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_HASHLOW, 976 mchash[0]); 977 978 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 979 sc->sc_control); 980 return; 981 982 allmulti: 983 sc->sc_control |= CONTROL_PM; 984 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 985 sc->sc_control); 986 } 987 988 /* 989 * aumac_mii_wait: 990 * 991 * Wait for the MII interface to not be busy. 992 */ 993 static int 994 aumac_mii_wait(struct aumac_softc *sc, const char *msg) 995 { 996 int i; 997 998 for (i = 0; i < 10000; i++) { 999 if ((bus_space_read_4(sc->sc_st, sc->sc_mac_sh, 1000 MAC_MIICTRL) & MIICTRL_MB) == 0) 1001 return (0); 1002 delay(10); 1003 } 1004 1005 printf("%s: MII failed to %s\n", sc->sc_dev.dv_xname, msg); 1006 return (1); 1007 } 1008 1009 /* 1010 * aumac_mii_readreg: [mii interface function] 1011 * 1012 * Read a PHY register on the MII. 1013 */ 1014 static int 1015 aumac_mii_readreg(struct device *self, int phy, int reg) 1016 { 1017 struct aumac_softc *sc = (void *) self; 1018 1019 if (aumac_mii_wait(sc, "become ready")) 1020 return (0); 1021 1022 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1023 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg)); 1024 1025 if (aumac_mii_wait(sc, "complete")) 1026 return (0); 1027 1028 return (bus_space_read_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA) & 1029 MIIDATA_MASK); 1030 } 1031 1032 /* 1033 * aumac_mii_writereg: [mii interface function] 1034 * 1035 * Write a PHY register on the MII. 1036 */ 1037 static void 1038 aumac_mii_writereg(struct device *self, int phy, int reg, int val) 1039 { 1040 struct aumac_softc *sc = (void *) self; 1041 1042 if (aumac_mii_wait(sc, "become ready")) 1043 return; 1044 1045 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIIDATA, val); 1046 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_MIICTRL, 1047 MIICTRL_PHYADDR(phy) | MIICTRL_MIIREG(reg) | MIICTRL_MW); 1048 1049 (void) aumac_mii_wait(sc, "complete"); 1050 } 1051 1052 /* 1053 * aumac_mii_statchg: [mii interface function] 1054 * 1055 * Callback from MII layer when media changes. 1056 */ 1057 static void 1058 aumac_mii_statchg(struct device *self) 1059 { 1060 struct aumac_softc *sc = (void *) self; 1061 1062 if ((sc->sc_mii.mii_media_active & IFM_FDX) != 0) 1063 sc->sc_control |= CONTROL_F; 1064 else 1065 sc->sc_control &= ~CONTROL_F; 1066 1067 bus_space_write_4(sc->sc_st, sc->sc_mac_sh, MAC_CONTROL, 1068 sc->sc_control); 1069 } 1070