1 /* $NetBSD: aupcmcia.c,v 1.7 2011/07/26 22:52:49 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* #include "opt_pci.h" */ 35 /* #include "pci.h" */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: aupcmcia.c,v 1.7 2011/07/26 22:52:49 dyoung Exp $"); 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/errno.h> 44 #include <sys/kernel.h> 45 #include <sys/kthread.h> 46 #include <sys/intr.h> 47 #include <sys/device.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 #include <dev/pcmcia/pcmciachip.h> 52 53 #include <mips/alchemy/include/au_himem_space.h> 54 #include <mips/alchemy/include/aubusvar.h> 55 #include <mips/alchemy/include/aureg.h> 56 #include <mips/alchemy/include/auvar.h> 57 58 #include <mips/alchemy/dev/aupcmciareg.h> 59 #include <mips/alchemy/dev/aupcmciavar.h> 60 61 /* 62 * Borrow PCMCIADEBUG for now. Generally aupcmcia is the only PCMCIA 63 * host on these machines anyway. 64 */ 65 #ifdef PCMCIADEBUG 66 int aupcm_debug = 1; 67 #define DPRINTF(arg) if (aupcm_debug) printf arg 68 #else 69 #define DPRINTF(arg) 70 #endif 71 72 /* 73 * And for information about mappings, etc. use this one. 74 */ 75 #ifdef AUPCMCIANOISY 76 #define NOISY(arg) printf arg 77 #else 78 #define NOISY(arg) 79 #endif 80 81 /* 82 * Note, we use prefix "aupcm" instead of "aupcmcia", even though our 83 * driver is the latter, mostly because my fingers have trouble typing 84 * the former. "aupcm" should be sufficiently unique to avoid 85 * confusion. 86 */ 87 88 static int aupcm_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 89 struct pcmcia_mem_handle *); 90 static void aupcm_mem_free(pcmcia_chipset_handle_t, 91 struct pcmcia_mem_handle *); 92 static int aupcm_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 93 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 94 static void aupcm_mem_unmap(pcmcia_chipset_handle_t, int); 95 96 static int aupcm_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t, 97 bus_size_t, struct pcmcia_io_handle *); 98 static void aupcm_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *); 99 static int aupcm_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 100 bus_size_t, struct pcmcia_io_handle *, int *); 101 static void aupcm_io_unmap(pcmcia_chipset_handle_t, int); 102 static void *aupcm_intr_establish(pcmcia_chipset_handle_t, 103 struct pcmcia_function *, int, int (*)(void *), void *); 104 static void aupcm_intr_disestablish(pcmcia_chipset_handle_t, void *); 105 106 static void aupcm_slot_enable(pcmcia_chipset_handle_t); 107 static void aupcm_slot_disable(pcmcia_chipset_handle_t); 108 static void aupcm_slot_settype(pcmcia_chipset_handle_t, int); 109 110 static int aupcm_match(struct device *, struct cfdata *, void *); 111 static void aupcm_attach(struct device *, struct device *, void *); 112 113 static void aupcm_event_thread(void *); 114 static int aupcm_card_intr(void *); 115 static void aupcm_softintr(void *); 116 static int aupcm_print(void *, const char *); 117 118 struct aupcm_slot { 119 struct aupcm_softc *as_softc; 120 int as_slot; 121 int as_status; 122 int as_enabled; 123 int (*as_intr)(void *); 124 int as_card_irq; 125 int as_status_irq; 126 void *as_intrarg; 127 void *as_softint; 128 void *as_hardint; 129 const char *as_name; 130 bus_addr_t as_offset; 131 struct mips_bus_space as_iot; 132 struct mips_bus_space as_attrt; 133 struct mips_bus_space as_memt; 134 void *as_wins[AUPCMCIA_NWINS]; 135 136 struct device *as_pcmcia; 137 }; 138 139 /* this structure needs to be exposed... */ 140 struct aupcm_softc { 141 struct device sc_dev; 142 pcmcia_chipset_tag_t sc_pct; 143 144 void (*sc_slot_enable)(int); 145 void (*sc_slot_disable)(int); 146 int (*sc_slot_status)(int); 147 148 paddr_t sc_base; 149 150 int sc_wake; 151 lwp_t *sc_thread; 152 153 int sc_nslots; 154 struct aupcm_slot sc_slots[AUPCMCIA_NSLOTS]; 155 }; 156 157 static struct pcmcia_chip_functions aupcm_functions = { 158 aupcm_mem_alloc, 159 aupcm_mem_free, 160 aupcm_mem_map, 161 aupcm_mem_unmap, 162 163 aupcm_io_alloc, 164 aupcm_io_free, 165 aupcm_io_map, 166 aupcm_io_unmap, 167 168 aupcm_intr_establish, 169 aupcm_intr_disestablish, 170 171 aupcm_slot_enable, 172 aupcm_slot_disable, 173 aupcm_slot_settype, 174 }; 175 176 static struct mips_bus_space aupcm_memt; 177 178 CFATTACH_DECL(aupcmcia, sizeof (struct aupcm_softc), 179 aupcm_match, aupcm_attach, NULL, NULL); 180 181 int 182 aupcm_match(struct device *parent, struct cfdata *cf, void *aux) 183 { 184 struct aubus_attach_args *aa = aux; 185 static int found = 0; 186 187 if (found) 188 return 0; 189 190 if (strcmp(aa->aa_name, "aupcmcia") != 0) 191 return 0; 192 193 found = 1; 194 195 return 1; 196 } 197 198 void 199 aupcm_attach(struct device *parent, struct device *self, void *aux) 200 { 201 /* struct aubus_attach_args *aa = aux; */ 202 struct aupcm_softc *sc = (struct aupcm_softc *)self; 203 static int done = 0; 204 int slot; 205 struct aupcmcia_machdep *md; 206 207 /* initialize bus space */ 208 if (done) { 209 /* there can be only one. */ 210 return; 211 } 212 213 done = 1; 214 /* 215 * PCMCIA memory can live within pretty much the entire 32-bit 216 * space, modulo 64 MB wraps. We don't have to support coexisting 217 * DMA. 218 */ 219 au_himem_space_init(&aupcm_memt, "pcmciamem", 220 PCMCIA_BASE, AUPCMCIA_ATTR_OFFSET, 0xffffffff, 221 AU_HIMEM_SPACE_LITTLE_ENDIAN); 222 223 if ((md = aupcmcia_machdep()) == NULL) { 224 printf("\n%s:unable to get machdep structure\n", 225 sc->sc_dev.dv_xname); 226 return; 227 } 228 229 sc->sc_nslots = md->am_nslots; 230 sc->sc_slot_enable = md->am_slot_enable; 231 sc->sc_slot_disable = md->am_slot_disable; 232 sc->sc_slot_status = md->am_slot_status; 233 234 printf(": Alchemy PCMCIA, %d slots\n", sc->sc_nslots); 235 236 sc->sc_pct = (pcmcia_chipset_tag_t)&aupcm_functions; 237 238 for (slot = 0; slot < sc->sc_nslots; slot++) { 239 struct aupcm_slot *sp; 240 struct pcmciabus_attach_args paa; 241 242 sp = &sc->sc_slots[slot]; 243 sp->as_softc = sc; 244 245 sp->as_slot = slot; 246 sp->as_name = md->am_slot_name(slot); 247 sp->as_offset = md->am_slot_offset(slot); 248 sp->as_card_irq = md->am_slot_irq(slot, AUPCMCIA_IRQ_CARD); 249 sp->as_status_irq = md->am_slot_irq(slot, 250 AUPCMCIA_IRQ_INSERT); 251 252 au_himem_space_init(&sp->as_attrt, "pcmciaattr", 253 PCMCIA_BASE + sp->as_offset + AUPCMCIA_ATTR_OFFSET, 254 0, AUPCMCIA_MAP_SIZE, AU_HIMEM_SPACE_LITTLE_ENDIAN); 255 256 au_himem_space_init(&sp->as_memt, "pcmciamem", 257 PCMCIA_BASE + sp->as_offset + AUPCMCIA_MEM_OFFSET, 258 0, AUPCMCIA_MAP_SIZE, AU_HIMEM_SPACE_LITTLE_ENDIAN); 259 260 au_himem_space_init(&sp->as_iot, "pcmciaio", 261 PCMCIA_BASE + sp->as_offset + AUPCMCIA_IO_OFFSET, 262 0, AUPCMCIA_MAP_SIZE, 263 AU_HIMEM_SPACE_LITTLE_ENDIAN | AU_HIMEM_SPACE_IO); 264 265 sp->as_status = 0; 266 267 paa.paa_busname = "pcmcia"; 268 paa.pct = sc->sc_pct; 269 paa.pch = (pcmcia_chipset_handle_t)sp; 270 271 sp->as_pcmcia = config_found(&sc->sc_dev, &paa, aupcm_print); 272 273 /* if no pcmcia, make sure slot is powered down */ 274 if (sp->as_pcmcia == NULL) { 275 aupcm_slot_disable(sp); 276 continue; 277 } 278 279 /* this makes sure we probe the slot */ 280 sc->sc_wake |= (1 << slot); 281 } 282 283 /* 284 * XXX: this would be an excellent time time to establish a handler 285 * for the card insertion interrupt, but that's edge triggered, and 286 * au_icu.c won't support it right now. We poll in the event thread 287 * for now. Start by initializing it now. 288 */ 289 if (kthread_create(PRI_NONE, 0, NULL, aupcm_event_thread, sc, 290 &sc->sc_thread, "%s", sc->sc_dev.dv_xname) != 0) 291 panic("%s: unable to create event kthread", 292 sc->sc_dev.dv_xname); 293 } 294 295 int 296 aupcm_print(void *aux, const char *pnp) 297 { 298 struct pcmciabus_attach_args *paa = aux; 299 struct aupcm_slot *sp = paa->pch; 300 301 printf(" socket %d irq %d, %s", sp->as_slot, sp->as_card_irq, 302 sp->as_name); 303 304 return (UNCONF); 305 } 306 307 void * 308 aupcm_intr_establish(pcmcia_chipset_handle_t pch, 309 struct pcmcia_function *pf, int level, int (*handler)(void *), void *arg) 310 { 311 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 312 int s; 313 314 /* 315 * Hmm. perhaps this intr should be a list. well, PCMCIA 316 * devices generally only have one interrupt, and so should 317 * generally have only one handler. So we leave it for now. 318 * (Other PCMCIA bus drivers do it this way.) 319 */ 320 sp->as_intr = handler; 321 sp->as_intrarg = arg; 322 sp->as_softint = softint_establish(IPL_SOFTNET, aupcm_softintr, sp); 323 324 /* set up hard interrupt handler for the card IRQs */ 325 s = splhigh(); 326 sp->as_hardint = au_intr_establish(sp->as_card_irq, 0, 327 IPL_TTY, IST_LEVEL_LOW, aupcm_card_intr, sp); 328 /* if card is not powered up, then leave the IRQ masked */ 329 if (!sp->as_enabled) { 330 au_intr_disable(sp->as_card_irq); 331 } 332 splx(s); 333 334 return (sp->as_softint); 335 } 336 337 void 338 aupcm_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 339 { 340 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 341 342 KASSERT(sp->as_softint == ih); 343 /* KASSERT(sp->as_hardint); */ 344 /* set up hard interrupt handler for the card IRQs */ 345 346 au_intr_disestablish(sp->as_hardint); 347 sp->as_hardint = 0; 348 349 softint_disestablish(ih); 350 sp->as_softint = 0; 351 sp->as_intr = NULL; 352 sp->as_intrarg = NULL; 353 } 354 355 /* 356 * FYI: Hot detach of PCMCIA is supposedly safe because H/W doesn't 357 * fault on accesses to missing hardware. 358 */ 359 void 360 aupcm_event_thread(void *arg) 361 { 362 struct aupcm_softc *sc = arg; 363 struct aupcm_slot *sp; 364 int s, i, attach, detach; 365 366 for (;;) { 367 s = splhigh(); 368 if (sc->sc_wake == 0) { 369 splx(s); 370 /* 371 * XXX: Currently, the au_icu.c lacks support 372 * for edge-triggered interrupts. So we 373 * cannot really use the status change 374 * inerrupts. For now we poll (once per sec). 375 * FYI, Linux does it this way, and they *do* 376 * have support for edge triggered interrupts. 377 * Go figure. 378 */ 379 tsleep(&sc->sc_wake, PWAIT, "aupcm_event", hz); 380 } 381 sc->sc_wake = 0; 382 383 attach = detach = 0; 384 for (i = 0; i < sc->sc_nslots; i++) { 385 sp = &sc->sc_slots[i]; 386 387 if (sc->sc_slot_status(sp->as_slot) != 0) { 388 if (!sp->as_status) { 389 DPRINTF(("%s: card %d insertion\n", 390 sc->sc_dev.dv_xname, i)); 391 attach |= (1 << i); 392 sp->as_status = 1; 393 } 394 } else { 395 if (sp->as_status) { 396 DPRINTF(("%s: card %d removal\n", 397 sc->sc_dev.dv_xname, i)); 398 detach |= (1 << i); 399 sp->as_status = 0; 400 } 401 } 402 } 403 splx(s); 404 405 for (i = 0; i < sc->sc_nslots; i++) { 406 sp = &sc->sc_slots[i]; 407 408 if (detach & (1 << i)) { 409 aupcm_slot_disable(sp); 410 pcmcia_card_detach(sp->as_pcmcia, 411 DETACH_FORCE); 412 } else if (attach & (1 << i)) { 413 /* 414 * until the function is enabled, don't 415 * honor interrupts 416 */ 417 sp->as_enabled = 0; 418 au_intr_disable(sp->as_card_irq); 419 pcmcia_card_attach(sp->as_pcmcia); 420 } 421 } 422 } 423 } 424 425 #if 0 426 void 427 aupcm_status_intr(void *arg) 428 { 429 int s; 430 struct aupcm_softc *sc = arg; 431 432 s = splhigh(); 433 434 /* kick the status thread so it does its bit */ 435 sc->sc_wake = 1; 436 wakeup(&sc->sc_wake); 437 438 splx(s); 439 } 440 #endif 441 442 int 443 aupcm_card_intr(void *arg) 444 { 445 struct aupcm_slot *sp = arg; 446 447 /* disable the hard interrupt for now */ 448 au_intr_disable(sp->as_card_irq); 449 450 if (sp->as_intr != NULL) { 451 softint_schedule(sp->as_softint); 452 } 453 454 return 1; 455 } 456 457 void 458 aupcm_softintr(void *arg) 459 { 460 struct aupcm_slot *sp = arg; 461 int s; 462 463 sp->as_intr(sp->as_intrarg); 464 465 s = splhigh(); 466 467 if (sp->as_intr && sp->as_enabled) { 468 au_intr_enable(sp->as_card_irq); 469 } 470 471 splx(s); 472 } 473 474 void 475 aupcm_slot_enable(pcmcia_chipset_handle_t pch) 476 { 477 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 478 int s; 479 480 /* no interrupts while we reset the card, please */ 481 if (sp->as_intr) 482 au_intr_disable(sp->as_card_irq); 483 484 /* 485 * XXX: should probably lock to make sure slot_disable and 486 * enable not called together. However, i believe that the 487 * event thread basically serializes them anyway. 488 */ 489 490 sp->as_softc->sc_slot_enable(sp->as_slot); 491 /* card is powered up now, honor device interrupts */ 492 493 s = splhigh(); 494 sp->as_enabled = 1; 495 if (sp->as_intr) 496 au_intr_enable(sp->as_card_irq); 497 splx(s); 498 } 499 500 void 501 aupcm_slot_disable(pcmcia_chipset_handle_t pch) 502 { 503 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 504 int s; 505 506 s = splhigh(); 507 au_intr_disable(sp->as_card_irq); 508 sp->as_enabled = 0; 509 splx(s); 510 511 sp->as_softc->sc_slot_disable(sp->as_slot); 512 } 513 514 void 515 aupcm_slot_settype(pcmcia_chipset_handle_t pch, int type) 516 { 517 /* we do nothing now : type == PCMCIA_IFTYPE_IO */ 518 } 519 520 int 521 aupcm_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 522 struct pcmcia_mem_handle *pcmh) 523 { 524 pcmh->memt = NULL; 525 pcmh->size = pcmh->realsize = size; 526 pcmh->addr = 0; 527 pcmh->mhandle = 0; 528 529 return 0; 530 } 531 532 void 533 aupcm_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmh) 534 { 535 /* nothing to do */ 536 } 537 538 int 539 aupcm_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t addr, 540 bus_size_t size, struct pcmcia_mem_handle *pcmh, bus_size_t *offsetp, 541 int *windowp) 542 { 543 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 544 int win, err; 545 int s; 546 547 s = splhigh(); 548 for (win = 0; win < AUPCMCIA_NWINS; win++) { 549 if (sp->as_wins[win] == NULL) { 550 sp->as_wins[win] = pcmh; 551 break; 552 } 553 } 554 splx(s); 555 556 if (win >= AUPCMCIA_NWINS) { 557 return ENOMEM; 558 } 559 560 if (kind & PCMCIA_MEM_ATTR) { 561 pcmh->memt = &sp->as_attrt; 562 NOISY(("mapping ATTR addr %x size %x\n", (uint32_t)addr, 563 (uint32_t)size)); 564 } else { 565 pcmh->memt = &sp->as_memt; 566 NOISY(("mapping MEMORY addr %x size %x\n", (uint32_t)addr, 567 (uint32_t)size)); 568 } 569 570 if ((size + addr) > (64 * 1024 * 1024)) 571 return EINVAL; 572 573 pcmh->size = size; 574 575 err = bus_space_map(pcmh->memt, addr, size, 0, &pcmh->memh); 576 if (err != 0) { 577 sp->as_wins[win] = NULL; 578 return err; 579 } 580 *offsetp = 0; 581 *windowp = win; 582 583 return 0; 584 } 585 586 void 587 aupcm_mem_unmap(pcmcia_chipset_handle_t pch, int win) 588 { 589 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 590 struct pcmcia_mem_handle *pcmh; 591 592 pcmh = (struct pcmcia_mem_handle *)sp->as_wins[win]; 593 sp->as_wins[win] = NULL; 594 595 NOISY(("memory umap virtual %x\n", (uint32_t)pcmh->memh)); 596 bus_space_unmap(pcmh->memt, pcmh->memh, pcmh->size); 597 pcmh->memt = NULL; 598 } 599 600 int 601 aupcm_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 602 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pih) 603 { 604 struct aupcm_slot *sp = (struct aupcm_slot *)pch; 605 bus_space_handle_t bush; 606 int err; 607 608 pih->iot = &sp->as_iot; 609 pih->size = size; 610 pih->flags = 0; 611 612 /* 613 * start from the initial offset - this gets us a slot 614 * specific address, while still leaving the addresses more or 615 * less zero-based which is required for x86-style device 616 * drivers. 617 */ 618 err = bus_space_alloc(pih->iot, start, 0x100000, 619 size, align, 0, 0, &pih->addr, &bush); 620 NOISY(("start = %x, addr = %x, size = %x, bush = %x\n", 621 (uint32_t)start, (uint32_t)pih->addr, (uint32_t)size, 622 (uint32_t)bush)); 623 624 /* and we convert it back */ 625 if (err == 0) { 626 pih->ihandle = (void *)bush; 627 } 628 629 return (err); 630 } 631 632 void 633 aupcm_io_free(pcmcia_chipset_handle_t pch, struct pcmcia_io_handle *pih) 634 { 635 bus_space_free(pih->iot, (bus_space_handle_t)pih->ihandle, 636 pih->size); 637 } 638 639 int 640 aupcm_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, 641 bus_size_t size, struct pcmcia_io_handle *pih, int *windowp) 642 { 643 int err; 644 645 err = bus_space_subregion(pih->iot, (bus_space_handle_t)pih->ihandle, 646 offset, size, &pih->ioh); 647 NOISY(("io map offset = %x, size = %x, ih = %x, hdl=%x\n", 648 (uint32_t)offset, (uint32_t)size, 649 (uint32_t)pih->ihandle, (uint32_t)pih->ioh)); 650 651 return err; 652 } 653 654 void 655 aupcm_io_unmap(pcmcia_chipset_handle_t pch, int win) 656 { 657 /* We mustn't unmap/free subregion bus space! */ 658 NOISY(("io unmap\n")); 659 } 660