1 /* $NetBSD: aupci.c,v 1.1 2006/02/09 00:26:40 gdamore Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_pci.h" 35 #include "pci.h" 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: aupci.c,v 1.1 2006/02/09 00:26:40 gdamore Exp $"); 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/time.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/extent.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/cpu.h> 53 #include <machine/pte.h> 54 #include <machine/wired_map.h> 55 56 #include <dev/pci/pcivar.h> 57 #include <dev/pci/pcireg.h> 58 #include <dev/pci/pciconf.h> 59 60 #ifdef PCI_NETBSD_CONFIGURE 61 #include <mips/cache.h> 62 #endif 63 64 #include <mips/alchemy/include/au_wired_space.h> 65 #include <mips/alchemy/include/aubusvar.h> 66 #include <mips/alchemy/include/aureg.h> 67 #include <mips/alchemy/include/auvar.h> 68 69 #include <mips/alchemy/dev/aupcireg.h> 70 #include <mips/alchemy/dev/aupcivar.h> 71 72 struct aupci_softc { 73 struct device sc_dev; 74 struct mips_pci_chipset sc_pc; 75 struct mips_bus_space sc_mem_space; 76 struct mips_bus_space sc_io_space; 77 78 bus_space_tag_t sc_memt; 79 bus_space_tag_t sc_iot; 80 81 bus_space_tag_t sc_bust; 82 83 bus_space_handle_t sc_bush; 84 vaddr_t sc_cfgva; 85 paddr_t sc_cfgpa; 86 paddr_t sc_cfgbase; 87 paddr_t sc_membase; 88 paddr_t sc_iobase; 89 90 /* XXX: dma tag */ 91 }; 92 93 int aupcimatch(struct device *, struct cfdata *, void *); 94 void aupciattach(struct device *, struct device *, void *); 95 96 #if NPCI > 0 97 static void aupci_attach_hook(struct device *, struct device *, 98 struct pcibus_attach_args *); 99 static int aupci_bus_maxdevs(void *, int); 100 static pcitag_t aupci_make_tag(void *, int, int, int); 101 static void aupci_decompose_tag(void *, pcitag_t, int *, int *, int *); 102 static pcireg_t aupci_conf_read(void *, pcitag_t, int); 103 static void aupci_conf_write(void *, pcitag_t, int, pcireg_t); 104 static const char *aupci_intr_string(void *, pci_intr_handle_t); 105 static void aupci_conf_interrupt(void *, int, int, int, int, int *); 106 static void *aupci_intr_establish(void *, pci_intr_handle_t, int, 107 int (*)(void *), void *); 108 static void aupci_intr_disestablish(void *, void *); 109 110 #ifdef PCI_NETBSD_CONFIGURE 111 static struct extent *io_ex = NULL; 112 static struct extent *mem_ex = NULL; 113 #endif /* PCI_NETBSD_CONFIGURE */ 114 115 #define PCI_CFG_READ 0 116 #define PCI_CFG_WRITE 1 117 118 #endif /* NPCI > 0 */ 119 120 CFATTACH_DECL(aupci, sizeof(struct aupci_softc), 121 aupcimatch, aupciattach, NULL, NULL); 122 123 int aupci_found = 0; 124 125 /* 126 * Physical PCI addresses are 36-bits long, so we need to have 127 * adequate storage space for them. 128 */ 129 #if NPCI > 0 130 #if !defined(_MIPS_PADDR_T_64BIT) && !defined(_LP64) 131 #error "aupci requires 64 bit paddr_t!" 132 #endif 133 #endif 134 135 int 136 aupcimatch(struct device *parent, struct cfdata *match, void *aux) 137 { 138 struct aubus_attach_args *aa = (struct aubus_attach_args *)aux; 139 140 if (strcmp(aa->aa_name, "aupci") != 0) 141 return 0; 142 143 if (aupci_found) 144 return 0; 145 146 return 1; 147 } 148 149 void 150 aupciattach(struct device *parent, struct device *self, void *aux) 151 { 152 struct aupci_softc *sc = (struct aupci_softc *)self; 153 struct aubus_attach_args *aa = (struct aubus_attach_args *)aux; 154 uint32_t cfg; 155 #if NPCI > 0 156 struct pcibus_attach_args pba; 157 #endif 158 159 aupci_found = 1; 160 161 sc->sc_bust = aa->aa_st; 162 if (bus_space_map(sc->sc_bust, aa->aa_addrs[0], 512, 0, 163 &sc->sc_bush) != 0) { 164 printf("\n%s: unable to map PCI registers\n", 165 sc->sc_dev.dv_xname); 166 return; 167 } 168 169 #if NPCI > 0 170 /* 171 * XXX: These physical addresses are locked in on the CPUs we have 172 * seen. Perhaps these should be passed in via locators, thru 173 * the configuration file. 174 */ 175 sc->sc_cfgbase = PCI_CONFIG_BASE; 176 sc->sc_membase = PCI_MEM_BASE; 177 sc->sc_iobase = PCI_IO_BASE; 178 179 /* 180 * We cannot map all of configuration space, because of the IDSEL 181 * logic. So we create a single entry and reuse it. For now we 182 * just map it to the start of configuration space, though we 183 * will be "adjusting" this for subsequent accesses later. 184 */ 185 sc->sc_cfgpa = 0; 186 sc->sc_cfgva = AU_PCI_CFG_VA; 187 #endif 188 189 /* 190 * Configure byte swapping, as YAMON doesn't do it. YAMON does take 191 * care of most of the rest of the details (clocking, etc.), however. 192 */ 193 #if _BYTE_ORDER == _BIG_ENDIAN 194 /* 195 * N.B.: This still doesn't do the DMA thing properly. I have 196 * not yet figured out how to get DMA access to work properly 197 * without having bytes swapped while the processor is in 198 * big-endian mode. I'm not even sure that the Alchemy part 199 * can do it without swapping the bytes (which would be a 200 * bummer, since then only parts which had hardware detection 201 * and swapping support would work without special hacks in 202 * their drivers.) 203 */ 204 cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H | 205 AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN | 206 AUPCI_CONFIG_SM | AUPCI_CONFIG_ST | AUPCI_CONFIG_SIC_DATA; 207 #else 208 cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H | 209 AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN; 210 #endif 211 bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, cfg); 212 213 cfg = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_COMMAND_STATUS); 214 215 printf(": Alchemy Host-PCI Bridge"); 216 if (cfg & PCI_STATUS_66MHZ_SUPPORT) 217 printf(", 66MHz"); 218 else 219 printf(", 33MHz"); 220 221 222 printf("\n"); 223 224 #if NPCI > 0 225 /* 226 * 256MB virtual PCI memory. Note that we probably cannot 227 * really use all this because of limits on the number wired 228 * entries we can have at once. In all likelihood, we won't 229 * use wired entries for more than a few megs anyway, since 230 * big devices like framebuffers are likely to be mapped into 231 * USEG using ordinary TLB entries. 232 */ 233 sc->sc_memt = &sc->sc_mem_space; 234 au_wired_space_init(sc->sc_memt, "pcimem", 235 sc->sc_membase | AU_PCI_MEM_VA, AU_PCI_MEM_VA, AU_PCI_MEM_SZ, 236 AU_WIRED_SPACE_LITTLE_ENDIAN /* | AU_WIRED_SPACE_SWAP_HW */); 237 238 /* 239 * IO space. 240 */ 241 sc->sc_iot = &sc->sc_io_space; 242 au_wired_space_init(sc->sc_iot, "pciio", 243 sc->sc_iobase | AU_PCI_IO_VA, AU_PCI_IO_VA, AU_PCI_IO_SZ, 244 AU_WIRED_SPACE_LITTLE_ENDIAN | /* AU_WIRED_SPACE_SWAP_HW | */ 245 AU_WIRED_SPACE_IO); 246 247 sc->sc_pc.pc_conf_v = sc; 248 sc->sc_pc.pc_attach_hook = aupci_attach_hook; 249 sc->sc_pc.pc_bus_maxdevs = aupci_bus_maxdevs; 250 sc->sc_pc.pc_make_tag = aupci_make_tag; 251 sc->sc_pc.pc_decompose_tag = aupci_decompose_tag; 252 sc->sc_pc.pc_conf_read = aupci_conf_read; 253 sc->sc_pc.pc_conf_write = aupci_conf_write; 254 255 sc->sc_pc.pc_intr_v = sc; 256 sc->sc_pc.pc_intr_map = aupci_intr_map; 257 sc->sc_pc.pc_intr_string = aupci_intr_string; 258 sc->sc_pc.pc_intr_establish = aupci_intr_establish; 259 sc->sc_pc.pc_intr_disestablish = aupci_intr_disestablish; 260 sc->sc_pc.pc_conf_interrupt = aupci_conf_interrupt; 261 262 #ifdef PCI_NETBSD_CONFIGURE 263 mem_ex = extent_create("pcimem", AU_PCI_MEM_VA, 264 AU_PCI_MEM_VA + AU_PCI_MEM_SZ - 1, M_DEVBUF, NULL, 0, EX_WAITOK); 265 io_ex = extent_create("pciio", AU_PCI_IO_VA, 266 AU_PCI_IO_VA + AU_PCI_IO_SZ - 1, M_DEVBUF, NULL, 0, EX_WAITOK); 267 pci_configure_bus(&sc->sc_pc, 268 io_ex, mem_ex, NULL, 0, mips_dcache_align); 269 extent_destroy(mem_ex); 270 extent_destroy(io_ex); 271 #endif 272 273 pba.pba_iot = sc->sc_iot; 274 pba.pba_memt = sc->sc_memt; 275 /* XXX: review dma tag logic */ 276 pba.pba_dmat = aa->aa_dt; 277 pba.pba_dmat64 = NULL; 278 pba.pba_pc = &sc->sc_pc; 279 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 280 pba.pba_bus = 0; 281 pba.pba_bridgetag = NULL; 282 283 config_found_ia(self, "pcibus", &pba, pcibusprint); 284 #endif /* NPCI > 0 */ 285 } 286 287 #if NPCI > 0 288 289 void 290 aupci_attach_hook(struct device *parent, struct device *self, 291 struct pcibus_attach_args *pba) 292 { 293 } 294 295 int 296 aupci_bus_maxdevs(void *v, int busno) 297 { 298 299 return 32; 300 } 301 302 pcitag_t 303 aupci_make_tag(void *v, int bus, int device, int function) 304 { 305 pcitag_t tag; 306 307 if (bus >= 256 || device >= 32 || function >= 8) 308 panic("aupci_make_tag: bad request"); 309 310 tag = (bus << 16) | (device << 11) | (function << 8); 311 312 return tag; 313 } 314 315 void 316 aupci_decompose_tag(void *v, pcitag_t tag, int *b, int *d, int *f) 317 { 318 319 if (b != NULL) 320 *b = (tag >> 16) & 0xff; 321 if (d != NULL) 322 *d = (tag >> 11) & 0x1f; 323 if (f != NULL) 324 *f = (tag >> 8) & 0x07; 325 } 326 327 /* 328 * Figure out the configuration space physical address for a given 329 * tag, taking into consideration the IDSEL logic on bus 0. 330 */ 331 static inline paddr_t 332 aupci_conf_tag_to_pa(void *v, pcitag_t tag) 333 { 334 uint32_t offset; 335 int b, d, f; 336 struct aupci_softc *sc = (struct aupci_softc *)v; 337 338 aupci_decompose_tag(v, tag, &b, &d, &f); 339 if (b) { 340 /* configuration type 1 */ 341 offset = 0x80000000 | tag; 342 } else if (d > 19) { 343 /* device num too big for bus 0 */ 344 return 0; 345 } else { 346 offset = (0x800 << d) | (f << 8); 347 } 348 return (sc->sc_cfgbase + offset); 349 } 350 351 static inline boolean_t 352 aupci_conf_access(void *v, int dir, pcitag_t tag, int reg, pcireg_t *datap) 353 { 354 uint32_t status; 355 int s; 356 vsize_t off; 357 paddr_t pa; 358 struct aupci_softc *sc = (struct aupci_softc *)v; 359 360 pa = aupci_conf_tag_to_pa(v, tag); 361 /* probing illegal target is OK, return an error indication */ 362 if (pa == 0) 363 return FALSE; 364 365 /* align it down to start of phys addr */ 366 off = pa & (MIPS3_WIRED_SIZE - 1); 367 pa -= off; 368 369 s = splhigh(); 370 371 if (sc->sc_cfgpa != pa) { 372 if (mips3_wired_enter_region(sc->sc_cfgva, pa, 373 MIPS3_WIRED_SIZE) == FALSE) { 374 printf("%s: cannot map PCI configuration space!\n", 375 sc->sc_dev.dv_xname); 376 splx(s); 377 return FALSE; 378 } 379 sc->sc_cfgpa = pa; 380 } 381 382 /* 383 * Note that configuration space accesses are *always* endian 384 * swapped properly by the processor. 385 */ 386 if (dir == PCI_CFG_WRITE) 387 *(volatile pcireg_t *)(sc->sc_cfgva + off + reg) = *datap; 388 else 389 *datap = *(volatile pcireg_t *)(sc->sc_cfgva + off + reg); 390 391 DELAY(2); 392 393 /* check for and clear master abort condition */ 394 status = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG); 395 bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, 396 status & ~(AUPCI_CONFIG_EF)); 397 398 /* if we got a PCI master abort, fail it */ 399 if (status & AUPCI_CONFIG_EF) 400 return FALSE; 401 402 splx(s); 403 404 return TRUE; 405 } 406 407 408 pcireg_t 409 aupci_conf_read(void *v, pcitag_t tag, int reg) 410 { 411 pcireg_t data; 412 413 if (aupci_conf_access(v, PCI_CFG_READ, tag, reg, &data) == FALSE) 414 return 0xffffffff; 415 416 return (data); 417 } 418 419 void 420 aupci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 421 { 422 423 aupci_conf_access(v, PCI_CFG_WRITE, tag, reg, &data); 424 } 425 426 const char * 427 aupci_intr_string(void *v, pci_intr_handle_t ih) 428 { 429 static char name[16]; 430 431 sprintf(name, "irq %u", (unsigned)ih); 432 return (name); 433 } 434 435 void * 436 aupci_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 437 int (*handler)(void *), void *arg) 438 { 439 440 return (au_intr_establish(ih, 0, ipl, IST_LEVEL_LOW, handler, arg)); 441 } 442 443 void 444 aupci_intr_disestablish(void *v, void *cookie) 445 { 446 447 au_intr_disestablish(cookie); 448 } 449 450 void 451 aupci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 452 { 453 /* 454 * We let the machdep_pci_intr_map take care of IRQ routing. 455 * On some platforms the BIOS may have handled this properly, 456 * on others it might not have. For now we avoid clobbering 457 * the settings establishsed by the BIOS, so that they will be 458 * there if the platform logic is confident that it can rely 459 * on them. 460 */ 461 } 462 463 #endif 464