1 /* $NetBSD: aupci.c,v 1.20 2021/08/07 16:18:58 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include "opt_pci.h" 35 #include "pci.h" 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: aupci.c,v 1.20 2021/08/07 16:18:58 thorpej Exp $"); 39 40 #include <sys/types.h> 41 #include <sys/param.h> 42 #include <sys/time.h> 43 #include <sys/systm.h> 44 #include <sys/errno.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/bus.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <mips/locore.h> 52 #include <mips/pte.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pciconf.h> 57 58 #ifdef PCI_NETBSD_CONFIGURE 59 #include <mips/cache.h> 60 #endif 61 62 #include <mips/alchemy/include/au_himem_space.h> 63 #include <mips/alchemy/include/aubusvar.h> 64 #include <mips/alchemy/include/aureg.h> 65 #include <mips/alchemy/include/auvar.h> 66 67 #include <mips/alchemy/dev/aupcireg.h> 68 #include <mips/alchemy/dev/aupcivar.h> 69 70 struct aupci_softc { 71 device_t sc_dev; 72 struct mips_pci_chipset sc_pc; 73 struct mips_bus_space sc_mem_space; 74 struct mips_bus_space sc_io_space; 75 struct mips_bus_space sc_cfg_space; 76 77 bus_space_tag_t sc_memt; 78 bus_space_tag_t sc_iot; 79 bus_space_tag_t sc_cfgt; 80 81 bus_space_tag_t sc_bust; 82 83 bus_space_handle_t sc_bush; 84 paddr_t sc_cfgbase; 85 paddr_t sc_membase; 86 paddr_t sc_iobase; 87 88 /* XXX: dma tag */ 89 }; 90 91 int aupcimatch(device_t, struct cfdata *, void *); 92 void aupciattach(device_t, device_t, void *); 93 94 #if NPCI > 0 95 static void aupci_attach_hook(device_t, device_t, struct pcibus_attach_args *); 96 static int aupci_bus_maxdevs(void *, int); 97 static pcitag_t aupci_make_tag(void *, int, int, int); 98 static void aupci_decompose_tag(void *, pcitag_t, int *, int *, int *); 99 static pcireg_t aupci_conf_read(void *, pcitag_t, int); 100 static void aupci_conf_write(void *, pcitag_t, int, pcireg_t); 101 static const char *aupci_intr_string(void *, pci_intr_handle_t, char *, size_t); 102 static void aupci_conf_interrupt(void *, int, int, int, int, int *); 103 static void *aupci_intr_establish(void *, pci_intr_handle_t, int, 104 int (*)(void *), void *); 105 static void aupci_intr_disestablish(void *, void *); 106 107 #define PCI_CFG_READ 0 108 #define PCI_CFG_WRITE 1 109 110 #define PCI_IO_START AUPCI_IO_START 111 #define PCI_IO_END AUPCI_IO_END 112 #define PCI_IO_SIZE ((PCI_IO_END - PCI_IO_START) + 1) 113 114 #define PCI_MEM_END 0xffffffff 115 #define PCI_MEM_SIZE(m) ((PCI_MEM_END - (m)) + 1) 116 117 #endif /* NPCI > 0 */ 118 119 CFATTACH_DECL_NEW(aupci, sizeof(struct aupci_softc), 120 aupcimatch, aupciattach, NULL, NULL); 121 122 int aupci_found = 0; 123 124 /* 125 * Physical PCI addresses are 36-bits long, so we need to have 126 * adequate storage space for them. 127 */ 128 #if NPCI > 0 129 #if !defined(_MIPS_PADDR_T_64BIT) && !defined(_LP64) 130 #error "aupci requires 64 bit paddr_t!" 131 #endif 132 #endif 133 134 int 135 aupcimatch(device_t parent, struct cfdata *match, void *aux) 136 { 137 struct aubus_attach_args *aa = (struct aubus_attach_args *)aux; 138 139 if (strcmp(aa->aa_name, "aupci") != 0) 140 return 0; 141 142 if (aupci_found) 143 return 0; 144 145 return 1; 146 } 147 148 void 149 aupciattach(device_t parent, device_t self, void *aux) 150 { 151 struct aupci_softc *sc = device_private(self); 152 struct aubus_attach_args *aa = (struct aubus_attach_args *)aux; 153 uint32_t cfg; 154 #if NPCI > 0 155 uint32_t mbar, mask; 156 bus_addr_t mstart; 157 struct pcibus_attach_args pba; 158 #endif 159 160 aupci_found = 1; 161 162 sc->sc_dev = self; 163 sc->sc_bust = aa->aa_st; 164 if (bus_space_map(sc->sc_bust, aa->aa_addrs[0], 512, 0, 165 &sc->sc_bush) != 0) { 166 aprint_error(": unable to map PCI registers\n"); 167 return; 168 } 169 170 #if NPCI > 0 171 /* 172 * These physical addresses are locked in on the CPUs we have 173 * seen. Perhaps these should be passed in via locators, thru 174 * the configuration file. 175 */ 176 sc->sc_cfgbase = PCI_CONFIG_BASE; 177 sc->sc_membase = PCI_MEM_BASE; 178 sc->sc_iobase = PCI_IO_BASE; 179 #endif 180 181 /* 182 * Configure byte swapping, as YAMON doesn't do it. YAMON does take 183 * care of most of the rest of the details (clocking, etc.), however. 184 */ 185 #if _BYTE_ORDER == _BIG_ENDIAN 186 /* 187 * N.B.: This still doesn't do the DMA thing properly. I have 188 * not yet figured out how to get DMA access to work properly 189 * without having bytes swapped while the processor is in 190 * big-endian mode. I'm not even sure that the Alchemy part 191 * can do it without swapping the bytes (which would be a 192 * bummer, since then only parts which had hardware detection 193 * and swapping support would work without special hacks in 194 * their drivers.) 195 */ 196 cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H | 197 AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN | 198 AUPCI_CONFIG_SM | AUPCI_CONFIG_ST | AUPCI_CONFIG_SIC_DATA; 199 #else 200 cfg = AUPCI_CONFIG_CH | AUPCI_CONFIG_R1H | 201 AUPCI_CONFIG_R2H | AUPCI_CONFIG_AEN; 202 #endif 203 bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, cfg); 204 205 cfg = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_COMMAND_STATUS); 206 207 aprint_normal(": Alchemy Host-PCI Bridge, %sMHz\n", 208 (cfg & PCI_STATUS_66MHZ_SUPPORT) ? "66" : "33"); 209 aprint_naive("\n"); 210 211 #if NPCI > 0 212 /* 213 * PCI configuration space. Address in this bus are 214 * orthogonal to other spaces. We need to make the entire 215 * 32-bit address space available. 216 */ 217 sc->sc_cfgt = &sc->sc_cfg_space; 218 au_himem_space_init(sc->sc_cfgt, "pcicfg", sc->sc_cfgbase, 219 0x00000000, 0xffffffff, AU_HIMEM_SPACE_IO); 220 221 /* 222 * Virtual PCI memory. Configured so that we don't overlap 223 * with PCI memory space. 224 */ 225 mask = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MWMASK); 226 mask >>= AUPCI_MWMASK_SHIFT; 227 mask <<= AUPCI_MWMASK_SHIFT; 228 229 mbar = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_MBAR); 230 mstart = (mbar & mask) + (~mask + 1); 231 232 sc->sc_memt = &sc->sc_mem_space; 233 au_himem_space_init(sc->sc_memt, "pcimem", sc->sc_membase, 234 mstart, 0xffffffff, AU_HIMEM_SPACE_LITTLE_ENDIAN); 235 236 /* 237 * IO space. Address in this bus are orthogonal to other spaces. 238 * 16 MB should be plenty. We don't start from zero to avoid 239 * potential device bugs. 240 */ 241 sc->sc_iot = &sc->sc_io_space; 242 au_himem_space_init(sc->sc_iot, "pciio", 243 sc->sc_iobase, AUPCI_IO_START, AUPCI_IO_END, 244 AU_HIMEM_SPACE_LITTLE_ENDIAN | AU_HIMEM_SPACE_IO); 245 246 sc->sc_pc.pc_conf_v = sc; 247 sc->sc_pc.pc_attach_hook = aupci_attach_hook; 248 sc->sc_pc.pc_bus_maxdevs = aupci_bus_maxdevs; 249 sc->sc_pc.pc_make_tag = aupci_make_tag; 250 sc->sc_pc.pc_decompose_tag = aupci_decompose_tag; 251 sc->sc_pc.pc_conf_read = aupci_conf_read; 252 sc->sc_pc.pc_conf_write = aupci_conf_write; 253 254 sc->sc_pc.pc_intr_v = sc; 255 sc->sc_pc.pc_intr_map = aupci_intr_map; 256 sc->sc_pc.pc_intr_string = aupci_intr_string; 257 sc->sc_pc.pc_intr_establish = aupci_intr_establish; 258 sc->sc_pc.pc_intr_disestablish = aupci_intr_disestablish; 259 sc->sc_pc.pc_conf_interrupt = aupci_conf_interrupt; 260 261 #ifdef PCI_NETBSD_CONFIGURE 262 struct pciconf_resources *pcires = pciconf_resource_init(); 263 264 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 265 PCI_IO_START, PCI_IO_SIZE); 266 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 267 mstart, PCI_MEM_SIZE(mstart)); 268 269 pci_configure_bus(&sc->sc_pc, pcires, 0, 270 mips_cache_info.mci_dcache_align); 271 pciconf_resource_fini(pcires); 272 #endif 273 274 pba.pba_iot = sc->sc_iot; 275 pba.pba_memt = sc->sc_memt; 276 /* XXX: review dma tag logic */ 277 pba.pba_dmat = aa->aa_dt; 278 pba.pba_dmat64 = NULL; 279 pba.pba_pc = &sc->sc_pc; 280 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 281 pba.pba_bus = 0; 282 pba.pba_bridgetag = NULL; 283 284 config_found(self, &pba, pcibusprint, CFARGS_NONE); 285 #endif /* NPCI > 0 */ 286 } 287 288 #if NPCI > 0 289 290 void 291 aupci_attach_hook(device_t parent, device_t self, 292 struct pcibus_attach_args *pba) 293 { 294 } 295 296 int 297 aupci_bus_maxdevs(void *v, int busno) 298 { 299 300 return 32; 301 } 302 303 pcitag_t 304 aupci_make_tag(void *v, int bus, int device, int function) 305 { 306 pcitag_t tag; 307 308 if (bus >= 256 || device >= 32 || function >= 8) 309 panic("aupci_make_tag: bad request"); 310 311 tag = (bus << 16) | (device << 11) | (function << 8); 312 313 return tag; 314 } 315 316 void 317 aupci_decompose_tag(void *v, pcitag_t tag, int *b, int *d, int *f) 318 { 319 320 if (b != NULL) 321 *b = (tag >> 16) & 0xff; 322 if (d != NULL) 323 *d = (tag >> 11) & 0x1f; 324 if (f != NULL) 325 *f = (tag >> 8) & 0x07; 326 } 327 328 static inline bool 329 aupci_conf_access(void *v, int dir, pcitag_t tag, int reg, pcireg_t *datap) 330 { 331 struct aupci_softc *sc = (struct aupci_softc *)v; 332 uint32_t status; 333 int s; 334 bus_addr_t addr; 335 int b, d, f; 336 bus_space_handle_t h; 337 338 if ((unsigned int)reg >= PCI_CONF_SIZE) 339 return false; 340 341 aupci_decompose_tag(v, tag, &b, &d, &f); 342 if (b) { 343 /* configuration type 1 */ 344 addr = 0x80000000 | tag; 345 } else if (d > 19) { 346 /* device num too big for bus 0 */ 347 return false; 348 } else { 349 addr = (0x800 << d) | (f << 8); 350 } 351 352 /* probing illegal target is OK, return an error indication */ 353 if (addr == 0) 354 return false; 355 356 if (bus_space_map(sc->sc_cfgt, addr, 256, 0, &h) != 0) 357 return false; 358 359 s = splhigh(); 360 361 if (dir == PCI_CFG_WRITE) 362 bus_space_write_4(sc->sc_cfgt, h, reg, *datap); 363 else 364 *datap = bus_space_read_4(sc->sc_cfgt, h, reg); 365 366 DELAY(2); 367 368 /* check for and clear master abort condition */ 369 status = bus_space_read_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG); 370 bus_space_write_4(sc->sc_bust, sc->sc_bush, AUPCI_CONFIG, 371 status & ~(AUPCI_CONFIG_EF)); 372 373 splx(s); 374 375 bus_space_unmap(sc->sc_cfgt, h, 256); 376 377 /* if we got a PCI master abort, fail it */ 378 if (status & AUPCI_CONFIG_EF) 379 return false; 380 381 return true; 382 } 383 384 pcireg_t 385 aupci_conf_read(void *v, pcitag_t tag, int reg) 386 { 387 pcireg_t data; 388 389 if (aupci_conf_access(v, PCI_CFG_READ, tag, reg, &data) == false) 390 return 0xffffffff; 391 392 return (data); 393 } 394 395 void 396 aupci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 397 { 398 399 aupci_conf_access(v, PCI_CFG_WRITE, tag, reg, &data); 400 } 401 402 const char * 403 aupci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 404 { 405 snprintf(buf, len, "irq %u", (unsigned)ih); 406 return buf; 407 } 408 409 void * 410 aupci_intr_establish(void *v, pci_intr_handle_t ih, int ipl, 411 int (*handler)(void *), void *arg) 412 { 413 414 return (au_intr_establish(ih, 0, ipl, IST_LEVEL_LOW, handler, arg)); 415 } 416 417 void 418 aupci_intr_disestablish(void *v, void *cookie) 419 { 420 421 au_intr_disestablish(cookie); 422 } 423 424 void 425 aupci_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *iline) 426 { 427 /* 428 * We let the machdep_pci_intr_map take care of IRQ routing. 429 * On some platforms the BIOS may have handled this properly, 430 * on others it might not have. For now we avoid clobbering 431 * the settings establishsed by the BIOS, so that they will be 432 * there if the platform logic is confident that it can rely 433 * on them. 434 */ 435 } 436 437 #endif 438