1 /* $NetBSD: au_icu.c,v 1.29 2012/01/14 16:09:19 kiyohara Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 2001 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs. 65 * 66 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal 67 * interrupt controllers. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.29 2012/01/14 16:09:19 kiyohara Exp $"); 72 73 #include "opt_ddb.h" 74 #define __INTR_PRIVATE 75 76 #include <sys/param.h> 77 #include <sys/bus.h> 78 #include <sys/device.h> 79 #include <sys/intr.h> 80 #include <sys/kernel.h> 81 #include <sys/malloc.h> 82 #include <sys/systm.h> 83 84 #include <mips/locore.h> 85 #include <mips/alchemy/include/aureg.h> 86 #include <mips/alchemy/include/auvar.h> 87 88 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 89 90 /* 91 * This is a mask of bits to clear in the SR when we go to a 92 * given hardware interrupt priority level. 93 */ 94 95 static const struct ipl_sr_map alchemy_ipl_sr_map = { 96 .sr_bits = { 97 [IPL_NONE] = 0, 98 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 99 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0, 100 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, 101 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK, 102 [IPL_VM] = MIPS_SOFT_INT_MASK | 103 MIPS_INT_MASK_0 | 104 MIPS_INT_MASK_1 | 105 MIPS_INT_MASK_2 | 106 MIPS_INT_MASK_3, 107 [IPL_SCHED] = MIPS_INT_MASK, 108 [IPL_DDB] = MIPS_INT_MASK, 109 [IPL_HIGH] = MIPS_INT_MASK, 110 }, 111 }; 112 113 #define NIRQS 64 114 115 struct au_icu_intrhead { 116 struct evcnt intr_count; 117 int intr_refcnt; 118 }; 119 struct au_icu_intrhead au_icu_intrtab[NIRQS]; 120 121 #define NINTRS 4 /* MIPS INT0 - INT3 */ 122 123 struct au_intrhand { 124 LIST_ENTRY(au_intrhand) ih_q; 125 int (*ih_func)(void *); 126 void *ih_arg; 127 int ih_irq; 128 int ih_mask; 129 }; 130 131 struct au_cpuintr { 132 LIST_HEAD(, au_intrhand) cintr_list; 133 struct evcnt cintr_count; 134 }; 135 136 struct au_cpuintr au_cpuintrs[NINTRS]; 137 const char * const au_cpuintrnames[NINTRS] = { 138 "icu 0, req 0", 139 "icu 0, req 1", 140 "icu 1, req 0", 141 "icu 1, req 1", 142 }; 143 144 static bus_addr_t ic0_base, ic1_base; 145 146 void 147 au_intr_init(void) 148 { 149 ipl_sr_map = alchemy_ipl_sr_map; 150 151 for (size_t i = 0; i < NINTRS; i++) { 152 LIST_INIT(&au_cpuintrs[i].cintr_list); 153 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count, 154 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]); 155 } 156 157 struct au_chipdep * const chip = au_chipdep(); 158 KASSERT(chip != NULL); 159 160 ic0_base = chip->icus[0]; 161 ic1_base = chip->icus[1]; 162 163 for (size_t i = 0; i < NIRQS; i++) { 164 au_icu_intrtab[i].intr_refcnt = 0; 165 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count, 166 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]); 167 } 168 169 /* start with all interrupts masked */ 170 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff; 171 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff; 172 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff; 173 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff; 174 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff; 175 REGVAL(ic0_base + IC_TEST_BIT) = 0; 176 177 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff; 178 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff; 179 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff; 180 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff; 181 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff; 182 REGVAL(ic1_base + IC_TEST_BIT) = 0; 183 } 184 185 void * 186 au_intr_establish(int irq, int req, int level, int type, 187 int (*func)(void *), void *arg) 188 { 189 struct au_intrhand *ih; 190 uint32_t icu_base; 191 int cpu_int, s; 192 struct au_chipdep *chip; 193 194 chip = au_chipdep(); 195 KASSERT(chip != NULL); 196 197 if (irq >= NIRQS) 198 panic("au_intr_establish: bogus IRQ %d", irq); 199 if (req > 1) 200 panic("au_intr_establish: bogus request %d", req); 201 202 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 203 if (ih == NULL) 204 return (NULL); 205 206 ih->ih_func = func; 207 ih->ih_arg = arg; 208 ih->ih_irq = irq; 209 ih->ih_mask = (1 << (irq & 31)); 210 211 s = splhigh(); 212 213 /* 214 * First, link it into the tables. 215 * XXX do we want a separate list (really, should only be one item, not 216 * a list anyway) per irq, not per CPU interrupt? 217 */ 218 cpu_int = (irq < 32 ? 0 : 2) + req; 219 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q); 220 221 /* 222 * Now enable it. 223 */ 224 if (au_icu_intrtab[irq].intr_refcnt++ == 0) { 225 icu_base = (irq < 32) ? ic0_base : ic1_base; 226 227 irq &= 31; /* throw away high bit if set */ 228 irq = 1 << irq; /* only used as a mask from here on */ 229 230 /* XXX Only level interrupts for now */ 231 switch (type) { 232 case IST_NONE: 233 case IST_PULSE: 234 case IST_EDGE: 235 panic("unsupported irq type %d", type); 236 /* NOTREACHED */ 237 case IST_LEVEL: 238 case IST_LEVEL_HIGH: 239 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 240 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 241 REGVAL(icu_base + IC_CONFIG0_SET) = irq; 242 break; 243 case IST_LEVEL_LOW: 244 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 245 REGVAL(icu_base + IC_CONFIG1_SET) = irq; 246 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 247 break; 248 } 249 wbflush(); 250 251 /* XXX handle GPIO interrupts - not done at all yet */ 252 if (cpu_int & 0x1) 253 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq; 254 else 255 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq; 256 257 /* Associate interrupt with peripheral */ 258 REGVAL(icu_base + IC_SOURCE_SET) = irq; 259 260 /* Actually enable the interrupt */ 261 REGVAL(icu_base + IC_MASK_SET) = irq; 262 263 /* And allow the interrupt to interrupt idle */ 264 REGVAL(icu_base + IC_WAKEUP_SET) = irq; 265 266 wbflush(); 267 } 268 splx(s); 269 270 return (ih); 271 } 272 273 void 274 au_intr_disestablish(void *cookie) 275 { 276 struct au_intrhand *ih = cookie; 277 uint32_t icu_base; 278 int irq, s; 279 280 irq = ih->ih_irq; 281 282 s = splhigh(); 283 284 /* 285 * First, remove it from the table. 286 */ 287 LIST_REMOVE(ih, ih_q); 288 289 /* 290 * Now, disable it, if there is nothing remaining on the 291 * list. 292 */ 293 if (au_icu_intrtab[irq].intr_refcnt-- == 1) { 294 icu_base = (irq < 32) ? ic0_base : ic1_base; 295 296 irq &= 31; /* throw away high bit if set */ 297 irq = 1 << irq; /* only used as a mask from here on */ 298 299 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq; 300 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 301 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 302 303 /* disable with MASK_CLEAR and WAKEUP_CLEAR */ 304 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 305 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq; 306 wbflush(); 307 } 308 309 splx(s); 310 311 free(ih, M_DEVBUF); 312 } 313 314 void 315 au_iointr(int ipl, vaddr_t pc, uint32_t ipending) 316 { 317 struct au_intrhand *ih; 318 int level; 319 uint32_t icu_base, irqstat, irqmask; 320 321 icu_base = irqstat = 0; 322 323 for (level = 3; level >= 0; level--) { 324 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 325 continue; 326 327 /* 328 * XXX the following may well be slow to execute. 329 * investigate and possibly speed up. 330 * 331 * is something like: 332 * 333 * irqstat = REGVAL( 334 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE + 335 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT); 336 * 337 * be any better? 338 * 339 */ 340 switch (level) { 341 case 0: 342 icu_base = ic0_base; 343 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 344 break; 345 case 1: 346 icu_base = ic0_base; 347 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 348 break; 349 case 2: 350 icu_base = ic1_base; 351 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 352 break; 353 case 3: 354 icu_base = ic1_base; 355 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 356 break; 357 } 358 irqmask = REGVAL(icu_base + IC_MASK_READ); 359 au_cpuintrs[level].cintr_count.ev_count++; 360 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) { 361 int mask = ih->ih_mask; 362 363 if (mask & irqmask & irqstat) { 364 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++; 365 (*ih->ih_func)(ih->ih_arg); 366 367 if (REGVAL(icu_base + IC_MASK_READ) & mask) { 368 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 369 REGVAL(icu_base + IC_MASK_SET) = mask; 370 wbflush(); 371 } 372 } 373 } 374 } 375 } 376 377 /* 378 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at 379 * the ICU, and leave them masked off until some later time 380 * (e.g. reenabled by a soft interrupt). 381 */ 382 383 void 384 au_intr_enable(int irq) 385 { 386 int s; 387 uint32_t icu_base, mask; 388 389 if (irq >= NIRQS) 390 panic("au_intr_enable: bogus IRQ %d", irq); 391 392 icu_base = (irq < 32) ? ic0_base : ic1_base; 393 mask = irq & 31; 394 mask = 1 << mask; 395 396 s = splhigh(); 397 /* only enable the interrupt if we have a handler */ 398 if (au_icu_intrtab[irq].intr_refcnt) { 399 REGVAL(icu_base + IC_MASK_SET) = mask; 400 REGVAL(icu_base + IC_WAKEUP_SET) = mask; 401 wbflush(); 402 } 403 splx(s); 404 } 405 406 void 407 au_intr_disable(int irq) 408 { 409 int s; 410 uint32_t icu_base, mask; 411 412 if (irq >= NIRQS) 413 panic("au_intr_disable: bogus IRQ %d", irq); 414 415 icu_base = (irq < 32) ? ic0_base : ic1_base; 416 mask = irq & 31; 417 mask = 1 << mask; 418 419 s = splhigh(); 420 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 421 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask; 422 wbflush(); 423 splx(s); 424 } 425