1 /* $NetBSD: au_icu.c,v 1.23 2008/04/28 20:23:27 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /*- 35 * Copyright (c) 2001 The NetBSD Foundation, Inc. 36 * All rights reserved. 37 * 38 * This code is derived from software contributed to The NetBSD Foundation 39 * by Jason R. Thorpe. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that the following conditions 43 * are met: 44 * 1. Redistributions of source code must retain the above copyright 45 * notice, this list of conditions and the following disclaimer. 46 * 2. Redistributions in binary form must reproduce the above copyright 47 * notice, this list of conditions and the following disclaimer in the 48 * documentation and/or other materials provided with the distribution. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 51 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 53 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 60 * POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63 /* 64 * Interrupt support for the Alchemy Semiconductor Au1x00 CPUs. 65 * 66 * The Alchemy Semiconductor Au1x00's interrupts are wired to two internal 67 * interrupt controllers. 68 */ 69 70 #include <sys/cdefs.h> 71 __KERNEL_RCSID(0, "$NetBSD: au_icu.c,v 1.23 2008/04/28 20:23:27 martin Exp $"); 72 73 #include "opt_ddb.h" 74 75 #include <sys/param.h> 76 #include <sys/queue.h> 77 #include <sys/malloc.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/kernel.h> 81 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <mips/locore.h> 86 #include <mips/alchemy/include/aureg.h> 87 #include <mips/alchemy/include/auvar.h> 88 89 #define REGVAL(x) *((volatile uint32_t *)(MIPS_PHYS_TO_KSEG1((x)))) 90 91 /* 92 * This is a mask of bits to clear in the SR when we go to a 93 * given hardware interrupt priority level. 94 */ 95 96 const uint32_t ipl_sr_bits[_IPL_N] = { 97 0, /* 0: IPL_NONE */ 98 MIPS_SOFT_INT_MASK_0, /* 1: IPL_SOFTCLOCK */ 99 MIPS_SOFT_INT_MASK_0, /* 2: IPL_SOFTNET */ 100 MIPS_SOFT_INT_MASK_0| 101 MIPS_SOFT_INT_MASK_1| 102 MIPS_INT_MASK_0, /* 3: IPL_VM */ 103 MIPS_SOFT_INT_MASK_0| 104 MIPS_SOFT_INT_MASK_1| 105 MIPS_INT_MASK_0| 106 MIPS_INT_MASK_1| 107 MIPS_INT_MASK_2| 108 MIPS_INT_MASK_3| 109 MIPS_INT_MASK_4| 110 MIPS_INT_MASK_5, /* 4: IPL_{SCHED,HIGH} */ 111 }; 112 113 #define NIRQS 64 114 115 struct au_icu_intrhead { 116 struct evcnt intr_count; 117 int intr_refcnt; 118 }; 119 struct au_icu_intrhead au_icu_intrtab[NIRQS]; 120 121 #define NINTRS 4 /* MIPS INT0 - INT3 */ 122 123 struct au_intrhand { 124 LIST_ENTRY(au_intrhand) ih_q; 125 int (*ih_func)(void *); 126 void *ih_arg; 127 int ih_irq; 128 int ih_mask; 129 }; 130 131 struct au_cpuintr { 132 LIST_HEAD(, au_intrhand) cintr_list; 133 struct evcnt cintr_count; 134 }; 135 136 struct au_cpuintr au_cpuintrs[NINTRS]; 137 const char *au_cpuintrnames[NINTRS] = { 138 "icu 0, req 0", 139 "icu 0, req 1", 140 "icu 1, req 0", 141 "icu 1, req 1", 142 }; 143 144 static bus_addr_t ic0_base, ic1_base; 145 146 void 147 au_intr_init(void) 148 { 149 int i; 150 struct au_chipdep *chip; 151 152 for (i = 0; i < NINTRS; i++) { 153 LIST_INIT(&au_cpuintrs[i].cintr_list); 154 evcnt_attach_dynamic(&au_cpuintrs[i].cintr_count, 155 EVCNT_TYPE_INTR, NULL, "mips", au_cpuintrnames[i]); 156 } 157 158 chip = au_chipdep(); 159 KASSERT(chip != NULL); 160 161 ic0_base = chip->icus[0]; 162 ic1_base = chip->icus[1]; 163 164 for (i = 0; i < NIRQS; i++) { 165 au_icu_intrtab[i].intr_refcnt = 0; 166 evcnt_attach_dynamic(&au_icu_intrtab[i].intr_count, 167 EVCNT_TYPE_INTR, NULL, chip->name, chip->irqnames[i]); 168 } 169 170 /* start with all interrupts masked */ 171 REGVAL(ic0_base + IC_MASK_CLEAR) = 0xffffffff; 172 REGVAL(ic0_base + IC_WAKEUP_CLEAR) = 0xffffffff; 173 REGVAL(ic0_base + IC_SOURCE_SET) = 0xffffffff; 174 REGVAL(ic0_base + IC_RISING_EDGE) = 0xffffffff; 175 REGVAL(ic0_base + IC_FALLING_EDGE) = 0xffffffff; 176 REGVAL(ic0_base + IC_TEST_BIT) = 0; 177 178 REGVAL(ic1_base + IC_MASK_CLEAR) = 0xffffffff; 179 REGVAL(ic1_base + IC_WAKEUP_CLEAR) = 0xffffffff; 180 REGVAL(ic1_base + IC_SOURCE_SET) = 0xffffffff; 181 REGVAL(ic1_base + IC_RISING_EDGE) = 0xffffffff; 182 REGVAL(ic1_base + IC_FALLING_EDGE) = 0xffffffff; 183 REGVAL(ic1_base + IC_TEST_BIT) = 0; 184 } 185 186 void * 187 au_intr_establish(int irq, int req, int level, int type, 188 int (*func)(void *), void *arg) 189 { 190 struct au_intrhand *ih; 191 uint32_t icu_base; 192 int cpu_int, s; 193 struct au_chipdep *chip; 194 195 chip = au_chipdep(); 196 KASSERT(chip != NULL); 197 198 if (irq >= NIRQS) 199 panic("au_intr_establish: bogus IRQ %d", irq); 200 if (req > 1) 201 panic("au_intr_establish: bogus request %d", req); 202 203 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 204 if (ih == NULL) 205 return (NULL); 206 207 ih->ih_func = func; 208 ih->ih_arg = arg; 209 ih->ih_irq = irq; 210 ih->ih_mask = (1 << (irq & 31)); 211 212 s = splhigh(); 213 214 /* 215 * First, link it into the tables. 216 * XXX do we want a separate list (really, should only be one item, not 217 * a list anyway) per irq, not per CPU interrupt? 218 */ 219 cpu_int = (irq < 32 ? 0 : 2) + req; 220 LIST_INSERT_HEAD(&au_cpuintrs[cpu_int].cintr_list, ih, ih_q); 221 222 /* 223 * Now enable it. 224 */ 225 if (au_icu_intrtab[irq].intr_refcnt++ == 0) { 226 icu_base = (irq < 32) ? ic0_base : ic1_base; 227 228 irq &= 31; /* throw away high bit if set */ 229 irq = 1 << irq; /* only used as a mask from here on */ 230 231 /* XXX Only level interrupts for now */ 232 switch (type) { 233 case IST_NONE: 234 case IST_PULSE: 235 case IST_EDGE: 236 panic("unsupported irq type %d", type); 237 /* NOTREACHED */ 238 case IST_LEVEL: 239 case IST_LEVEL_HIGH: 240 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 241 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 242 REGVAL(icu_base + IC_CONFIG0_SET) = irq; 243 break; 244 case IST_LEVEL_LOW: 245 REGVAL(icu_base + IC_CONFIG2_SET) = irq; 246 REGVAL(icu_base + IC_CONFIG1_SET) = irq; 247 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 248 break; 249 } 250 wbflush(); 251 252 /* XXX handle GPIO interrupts - not done at all yet */ 253 if (cpu_int & 0x1) 254 REGVAL(icu_base + IC_ASSIGN_REQUEST_CLEAR) = irq; 255 else 256 REGVAL(icu_base + IC_ASSIGN_REQUEST_SET) = irq; 257 258 /* Associate interrupt with peripheral */ 259 REGVAL(icu_base + IC_SOURCE_SET) = irq; 260 261 /* Actually enable the interrupt */ 262 REGVAL(icu_base + IC_MASK_SET) = irq; 263 264 /* And allow the interrupt to interrupt idle */ 265 REGVAL(icu_base + IC_WAKEUP_SET) = irq; 266 267 wbflush(); 268 } 269 splx(s); 270 271 return (ih); 272 } 273 274 void 275 au_intr_disestablish(void *cookie) 276 { 277 struct au_intrhand *ih = cookie; 278 uint32_t icu_base; 279 int irq, s; 280 281 irq = ih->ih_irq; 282 283 s = splhigh(); 284 285 /* 286 * First, remove it from the table. 287 */ 288 LIST_REMOVE(ih, ih_q); 289 290 /* 291 * Now, disable it, if there is nothing remaining on the 292 * list. 293 */ 294 if (au_icu_intrtab[irq].intr_refcnt-- == 1) { 295 icu_base = (irq < 32) ? ic0_base : ic1_base; 296 297 irq &= 31; /* throw away high bit if set */ 298 irq = 1 << irq; /* only used as a mask from here on */ 299 300 REGVAL(icu_base + IC_CONFIG2_CLEAR) = irq; 301 REGVAL(icu_base + IC_CONFIG1_CLEAR) = irq; 302 REGVAL(icu_base + IC_CONFIG0_CLEAR) = irq; 303 304 /* disable with MASK_CLEAR and WAKEUP_CLEAR */ 305 REGVAL(icu_base + IC_MASK_CLEAR) = irq; 306 REGVAL(icu_base + IC_WAKEUP_CLEAR) = irq; 307 wbflush(); 308 } 309 310 splx(s); 311 312 free(ih, M_DEVBUF); 313 } 314 315 void 316 au_iointr(uint32_t status, uint32_t cause, uint32_t pc, uint32_t ipending) 317 { 318 struct au_intrhand *ih; 319 int level; 320 uint32_t icu_base, irqstat, irqmask; 321 322 icu_base = irqstat = 0; 323 324 for (level = 3; level >= 0; level--) { 325 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 326 continue; 327 328 /* 329 * XXX the following may well be slow to execute. 330 * investigate and possibly speed up. 331 * 332 * is something like: 333 * 334 * irqstat = REGVAL( 335 * (level & 4 == 0) ? IC0_BASE ? IC1_BASE + 336 * (level & 2 == 0) ? IC_REQUEST0_INT : IC_REQUEST1_INT); 337 * 338 * be any better? 339 * 340 */ 341 switch (level) { 342 case 0: 343 icu_base = ic0_base; 344 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 345 break; 346 case 1: 347 icu_base = ic0_base; 348 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 349 break; 350 case 2: 351 icu_base = ic1_base; 352 irqstat = REGVAL(icu_base + IC_REQUEST0_INT); 353 break; 354 case 3: 355 icu_base = ic1_base; 356 irqstat = REGVAL(icu_base + IC_REQUEST1_INT); 357 break; 358 } 359 irqmask = REGVAL(icu_base + IC_MASK_READ); 360 au_cpuintrs[level].cintr_count.ev_count++; 361 LIST_FOREACH(ih, &au_cpuintrs[level].cintr_list, ih_q) { 362 int mask = ih->ih_mask; 363 364 if (mask & irqmask & irqstat) { 365 au_icu_intrtab[ih->ih_irq].intr_count.ev_count++; 366 (*ih->ih_func)(ih->ih_arg); 367 368 if (REGVAL(icu_base + IC_MASK_READ) & mask) { 369 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 370 REGVAL(icu_base + IC_MASK_SET) = mask; 371 wbflush(); 372 } 373 } 374 } 375 cause &= ~(MIPS_INT_MASK_0 << level); 376 } 377 378 /* Re-enable anything that we have processed. */ 379 _splset(MIPS_SR_INT_IE | ((status & ~cause) & MIPS_HARD_INT_MASK)); 380 } 381 382 /* 383 * Some devices (e.g. PCMCIA) want to be able to mask interrupts at 384 * the ICU, and leave them masked off until some later time 385 * (e.g. reenabled by a soft interrupt). 386 */ 387 388 void 389 au_intr_enable(int irq) 390 { 391 int s; 392 uint32_t icu_base, mask; 393 394 if (irq >= NIRQS) 395 panic("au_intr_enable: bogus IRQ %d", irq); 396 397 icu_base = (irq < 32) ? ic0_base : ic1_base; 398 mask = irq & 31; 399 mask = 1 << mask; 400 401 s = splhigh(); 402 /* only enable the interrupt if we have a handler */ 403 if (au_icu_intrtab[irq].intr_refcnt) { 404 REGVAL(icu_base + IC_MASK_SET) = mask; 405 REGVAL(icu_base + IC_WAKEUP_SET) = mask; 406 wbflush(); 407 } 408 splx(s); 409 } 410 411 void 412 au_intr_disable(int irq) 413 { 414 int s; 415 uint32_t icu_base, mask; 416 417 if (irq >= NIRQS) 418 panic("au_intr_disable: bogus IRQ %d", irq); 419 420 icu_base = (irq < 32) ? ic0_base : ic1_base; 421 mask = irq & 31; 422 mask = 1 << mask; 423 424 s = splhigh(); 425 REGVAL(icu_base + IC_MASK_CLEAR) = mask; 426 REGVAL(icu_base + IC_WAKEUP_CLEAR) = mask; 427 wbflush(); 428 splx(s); 429 } 430