1 /* $NetBSD: adm5120_intr.c,v 1.4 2011/02/20 07:48:35 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 */ 33 /*- 34 * Copyright (c) 2001 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Jason R. Thorpe. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 49 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 50 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 51 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 52 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 53 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 54 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 55 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 56 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 57 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 58 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 59 * POSSIBILITY OF SUCH DAMAGE. 60 */ 61 62 /* 63 * Platform-specific interrupt support for the Alchemy Semiconductor Pb1000. 64 * 65 * The Alchemy Semiconductor Pb1000's interrupts are wired to two internal 66 * interrupt controllers. 67 */ 68 69 #include <sys/cdefs.h> 70 __KERNEL_RCSID(0, "$NetBSD: adm5120_intr.c,v 1.4 2011/02/20 07:48:35 matt Exp $"); 71 72 #include "opt_ddb.h" 73 #define __INTR_PRIVATE 74 75 #include <sys/param.h> 76 #include <sys/queue.h> 77 #include <sys/malloc.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/kernel.h> 81 82 #include <machine/bus.h> 83 #include <machine/intr.h> 84 85 #include <mips/locore.h> 86 #include <mips/adm5120/include/adm5120reg.h> 87 #include <mips/adm5120/include/adm5120var.h> 88 89 #include <dev/pci/pcireg.h> 90 #include <dev/pci/pcivar.h> 91 92 /* 93 * This is a mask of bits to clear in the SR when we go to a 94 * given hardware interrupt priority level. 95 */ 96 static const struct ipl_sr_map adm5120_ipl_sr_map = { 97 .sr_bits = { 98 [IPL_NONE] = 0, 99 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0, 100 [IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0, 101 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK, 102 [IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK, 103 [IPL_VM] = MIPS_SOFT_INT_MASK|MIPS_INT_MASK_0, 104 [IPL_SCHED] = MIPS_INT_MASK, 105 [IPL_HIGH] = MIPS_INT_MASK, 106 }, 107 }; 108 109 #define NIRQS 32 110 const char * const adm5120_intrnames[NIRQS] = { 111 "timer", /* 0 */ 112 "uart0", /* 1 */ 113 "uart1", /* 2 */ 114 "usb", /* 3 */ 115 "intx0/gpio2", /* 4 */ 116 "intx1/gpio4", /* 5 */ 117 "pci0", /* 6 */ 118 "pci1", /* 7 */ 119 "pci2", /* 8 */ 120 "switch",/* 9 */ 121 "res10", /* 10 */ 122 "res11", /* 11 */ 123 "res12", /* 12 */ 124 "res13", /* 13 */ 125 "res14", /* 14 */ 126 "res15", /* 15 */ 127 "res16", /* 16 */ 128 "res17", /* 17 */ 129 "res18", /* 18 */ 130 "res19", /* 19 */ 131 "res20", /* 20 */ 132 "res21", /* 21 */ 133 "res22", /* 22 */ 134 "res23", /* 23 */ 135 "res24", /* 24 */ 136 "res25", /* 25 */ 137 "res26", /* 26 */ 138 "res27", /* 27 */ 139 "res28", /* 28 */ 140 "res29", /* 29 */ 141 "res30", /* 30 */ 142 "res31", /* 31 */ 143 }; 144 145 struct adm5120_intrhead { 146 struct evcnt intr_count; 147 int intr_refcnt; 148 }; 149 struct adm5120_intrhead adm5120_intrtab[NIRQS]; 150 151 152 #define NINTRS 2 /* MIPS INT0 - INT1 */ 153 struct adm5120_cpuintr { 154 LIST_HEAD(, evbmips_intrhand) cintr_list; 155 struct evcnt cintr_count; 156 }; 157 struct adm5120_cpuintr adm5120_cpuintrs[NINTRS]; 158 159 const char * const adm5120_cpuintrnames[NINTRS] = { 160 "int 0 (irq)", 161 "int 1 (fiq)", 162 }; 163 164 #define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(ADM5120_BASE_ICU + (o))) 165 #define REG_WRITE(o,v) (REG_READ(o)) = (v) 166 167 void 168 evbmips_intr_init(void) 169 { 170 ipl_sr_map = adm5120_ipl_sr_map; 171 172 for (size_t i = 0; i < NINTRS; i++) { 173 LIST_INIT(&adm5120_cpuintrs[i].cintr_list); 174 evcnt_attach_dynamic(&adm5120_cpuintrs[i].cintr_count, 175 EVCNT_TYPE_INTR, NULL, "mips", adm5120_cpuintrnames[i]); 176 } 177 178 for (size_t i = 0; i < NIRQS; i++) { 179 /* XXX steering - use an irqmap array? */ 180 181 adm5120_intrtab[i].intr_refcnt = 0; 182 evcnt_attach_dynamic(&adm5120_intrtab[i].intr_count, 183 EVCNT_TYPE_INTR, NULL, "adm5120", adm5120_intrnames[i]); 184 } 185 186 /* disable all interrupts */ 187 REG_WRITE(ICU_DISABLE_REG, ICU_INT_MASK); 188 } 189 190 void * 191 adm5120_intr_establish(int irq, int priority, int (*func)(void *), void *arg) 192 { 193 struct evbmips_intrhand *ih; 194 uint32_t irqmask; 195 int cpu_int, s; 196 197 if (irq < 0 || irq >= NIRQS) 198 panic("adm5120_intr_establish: bogus IRQ %d", irq); 199 200 ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT); 201 if (ih == NULL) 202 return NULL; 203 204 ih->ih_func = func; 205 ih->ih_arg = arg; 206 ih->ih_irq = irq; 207 208 s = splhigh(); 209 210 /* 211 * First, link it into the tables. 212 * XXX do we want a separate list (really, should only be one item, not 213 * a list anyway) per irq, not per CPU interrupt? 214 */ 215 216 cpu_int = (priority == INTR_FIQ) ? 1 : 0; 217 218 LIST_INSERT_HEAD(&adm5120_cpuintrs[cpu_int].cintr_list, ih, ih_q); 219 220 /* 221 * Now enable it. 222 */ 223 if (adm5120_intrtab[irq].intr_refcnt++ == 0) { 224 irqmask = 1 << irq; 225 226 /* configure as IRQ or FIQ */ 227 if (priority == INTR_FIQ) { 228 REG_WRITE(ICU_MODE_REG, 229 REG_READ(ICU_MODE_REG) | irqmask); 230 } else { 231 REG_WRITE(ICU_MODE_REG, 232 REG_READ(ICU_MODE_REG) & ~irqmask); 233 } 234 /* enable */ 235 REG_WRITE(ICU_ENABLE_REG, irqmask); 236 } 237 splx(s); 238 239 return ih; 240 } 241 242 void 243 adm5120_intr_disestablish(void *cookie) 244 { 245 struct evbmips_intrhand *ih = cookie; 246 int irq, s; 247 uint32_t irqmask; 248 249 irq = ih->ih_irq; 250 251 s = splhigh(); 252 253 /* 254 * First, remove it from the table. 255 */ 256 LIST_REMOVE(ih, ih_q); 257 258 /* 259 * Now, disable it, if there is nothing remaining on the 260 * list. 261 */ 262 if (adm5120_intrtab[irq].intr_refcnt-- == 1) { 263 irqmask = 1 << irq; /* only used as a mask from here on */ 264 265 /* disable this irq in HW */ 266 REG_WRITE(ICU_DISABLE_REG, irqmask); 267 } 268 269 splx(s); 270 271 free(ih, M_DEVBUF); 272 } 273 void 274 evbmips_iointr(int ipl, uint32_t pc, uint32_t ipending) 275 { 276 struct evbmips_intrhand *ih; 277 uint32_t irqmask, irqstat; 278 279 for (int level = NINTRS - 1; level >= 0; level--) { 280 if ((ipending & (MIPS_INT_MASK_0 << level)) == 0) 281 continue; 282 283 if (level) 284 irqstat = REG_READ(ICU_FIQ_STATUS_REG); 285 else 286 irqstat = REG_READ(ICU_STATUS_REG); 287 288 adm5120_cpuintrs[level].cintr_count.ev_count++; 289 LIST_FOREACH(ih, &adm5120_cpuintrs[level].cintr_list, ih_q) { 290 irqmask = 1 << ih->ih_irq; 291 if (irqmask & irqstat) { 292 adm5120_intrtab[ih->ih_irq].intr_count.ev_count++; 293 (*ih->ih_func)(ih->ih_arg); 294 } 295 } 296 } 297 } 298