1 /* $NetBSD: uninorth.c,v 1.18 2015/10/02 05:22:51 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: uninorth.c,v 1.18 2015/10/02 05:22:51 msaitoh Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/device.h> 34 #include <sys/systm.h> 35 36 #include <dev/pci/pcivar.h> 37 #include <dev/ofw/openfirm.h> 38 #include <dev/ofw/ofw_pci.h> 39 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 43 struct uninorth_softc { 44 device_t sc_dev; 45 struct genppc_pci_chipset sc_pc; 46 struct powerpc_bus_space sc_iot; 47 struct powerpc_bus_space sc_memt; 48 }; 49 50 static void uninorth_attach(device_t, device_t, void *); 51 static int uninorth_match(device_t, cfdata_t, void *); 52 53 static pcireg_t uninorth_conf_read(void *, pcitag_t, int); 54 static void uninorth_conf_write(void *, pcitag_t, int, pcireg_t); 55 static pcireg_t uninorth_conf_read_v3(void *, pcitag_t, int); 56 static void uninorth_conf_write_v3(void *, pcitag_t, int, pcireg_t); 57 58 CFATTACH_DECL_NEW(uninorth, sizeof(struct uninorth_softc), 59 uninorth_match, uninorth_attach, NULL, NULL); 60 61 static int 62 uninorth_match(device_t parent, cfdata_t cf, void *aux) 63 { 64 struct confargs *ca = aux; 65 char compat[32]; 66 67 if (strcmp(ca->ca_name, "pci") != 0) 68 return 0; 69 70 memset(compat, 0, sizeof(compat)); 71 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 72 if (strcmp(compat, "uni-north") != 0 && 73 strcmp(compat, "u3-agp") != 0 && 74 strcmp(compat, "u4-pcie") != 0) 75 return 0; 76 77 return 1; 78 } 79 80 static void 81 uninorth_attach(device_t parent, device_t self, void *aux) 82 { 83 struct uninorth_softc *sc = device_private(self); 84 pci_chipset_tag_t pc = &sc->sc_pc; 85 struct confargs *ca = aux; 86 struct pcibus_attach_args pba; 87 int len, child, node = ca->ca_node; 88 uint32_t reg[2], busrange[2]; 89 char compat[32]; 90 int ver; 91 struct ranges { 92 uint32_t pci_hi, pci_mid, pci_lo; 93 uint32_t host; 94 uint32_t size_hi, size_lo; 95 } ranges[6], *rp = ranges; 96 97 printf("\n"); 98 sc->sc_dev = self; 99 100 memset(compat, 0, sizeof(compat)); 101 OF_getprop(ca->ca_node, "compatible", compat, sizeof(compat)); 102 if (strcmp(compat, "u3-agp") == 0) 103 ver = 3; 104 else if (strcmp(compat, "u4-pcie") == 0) 105 ver = 4; 106 else 107 ver = 0; 108 109 /* UniNorth address */ 110 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) 111 return; 112 113 /* PCI bus number */ 114 if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8) 115 return; 116 117 memset(&sc->sc_iot, 0, sizeof(sc->sc_iot)); 118 119 /* find i/o tag */ 120 len = OF_getprop(node, "ranges", ranges, sizeof(ranges)); 121 if (len == -1) 122 return; 123 while (len >= sizeof(ranges[0])) { 124 if ((rp->pci_hi & OFW_PCI_PHYS_HI_SPACEMASK) == 125 OFW_PCI_PHYS_HI_SPACE_IO) { 126 sc->sc_iot.pbs_base = rp->host; 127 sc->sc_iot.pbs_limit = rp->host + rp->size_lo; 128 break; 129 } 130 len -= sizeof(ranges[0]); 131 rp++; 132 } 133 134 /* XXX enable gmac ethernet */ 135 for (child = OF_child(node); child; child = OF_peer(child)) { 136 volatile int *gmac_gbclock_en = (void *)0xf8000020; 137 138 memset(compat, 0, sizeof(compat)); 139 OF_getprop(child, "compatible", compat, sizeof(compat)); 140 if (strcmp(compat, "gmac") == 0) 141 *gmac_gbclock_en |= 0x02; 142 } 143 144 sc->sc_iot.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE; 145 sc->sc_iot.pbs_offset = 0; 146 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, &sc->sc_iot, 147 "uninorth io-space") != 0) 148 panic("Can't init uninorth io tag"); 149 150 memset(&sc->sc_memt, 0, sizeof(sc->sc_memt)); 151 sc->sc_memt.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE; 152 sc->sc_memt.pbs_base = 0x00000000; 153 if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, &sc->sc_memt, 154 "uninorth mem-space") != 0) 155 panic("Can't init uninorth mem tag"); 156 157 macppc_pci_get_chipset_tag(pc); 158 pc->pc_node = node; 159 pc->pc_bus = busrange[0]; 160 pc->pc_iot = &sc->sc_iot; 161 pc->pc_memt = &sc->sc_memt; 162 163 if (ver < 3) { 164 pc->pc_addr = mapiodev(reg[0] + 0x800000, 4, false); 165 pc->pc_data = mapiodev(reg[0] + 0xc00000, 8, false); 166 pc->pc_conf_read = uninorth_conf_read; 167 pc->pc_conf_write = uninorth_conf_write; 168 } else { 169 pc->pc_addr = mapiodev(reg[1] + 0x800000, 4, false); 170 pc->pc_data = mapiodev(reg[1] + 0xc00000, 8, false); 171 pc->pc_conf_read = uninorth_conf_read_v3; 172 pc->pc_conf_write = uninorth_conf_write_v3; 173 } 174 175 memset(&pba, 0, sizeof(pba)); 176 pba.pba_memt = pc->pc_memt; 177 pba.pba_iot = pc->pc_iot; 178 pba.pba_dmat = &pci_bus_dma_tag; 179 pba.pba_dmat64 = NULL; 180 pba.pba_bus = pc->pc_bus; 181 pba.pba_bridgetag = NULL; 182 pba.pba_pc = pc; 183 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 184 185 config_found_ia(self, "pcibus", &pba, pcibusprint); 186 } 187 188 static pcireg_t 189 uninorth_conf_read(void *cookie, pcitag_t tag, int reg) 190 { 191 pci_chipset_tag_t pc = cookie; 192 int32_t *daddr = pc->pc_data; 193 pcireg_t data; 194 int bus, dev, func, s; 195 uint32_t x; 196 197 if ((unsigned int)reg >= PCI_CONF_SIZE) 198 return (pcireg_t) -1; 199 200 /* UniNorth seems to have a 64bit data port */ 201 if (reg & 0x04) 202 daddr++; 203 204 pci_decompose_tag(pc, tag, &bus, &dev, &func); 205 206 /* 207 * bandit's minimum device number of the first bus is 11. 208 * So we behave as if there is no device when dev < 11. 209 */ 210 if (func > 7) 211 panic("pci_conf_read: func > 7"); 212 213 if (bus == pc->pc_bus) { 214 if (dev < 11) 215 return 0xffffffff; 216 x = (1 << dev) | (func << 8) | reg; 217 } else 218 x = tag | reg | 1; 219 220 s = splhigh(); 221 222 out32rb(pc->pc_addr, x); 223 in32rb(pc->pc_addr); 224 data = 0xffffffff; 225 if (!badaddr(daddr, 4)) 226 data = in32rb(daddr); 227 out32rb(pc->pc_addr, 0); 228 in32rb(pc->pc_addr); 229 splx(s); 230 231 return data; 232 } 233 234 static void 235 uninorth_conf_write(void *cookie, pcitag_t tag, int reg, pcireg_t data) 236 { 237 pci_chipset_tag_t pc = cookie; 238 int32_t *daddr = pc->pc_data; 239 int bus, dev, func, s; 240 uint32_t x; 241 242 if ((unsigned int)reg >= PCI_CONF_SIZE) 243 return; 244 245 /* UniNorth seems to have a 64bit data port */ 246 if (reg & 0x04) 247 daddr++; 248 249 pci_decompose_tag(pc, tag, &bus, &dev, &func); 250 251 if (func > 7) 252 panic("pci_conf_write: func > 7"); 253 254 if (bus == pc->pc_bus) { 255 if (dev < 11) 256 panic("pci_conf_write: dev < 11"); 257 x = (1 << dev) | (func << 8) | reg; 258 } else 259 x = tag | reg | 1; 260 261 s = splhigh(); 262 263 out32rb(pc->pc_addr, x); 264 in32rb(pc->pc_addr); 265 out32rb(daddr, data); 266 out32rb(pc->pc_addr, 0); 267 in32rb(pc->pc_addr); 268 269 splx(s); 270 } 271 272 static pcireg_t 273 uninorth_conf_read_v3(void *cookie, pcitag_t tag, int reg) 274 { 275 pci_chipset_tag_t pc = cookie; 276 int32_t *daddr = pc->pc_data; 277 pcireg_t data; 278 int bus, dev, func, s; 279 uint32_t x; 280 281 if ((unsigned int)reg >= PCI_CONF_SIZE) 282 return (pcireg_t) -1; 283 284 /* UniNorth seems to have a 64bit data port */ 285 if (reg & 0x04) 286 daddr++; 287 288 pci_decompose_tag(pc, tag, &bus, &dev, &func); 289 290 x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1; 291 /* Set extended register bits */ 292 x |= (reg >> 8) << 28; 293 294 s = splhigh(); 295 296 out32rb(pc->pc_addr, x); 297 in32rb(pc->pc_addr); 298 data = 0xffffffff; 299 if (!badaddr(daddr, 4)) 300 data = in32rb(daddr); 301 out32rb(pc->pc_addr, 0); 302 in32rb(pc->pc_addr); 303 splx(s); 304 305 return data; 306 } 307 308 static void 309 uninorth_conf_write_v3(void *cookie, pcitag_t tag, int reg, pcireg_t data) 310 { 311 pci_chipset_tag_t pc = cookie; 312 int32_t *daddr = pc->pc_data; 313 int bus, dev, func, s; 314 uint32_t x; 315 316 if ((unsigned int)reg >= PCI_CONF_SIZE) 317 return; 318 319 /* UniNorth seems to have a 64bit data port */ 320 if (reg & 0x04) 321 daddr++; 322 323 pci_decompose_tag(pc, tag, &bus, &dev, &func); 324 325 x = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 1; 326 /* Set extended register bits */ 327 x |= (reg >> 8) << 28; 328 329 s = splhigh(); 330 331 out32rb(pc->pc_addr, x); 332 in32rb(pc->pc_addr); 333 out32rb(daddr, data); 334 out32rb(pc->pc_addr, 0); 335 in32rb(pc->pc_addr); 336 337 splx(s); 338 } 339