xref: /netbsd-src/sys/arch/macppc/macppc/ipi_hammerhead.c (revision c505c4429840c353a86d4eb53b5e2bfc0092264e)
1 /* $NetBSD: ipi_hammerhead.c,v 1.3 2008/04/28 20:23:27 martin Exp $ */
2 /*-
3  * Copyright (c) 2007 The NetBSD Foundation, Inc.
4  * All rights reserved.
5  *
6  * This code is derived from software contributed to The NetBSD Foundation
7  * by Tim Rightnour
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  * 1. Redistributions of source code must retain the above copyright
13  *    notice, this list of conditions and the following disclaimer.
14  * 2. Redistributions in binary form must reproduce the above copyright
15  *    notice, this list of conditions and the following disclaimer in the
16  *    documentation and/or other materials provided with the distribution.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
20  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28  * POSSIBILITY OF SUCH DAMAGE.
29  */
30 
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: ipi_hammerhead.c,v 1.3 2008/04/28 20:23:27 martin Exp $");
33 
34 #include "opt_multiprocessor.h"
35 #include <sys/param.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
38 
39 #include <uvm/uvm_extern.h>
40 
41 #include <machine/pio.h>
42 #include <powerpc/atomic.h>
43 
44 #include <arch/powerpc/pic/picvar.h>
45 #include <arch/powerpc/pic/ipivar.h>
46 
47 #ifdef MULTIPROCESSOR
48 
49 extern struct ipi_ops ipiops;
50 extern volatile u_long IPI[CPU_MAXNUM];
51 static void hh_send_ipi(int, u_long);
52 static void hh_establish_ipi(int, int, void *);
53 
54 #define HH_INTR_SECONDARY	0xf80000c0
55 #define HH_INTR_PRIMARY		0xf3019000
56 #define GC_IPI_IRQ		30
57 
58 void
59 setup_hammerhead_ipi(void)
60 {
61 	ipiops.ppc_send_ipi = hh_send_ipi;
62 	ipiops.ppc_establish_ipi = hh_establish_ipi;
63 	ipiops.ppc_ipi_vector = GC_IPI_IRQ;
64 }
65 
66 static void
67 hh_send_ipi(int target, u_long mesg)
68 {
69 	int cpu_id = target;
70 
71 	if (target == IPI_T_ALL) {
72 		atomic_setbits_ulong(&IPI[0], mesg);
73 		atomic_setbits_ulong(&IPI[1], mesg);
74 		in32(HH_INTR_PRIMARY);
75 		out32(HH_INTR_SECONDARY, ~0);
76 		out32(HH_INTR_SECONDARY, 0);
77 		return;
78 	}
79 
80 	if (target == IPI_T_NOTME) {
81 		switch (cpu_number()) {
82 		case 0:
83 			cpu_id = 1;
84 			break;
85 		case 1:
86 			cpu_id = 0;
87 		}
88 	}
89 
90 	atomic_setbits_ulong(&IPI[cpu_id], mesg);
91 	switch (cpu_id) {
92 	case 0:
93 		in32(HH_INTR_PRIMARY);
94 		break;
95 	case 1:
96 		out32(HH_INTR_SECONDARY, ~0);
97 		out32(HH_INTR_SECONDARY, 0);
98 		break;
99 	}
100 }
101 
102 static void
103 hh_establish_ipi(int type, int level, void *ih_args)
104 {
105 	intr_establish(ipiops.ppc_ipi_vector, type, level, ppcipi_intr,
106 	    ih_args);
107 }
108 
109 #endif /*MULTIPROCESSOR*/
110