1 /* $NetBSD: intr.h,v 1.5 1999/08/05 18:08:11 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _MACPPC_INTR_H_ 40 #define _MACPPC_INTR_H_ 41 42 /* Interrupt priority `levels'. */ 43 #define IPL_NONE 9 /* nothing */ 44 #define IPL_SOFTCLOCK 8 /* timeouts */ 45 #define IPL_SOFTNET 7 /* protocol stacks */ 46 #define IPL_BIO 6 /* block I/O */ 47 #define IPL_NET 5 /* network */ 48 #define IPL_SOFTSERIAL 4 /* serial */ 49 #define IPL_TTY 3 /* terminal */ 50 #define IPL_IMP 3 /* memory allocation */ 51 #define IPL_AUDIO 2 /* audio */ 52 #define IPL_CLOCK 1 /* clock */ 53 #define IPL_HIGH 1 /* everything */ 54 #define IPL_SERIAL 0 /* serial */ 55 #define NIPL 10 56 57 /* Interrupt sharing types. */ 58 #define IST_NONE 0 /* none */ 59 #define IST_PULSE 1 /* pulsed */ 60 #define IST_EDGE 2 /* edge-triggered */ 61 #define IST_LEVEL 3 /* level-triggered */ 62 63 #ifndef _LOCORE 64 65 /* 66 * Interrupt handler chains. intr_establish() inserts a handler into 67 * the list. The handler is called with its (single) argument. 68 */ 69 struct intrhand { 70 int (*ih_fun) __P((void *)); 71 void *ih_arg; 72 u_long ih_count; 73 struct intrhand *ih_next; 74 int ih_level; 75 int ih_irq; 76 }; 77 78 void setsoftclock __P((void)); 79 void clearsoftclock __P((void)); 80 int splsoftclock __P((void)); 81 void setsoftnet __P((void)); 82 void clearsoftnet __P((void)); 83 int splsoftnet __P((void)); 84 85 void do_pending_int __P((void)); 86 87 static __inline int splraise __P((int)); 88 static __inline int spllower __P((int)); 89 static __inline void splx __P((int)); 90 static __inline void softintr __P((int)); 91 92 extern volatile int cpl, ipending, astpending, tickspending; 93 extern int imask[]; 94 95 /* 96 * Reorder protection in the following inline functions is 97 * achived with the "eieio" instruction which the assembler 98 * seems to detect and then doen't move instructions past.... 99 */ 100 static __inline int 101 splraise(ncpl) 102 int ncpl; 103 { 104 int ocpl; 105 106 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 107 ocpl = cpl; 108 cpl = ocpl | ncpl; 109 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 110 return (ocpl); 111 } 112 113 static __inline void 114 splx(ncpl) 115 int ncpl; 116 { 117 118 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 119 cpl = ncpl; 120 if (ipending & ~ncpl) 121 do_pending_int(); 122 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 123 } 124 125 static __inline int 126 spllower(ncpl) 127 int ncpl; 128 { 129 int ocpl; 130 131 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 132 ocpl = cpl; 133 cpl = ncpl; 134 if (ipending & ~ncpl) 135 do_pending_int(); 136 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 137 return (ocpl); 138 } 139 140 /* Following code should be implemented with lwarx/stwcx to avoid 141 * the disable/enable. i need to read the manual once more.... */ 142 static __inline void 143 softintr(ipl) 144 int ipl; 145 { 146 int msrsave; 147 148 __asm__ volatile("mfmsr %0" : "=r"(msrsave)); 149 __asm__ volatile("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 150 ipending |= 1 << ipl; 151 __asm__ volatile("mtmsr %0" :: "r"(msrsave)); 152 } 153 154 #define ICU_LEN 32 155 156 /* Soft interrupt masks. */ 157 #define SIR_CLOCK 28 158 #define SIR_NET 29 159 #define SIR_SERIAL 30 160 #define SPL_CLOCK 31 161 162 /* 163 * Hardware interrupt masks 164 */ 165 #define splbio() splraise(imask[IPL_BIO]) 166 #define splnet() splraise(imask[IPL_NET]) 167 #define spltty() splraise(imask[IPL_TTY]) 168 #define splaudio() splraise(imask[IPL_AUDIO]) 169 #define splclock() splraise(imask[IPL_CLOCK]) 170 #define splstatclock() splclock() 171 #define splserial() splraise(imask[IPL_SERIAL]) 172 173 #define spllpt() spltty() 174 175 /* 176 * Software interrupt masks 177 * 178 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 179 * clock to softclock before it calls softclock(). 180 */ 181 #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 182 #define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 183 #define splsoftnet() splraise(imask[IPL_SOFTNET]) 184 #define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 185 186 /* 187 * Miscellaneous 188 */ 189 #define splimp() splraise(imask[IPL_IMP]) 190 #define splhigh() splraise(imask[IPL_HIGH]) 191 #define spl0() spllower(0) 192 193 #define setsoftclock() softintr(SIR_CLOCK) 194 #define setsoftnet() softintr(SIR_NET) 195 #define setsoftserial() softintr(SIR_SERIAL) 196 197 extern long intrcnt[]; 198 199 #define CNT_IRQ0 0 200 #define CNT_CLOCK 64 201 #define CNT_SOFTCLOCK 65 202 #define CNT_SOFTNET 66 203 #define CNT_SOFTSERIAL 67 204 205 #endif /* !_LOCORE */ 206 207 #endif /* !_MACPPC_INTR_H_ */ 208