1 /* $NetBSD: if_gm.c,v 1.38 2010/04/05 07:19:30 joerg Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.38 2010/04/05 07:19:30 joerg Exp $"); 31 32 #include "opt_inet.h" 33 #include "rnd.h" 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/ioctl.h> 38 #include <sys/kernel.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 44 #if NRND > 0 45 #include <sys/rnd.h> 46 #endif 47 48 #include <uvm/uvm_extern.h> 49 50 #include <net/if.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 54 #include <net/bpf.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/if_inarp.h> 59 #endif 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/ofw/openfirm.h> 69 #include <macppc/dev/if_gmreg.h> 70 #include <machine/pio.h> 71 72 #define NTXBUF 4 73 #define NRXBUF 32 74 75 struct gmac_softc { 76 struct device sc_dev; 77 struct ethercom sc_ethercom; 78 vaddr_t sc_reg; 79 struct gmac_dma *sc_txlist; 80 struct gmac_dma *sc_rxlist; 81 int sc_txnext; 82 int sc_rxlast; 83 void *sc_txbuf[NTXBUF]; 84 void *sc_rxbuf[NRXBUF]; 85 struct mii_data sc_mii; 86 struct callout sc_tick_ch; 87 char sc_laddr[6]; 88 89 #if NRND > 0 90 rndsource_element_t sc_rnd_source; /* random source */ 91 #endif 92 }; 93 94 #define sc_if sc_ethercom.ec_if 95 96 int gmac_match(struct device *, struct cfdata *, void *); 97 void gmac_attach(struct device *, struct device *, void *); 98 99 static inline u_int gmac_read_reg(struct gmac_softc *, int); 100 static inline void gmac_write_reg(struct gmac_softc *, int, u_int); 101 102 static inline void gmac_start_txdma(struct gmac_softc *); 103 static inline void gmac_start_rxdma(struct gmac_softc *); 104 static inline void gmac_stop_txdma(struct gmac_softc *); 105 static inline void gmac_stop_rxdma(struct gmac_softc *); 106 107 int gmac_intr(void *); 108 void gmac_tint(struct gmac_softc *); 109 void gmac_rint(struct gmac_softc *); 110 struct mbuf * gmac_get(struct gmac_softc *, void *, int); 111 void gmac_start(struct ifnet *); 112 int gmac_put(struct gmac_softc *, void *, struct mbuf *); 113 114 void gmac_stop(struct gmac_softc *); 115 void gmac_reset(struct gmac_softc *); 116 void gmac_init(struct gmac_softc *); 117 void gmac_init_mac(struct gmac_softc *); 118 void gmac_setladrf(struct gmac_softc *); 119 120 int gmac_ioctl(struct ifnet *, u_long, void *); 121 void gmac_watchdog(struct ifnet *); 122 123 int gmac_mii_readreg(struct device *, int, int); 124 void gmac_mii_writereg(struct device *, int, int, int); 125 void gmac_mii_statchg(struct device *); 126 void gmac_mii_tick(void *); 127 128 CFATTACH_DECL(gm, sizeof(struct gmac_softc), 129 gmac_match, gmac_attach, NULL, NULL); 130 131 int 132 gmac_match(struct device *parent, struct cfdata *match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 136 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 137 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 139 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 140 return 1; 141 142 return 0; 143 } 144 145 void 146 gmac_attach(struct device *parent, struct device *self, void *aux) 147 { 148 struct gmac_softc *sc = (void *)self; 149 struct pci_attach_args *pa = aux; 150 struct ifnet *ifp = &sc->sc_if; 151 struct mii_data *mii = &sc->sc_mii; 152 pci_intr_handle_t ih; 153 const char *intrstr = NULL; 154 int node, i; 155 char *p; 156 struct gmac_dma *dp; 157 u_int32_t reg[10]; 158 u_char laddr[6]; 159 160 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 161 if (node == 0) { 162 printf(": cannot find gmac node\n"); 163 return; 164 } 165 166 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 167 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 168 169 memcpy(sc->sc_laddr, laddr, sizeof laddr); 170 sc->sc_reg = reg[2]; 171 172 if (pci_intr_map(pa, &ih)) { 173 printf(": unable to map interrupt\n"); 174 return; 175 } 176 intrstr = pci_intr_string(pa->pa_pc, ih); 177 178 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 179 printf(": unable to establish interrupt"); 180 if (intrstr) 181 printf(" at %s", intrstr); 182 printf("\n"); 183 return; 184 } 185 186 /* Setup packet buffers and DMA descriptors. */ 187 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 188 if (p == NULL) { 189 printf(": cannot malloc buffers\n"); 190 return; 191 } 192 p = (void *)roundup((vaddr_t)p, 0x800); 193 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 194 195 sc->sc_rxlist = (void *)p; 196 p += 0x800; 197 sc->sc_txlist = (void *)p; 198 p += 0x800; 199 200 dp = sc->sc_rxlist; 201 for (i = 0; i < NRXBUF; i++) { 202 sc->sc_rxbuf[i] = p; 203 dp->address = htole32(vtophys((vaddr_t)p)); 204 dp->cmd = htole32(GMAC_OWN); 205 dp++; 206 p += 2048; 207 } 208 209 dp = sc->sc_txlist; 210 for (i = 0; i < NTXBUF; i++) { 211 sc->sc_txbuf[i] = p; 212 dp->address = htole32(vtophys((vaddr_t)p)); 213 dp++; 214 p += 2048; 215 } 216 217 printf(": Ethernet address %s\n", ether_sprintf(laddr)); 218 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 219 220 callout_init(&sc->sc_tick_ch, 0); 221 222 gmac_reset(sc); 223 gmac_init_mac(sc); 224 225 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 226 ifp->if_softc = sc; 227 ifp->if_ioctl = gmac_ioctl; 228 ifp->if_start = gmac_start; 229 ifp->if_watchdog = gmac_watchdog; 230 ifp->if_flags = 231 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 232 IFQ_SET_READY(&ifp->if_snd); 233 234 mii->mii_ifp = ifp; 235 mii->mii_readreg = gmac_mii_readreg; 236 mii->mii_writereg = gmac_mii_writereg; 237 mii->mii_statchg = gmac_mii_statchg; 238 239 sc->sc_ethercom.ec_mii = mii; 240 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 241 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 242 243 /* Choose a default media. */ 244 if (LIST_FIRST(&mii->mii_phys) == NULL) { 245 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 246 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 247 } else 248 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 249 250 if_attach(ifp); 251 ether_ifattach(ifp, laddr); 252 #if NRND > 0 253 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 254 RND_TYPE_NET, 0); 255 #endif 256 } 257 258 u_int 259 gmac_read_reg(struct gmac_softc *sc, int reg) 260 { 261 return in32rb(sc->sc_reg + reg); 262 } 263 264 void 265 gmac_write_reg(struct gmac_softc *sc, int reg, u_int val) 266 { 267 out32rb(sc->sc_reg + reg, val); 268 } 269 270 void 271 gmac_start_txdma(struct gmac_softc *sc) 272 { 273 u_int x; 274 275 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 276 x |= 1; 277 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 278 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 279 x |= 1; 280 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 281 } 282 283 void 284 gmac_start_rxdma(struct gmac_softc *sc) 285 { 286 u_int x; 287 288 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 289 x |= 1; 290 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 291 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 292 x |= 1; 293 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 294 } 295 296 void 297 gmac_stop_txdma(struct gmac_softc *sc) 298 { 299 u_int x; 300 301 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 302 x &= ~1; 303 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 304 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 305 x &= ~1; 306 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 307 } 308 309 void 310 gmac_stop_rxdma(struct gmac_softc *sc) 311 { 312 u_int x; 313 314 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 315 x &= ~1; 316 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 317 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 318 x &= ~1; 319 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 320 } 321 322 int 323 gmac_intr(void *v) 324 { 325 struct gmac_softc *sc = v; 326 u_int status; 327 328 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 329 if (status == 0) 330 return 0; 331 332 if (status & GMAC_INT_RXDONE) 333 gmac_rint(sc); 334 335 if (status & GMAC_INT_TXEMPTY) 336 gmac_tint(sc); 337 338 #if NRND > 0 339 rnd_add_uint32(&sc->sc_rnd_source, status); 340 #endif 341 return 1; 342 } 343 344 void 345 gmac_tint(struct gmac_softc *sc) 346 { 347 struct ifnet *ifp = &sc->sc_if; 348 349 ifp->if_flags &= ~IFF_OACTIVE; 350 ifp->if_timer = 0; 351 gmac_start(ifp); 352 } 353 354 void 355 gmac_rint(struct gmac_softc *sc) 356 { 357 struct ifnet *ifp = &sc->sc_if; 358 volatile struct gmac_dma *dp; 359 struct mbuf *m; 360 int i, j, len; 361 u_int cmd; 362 363 for (i = sc->sc_rxlast;; i++) { 364 if (i == NRXBUF) 365 i = 0; 366 367 dp = &sc->sc_rxlist[i]; 368 cmd = le32toh(dp->cmd); 369 if (cmd & GMAC_OWN) 370 break; 371 len = (cmd >> 16) & GMAC_LEN_MASK; 372 len -= 4; /* CRC */ 373 374 if (le32toh(dp->cmd_hi) & 0x40000000) { 375 ifp->if_ierrors++; 376 goto next; 377 } 378 379 m = gmac_get(sc, sc->sc_rxbuf[i], len); 380 if (m == NULL) { 381 ifp->if_ierrors++; 382 goto next; 383 } 384 385 /* 386 * Check if there's a BPF listener on this interface. 387 * If so, hand off the raw packet to BPF. 388 */ 389 bpf_mtap(ifp, m); 390 (*ifp->if_input)(ifp, m); 391 ifp->if_ipackets++; 392 393 next: 394 dp->cmd_hi = 0; 395 __asm volatile ("sync"); 396 dp->cmd = htole32(GMAC_OWN); 397 } 398 sc->sc_rxlast = i; 399 400 /* XXX Make sure free buffers have GMAC_OWN. */ 401 i++; 402 for (j = 1; j < NRXBUF; j++) { 403 if (i == NRXBUF) 404 i = 0; 405 dp = &sc->sc_rxlist[i++]; 406 dp->cmd = htole32(GMAC_OWN); 407 } 408 } 409 410 struct mbuf * 411 gmac_get(struct gmac_softc *sc, void *pkt, int totlen) 412 { 413 struct mbuf *m; 414 struct mbuf *top, **mp; 415 int len; 416 417 MGETHDR(m, M_DONTWAIT, MT_DATA); 418 if (m == 0) 419 return 0; 420 m->m_pkthdr.rcvif = &sc->sc_if; 421 m->m_pkthdr.len = totlen; 422 len = MHLEN; 423 top = 0; 424 mp = ⊤ 425 426 while (totlen > 0) { 427 if (top) { 428 MGET(m, M_DONTWAIT, MT_DATA); 429 if (m == 0) { 430 m_freem(top); 431 return 0; 432 } 433 len = MLEN; 434 } 435 if (totlen >= MINCLSIZE) { 436 MCLGET(m, M_DONTWAIT); 437 if ((m->m_flags & M_EXT) == 0) { 438 m_free(m); 439 m_freem(top); 440 return 0; 441 } 442 len = MCLBYTES; 443 } 444 m->m_len = len = min(totlen, len); 445 memcpy(mtod(m, void *), pkt, len); 446 pkt += len; 447 totlen -= len; 448 *mp = m; 449 mp = &m->m_next; 450 } 451 452 return top; 453 } 454 455 void 456 gmac_start(struct ifnet *ifp) 457 { 458 struct gmac_softc *sc = ifp->if_softc; 459 struct mbuf *m; 460 void *buff; 461 int i, tlen; 462 volatile struct gmac_dma *dp; 463 464 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 465 return; 466 467 for (;;) { 468 if (ifp->if_flags & IFF_OACTIVE) 469 break; 470 471 IFQ_DEQUEUE(&ifp->if_snd, m); 472 if (m == 0) 473 break; 474 475 /* 5 seconds to watch for failing to transmit */ 476 ifp->if_timer = 5; 477 ifp->if_opackets++; /* # of pkts */ 478 479 i = sc->sc_txnext; 480 buff = sc->sc_txbuf[i]; 481 tlen = gmac_put(sc, buff, m); 482 483 dp = &sc->sc_txlist[i]; 484 dp->cmd_hi = 0; 485 dp->address_hi = 0; 486 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 487 488 i++; 489 if (i == NTXBUF) 490 i = 0; 491 __asm volatile ("sync"); 492 493 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 494 sc->sc_txnext = i; 495 496 /* 497 * If BPF is listening on this interface, let it see the 498 * packet before we commit it to the wire. 499 */ 500 bpf_mtap(ifp, m); 501 m_freem(m); 502 503 i++; 504 if (i == NTXBUF) 505 i = 0; 506 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 507 ifp->if_flags |= IFF_OACTIVE; 508 break; 509 } 510 } 511 } 512 513 int 514 gmac_put(struct gmac_softc *sc, void *buff, struct mbuf *m) 515 { 516 int len, tlen = 0; 517 518 for (; m; m = m->m_next) { 519 len = m->m_len; 520 if (len == 0) 521 continue; 522 memcpy(buff, mtod(m, void *), len); 523 buff += len; 524 tlen += len; 525 } 526 if (tlen > 2048) 527 panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname); 528 529 return tlen; 530 } 531 532 void 533 gmac_reset(struct gmac_softc *sc) 534 { 535 int i, s; 536 537 s = splnet(); 538 539 gmac_stop_txdma(sc); 540 gmac_stop_rxdma(sc); 541 542 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 543 for (i = 10; i > 0; i--) { 544 delay(300000); /* XXX long delay */ 545 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 546 break; 547 } 548 if (i == 0) 549 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 550 551 sc->sc_txnext = 0; 552 sc->sc_rxlast = 0; 553 for (i = 0; i < NRXBUF; i++) 554 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 555 __asm volatile ("sync"); 556 557 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 558 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 559 vtophys((vaddr_t)sc->sc_txlist)); 560 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 561 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 562 vtophys((vaddr_t)sc->sc_rxlist)); 563 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 564 565 splx(s); 566 } 567 568 void 569 gmac_stop(struct gmac_softc *sc) 570 { 571 struct ifnet *ifp = &sc->sc_if; 572 int s; 573 574 s = splnet(); 575 576 callout_stop(&sc->sc_tick_ch); 577 mii_down(&sc->sc_mii); 578 579 gmac_stop_txdma(sc); 580 gmac_stop_rxdma(sc); 581 582 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 583 584 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 585 ifp->if_timer = 0; 586 587 splx(s); 588 } 589 590 void 591 gmac_init_mac(struct gmac_softc *sc) 592 { 593 int i, tb; 594 char *laddr = sc->sc_laddr; 595 596 if ((mfpvr() >> 16) == MPC601) 597 tb = mfrtcl(); 598 else 599 tb = mftbl(); 600 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 601 602 /* init-mii */ 603 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 604 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 605 606 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 607 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 608 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 609 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 610 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 611 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 612 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 613 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 614 gmac_write_reg(sc, GMAC_PASIZE, 7); 615 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 616 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 617 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 618 619 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 620 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 621 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 622 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 623 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 624 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 625 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 626 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 627 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 628 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 629 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 630 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 631 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 632 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 633 634 for (i = 0; i < 0x6c; i += 4) 635 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 636 637 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 638 639 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 640 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 641 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 642 } else { 643 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 644 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 645 } 646 647 if (0) /* g-bit? */ 648 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 649 else 650 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 651 } 652 653 void 654 gmac_setladrf(struct gmac_softc *sc) 655 { 656 struct ifnet *ifp = &sc->sc_if; 657 struct ether_multi *enm; 658 struct ether_multistep step; 659 struct ethercom *ec = &sc->sc_ethercom; 660 u_int32_t crc; 661 u_int32_t hash[16]; 662 u_int v; 663 int i; 664 665 /* Clear hash table */ 666 for (i = 0; i < 16; i++) 667 hash[i] = 0; 668 669 /* Get current RX configuration */ 670 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 671 672 if ((ifp->if_flags & IFF_PROMISC) != 0) { 673 /* Turn on promiscuous mode; turn off the hash filter */ 674 v |= GMAC_RXMAC_PR; 675 v &= ~GMAC_RXMAC_HEN; 676 ifp->if_flags |= IFF_ALLMULTI; 677 goto chipit; 678 } 679 680 /* Turn off promiscuous mode; turn on the hash filter */ 681 v &= ~GMAC_RXMAC_PR; 682 v |= GMAC_RXMAC_HEN; 683 684 /* 685 * Set up multicast address filter by passing all multicast addresses 686 * through a crc generator, and then using the high order 8 bits as an 687 * index into the 256 bit logical address filter. The high order bit 688 * selects the word, while the rest of the bits select the bit within 689 * the word. 690 */ 691 692 ETHER_FIRST_MULTI(step, ec, enm); 693 while (enm != NULL) { 694 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 695 /* 696 * We must listen to a range of multicast addresses. 697 * For now, just accept all multicasts, rather than 698 * trying to set only those filter bits needed to match 699 * the range. (At this time, the only use of address 700 * ranges is for IP multicast routing, for which the 701 * range is big enough to require all bits set.) 702 */ 703 for (i = 0; i < 16; i++) 704 hash[i] = 0xffff; 705 ifp->if_flags |= IFF_ALLMULTI; 706 goto chipit; 707 } 708 709 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 710 711 /* Just want the 8 most significant bits. */ 712 crc >>= 24; 713 714 /* Set the corresponding bit in the filter. */ 715 hash[crc >> 4] |= 1 << (crc & 0xf); 716 717 ETHER_NEXT_MULTI(step, enm); 718 } 719 720 ifp->if_flags &= ~IFF_ALLMULTI; 721 722 chipit: 723 /* Now load the hash table into the chip */ 724 for (i = 0; i < 16; i++) 725 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 726 727 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 728 } 729 730 void 731 gmac_init(struct gmac_softc *sc) 732 { 733 struct ifnet *ifp = &sc->sc_if; 734 735 gmac_stop_txdma(sc); 736 gmac_stop_rxdma(sc); 737 738 gmac_init_mac(sc); 739 gmac_setladrf(sc); 740 741 gmac_start_txdma(sc); 742 gmac_start_rxdma(sc); 743 744 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 745 746 ifp->if_flags |= IFF_RUNNING; 747 ifp->if_flags &= ~IFF_OACTIVE; 748 ifp->if_timer = 0; 749 750 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 751 752 gmac_start(ifp); 753 } 754 755 int 756 gmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 757 { 758 struct gmac_softc *sc = ifp->if_softc; 759 struct ifaddr *ifa = (struct ifaddr *)data; 760 struct ifreq *ifr = (struct ifreq *)data; 761 int s, error = 0; 762 763 s = splnet(); 764 765 switch (cmd) { 766 767 case SIOCINITIFADDR: 768 ifp->if_flags |= IFF_UP; 769 770 gmac_init(sc); 771 switch (ifa->ifa_addr->sa_family) { 772 #ifdef INET 773 case AF_INET: 774 arp_ifinit(ifp, ifa); 775 break; 776 #endif 777 default: 778 break; 779 } 780 break; 781 782 case SIOCSIFFLAGS: 783 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 784 break; 785 /* XXX see the comment in ed_ioctl() about code re-use */ 786 if ((ifp->if_flags & IFF_UP) == 0 && 787 (ifp->if_flags & IFF_RUNNING) != 0) { 788 /* 789 * If interface is marked down and it is running, then 790 * stop it. 791 */ 792 gmac_stop(sc); 793 ifp->if_flags &= ~IFF_RUNNING; 794 } else if ((ifp->if_flags & IFF_UP) != 0 && 795 (ifp->if_flags & IFF_RUNNING) == 0) { 796 /* 797 * If interface is marked up and it is stopped, then 798 * start it. 799 */ 800 gmac_init(sc); 801 } else { 802 /* 803 * Reset the interface to pick up changes in any other 804 * flags that affect hardware registers. 805 */ 806 gmac_reset(sc); 807 gmac_init(sc); 808 } 809 #ifdef GMAC_DEBUG 810 if (ifp->if_flags & IFF_DEBUG) 811 sc->sc_flags |= GMAC_DEBUGFLAG; 812 #endif 813 break; 814 815 case SIOCADDMULTI: 816 case SIOCDELMULTI: 817 case SIOCGIFMEDIA: 818 case SIOCSIFMEDIA: 819 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 820 /* 821 * Multicast list has changed; set the hardware filter 822 * accordingly. 823 */ 824 if (ifp->if_flags & IFF_RUNNING) { 825 gmac_init(sc); 826 /* gmac_setladrf(sc); */ 827 } 828 error = 0; 829 } 830 break; 831 default: 832 error = ether_ioctl(ifp, cmd, data); 833 break; 834 } 835 836 splx(s); 837 return error; 838 } 839 840 void 841 gmac_watchdog(struct ifnet *ifp) 842 { 843 struct gmac_softc *sc = ifp->if_softc; 844 845 printf("%s: device timeout\n", ifp->if_xname); 846 ifp->if_oerrors++; 847 848 gmac_reset(sc); 849 gmac_init(sc); 850 } 851 852 int 853 gmac_mii_readreg(struct device *dev, int phy, int reg) 854 { 855 struct gmac_softc *sc = (void *)dev; 856 int i; 857 858 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 859 0x60020000 | (phy << 23) | (reg << 18)); 860 861 for (i = 1000; i >= 0; i -= 10) { 862 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 863 break; 864 delay(10); 865 } 866 if (i < 0) { 867 printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname); 868 return 0; 869 } 870 871 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 872 } 873 874 void 875 gmac_mii_writereg(struct device *dev, int phy, int reg, int val) 876 { 877 struct gmac_softc *sc = (void *)dev; 878 int i; 879 880 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 881 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 882 883 for (i = 1000; i >= 0; i -= 10) { 884 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 885 break; 886 delay(10); 887 } 888 if (i < 0) 889 printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname); 890 } 891 892 void 893 gmac_mii_statchg(struct device *dev) 894 { 895 struct gmac_softc *sc = (void *)dev; 896 897 gmac_stop_txdma(sc); 898 gmac_stop_rxdma(sc); 899 900 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 901 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 902 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 903 } else { 904 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 905 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 906 } 907 908 if (0) /* g-bit? */ 909 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 910 else 911 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 912 913 gmac_start_txdma(sc); 914 gmac_start_rxdma(sc); 915 } 916 917 void 918 gmac_mii_tick(void *v) 919 { 920 struct gmac_softc *sc = v; 921 int s; 922 923 s = splnet(); 924 mii_tick(&sc->sc_mii); 925 splx(s); 926 927 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 928 } 929