1 /* $NetBSD: if_gm.c,v 1.43 2014/03/29 19:28:29 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.43 2014/03/29 19:28:29 christos Exp $"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/device.h> 36 #include <sys/ioctl.h> 37 #include <sys/kernel.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 43 #include <sys/rnd.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/ofw/openfirm.h> 66 #include <macppc/dev/if_gmreg.h> 67 #include <machine/pio.h> 68 69 #define NTXBUF 4 70 #define NRXBUF 32 71 72 struct gmac_softc { 73 device_t sc_dev; 74 struct ethercom sc_ethercom; 75 vaddr_t sc_reg; 76 struct gmac_dma *sc_txlist; 77 struct gmac_dma *sc_rxlist; 78 int sc_txnext; 79 int sc_rxlast; 80 void *sc_txbuf[NTXBUF]; 81 void *sc_rxbuf[NRXBUF]; 82 struct mii_data sc_mii; 83 struct callout sc_tick_ch; 84 char sc_laddr[6]; 85 86 krndsource_t sc_rnd_source; /* random source */ 87 }; 88 89 #define sc_if sc_ethercom.ec_if 90 91 int gmac_match(device_t, cfdata_t, void *); 92 void gmac_attach(device_t, device_t, void *); 93 94 static inline u_int gmac_read_reg(struct gmac_softc *, int); 95 static inline void gmac_write_reg(struct gmac_softc *, int, u_int); 96 97 static inline void gmac_start_txdma(struct gmac_softc *); 98 static inline void gmac_start_rxdma(struct gmac_softc *); 99 static inline void gmac_stop_txdma(struct gmac_softc *); 100 static inline void gmac_stop_rxdma(struct gmac_softc *); 101 102 int gmac_intr(void *); 103 void gmac_tint(struct gmac_softc *); 104 void gmac_rint(struct gmac_softc *); 105 struct mbuf * gmac_get(struct gmac_softc *, void *, int); 106 void gmac_start(struct ifnet *); 107 int gmac_put(struct gmac_softc *, void *, struct mbuf *); 108 109 void gmac_stop(struct gmac_softc *); 110 void gmac_reset(struct gmac_softc *); 111 void gmac_init(struct gmac_softc *); 112 void gmac_init_mac(struct gmac_softc *); 113 void gmac_setladrf(struct gmac_softc *); 114 115 int gmac_ioctl(struct ifnet *, u_long, void *); 116 void gmac_watchdog(struct ifnet *); 117 118 int gmac_mii_readreg(device_t, int, int); 119 void gmac_mii_writereg(device_t, int, int, int); 120 void gmac_mii_statchg(struct ifnet *); 121 void gmac_mii_tick(void *); 122 123 CFATTACH_DECL_NEW(gm, sizeof(struct gmac_softc), 124 gmac_match, gmac_attach, NULL, NULL); 125 126 int 127 gmac_match(device_t parent, cfdata_t match, void *aux) 128 { 129 struct pci_attach_args *pa = aux; 130 131 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 132 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 134 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 135 return 1; 136 137 return 0; 138 } 139 140 void 141 gmac_attach(device_t parent, device_t self, void *aux) 142 { 143 struct gmac_softc * const sc = device_private(self); 144 struct pci_attach_args * const pa = aux; 145 struct ifnet * const ifp = &sc->sc_if; 146 struct mii_data * const mii = &sc->sc_mii; 147 pci_intr_handle_t ih; 148 const char *intrstr = NULL; 149 const char * const xname = device_xname(self); 150 int node, i; 151 char *p; 152 struct gmac_dma *dp; 153 u_int32_t reg[10]; 154 u_char laddr[6]; 155 char buf[PCI_INTRSTR_LEN]; 156 157 sc->sc_dev = self; 158 159 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 160 if (node == 0) { 161 printf(": cannot find gmac node\n"); 162 return; 163 } 164 165 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 166 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 167 168 memcpy(sc->sc_laddr, laddr, sizeof laddr); 169 sc->sc_reg = reg[2]; 170 171 if (pci_intr_map(pa, &ih)) { 172 printf(": unable to map interrupt\n"); 173 return; 174 } 175 intrstr = pci_intr_string(pa->pa_pc, ih, buf, sizeof(buf)); 176 177 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 178 printf(": unable to establish interrupt"); 179 if (intrstr) 180 printf(" at %s", intrstr); 181 printf("\n"); 182 return; 183 } 184 185 /* Setup packet buffers and DMA descriptors. */ 186 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 187 if (p == NULL) { 188 printf(": cannot malloc buffers\n"); 189 return; 190 } 191 p = (void *)roundup((vaddr_t)p, 0x800); 192 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 193 194 sc->sc_rxlist = (void *)p; 195 p += 0x800; 196 sc->sc_txlist = (void *)p; 197 p += 0x800; 198 199 dp = sc->sc_rxlist; 200 for (i = 0; i < NRXBUF; i++) { 201 sc->sc_rxbuf[i] = p; 202 dp->address = htole32(vtophys((vaddr_t)p)); 203 dp->cmd = htole32(GMAC_OWN); 204 dp++; 205 p += 2048; 206 } 207 208 dp = sc->sc_txlist; 209 for (i = 0; i < NTXBUF; i++) { 210 sc->sc_txbuf[i] = p; 211 dp->address = htole32(vtophys((vaddr_t)p)); 212 dp++; 213 p += 2048; 214 } 215 216 aprint_normal(": Ethernet address %s\n", ether_sprintf(laddr)); 217 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 218 219 callout_init(&sc->sc_tick_ch, 0); 220 221 gmac_reset(sc); 222 gmac_init_mac(sc); 223 224 memcpy(ifp->if_xname, xname, IFNAMSIZ); 225 ifp->if_softc = sc; 226 ifp->if_ioctl = gmac_ioctl; 227 ifp->if_start = gmac_start; 228 ifp->if_watchdog = gmac_watchdog; 229 ifp->if_flags = 230 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 231 IFQ_SET_READY(&ifp->if_snd); 232 233 mii->mii_ifp = ifp; 234 mii->mii_readreg = gmac_mii_readreg; 235 mii->mii_writereg = gmac_mii_writereg; 236 mii->mii_statchg = gmac_mii_statchg; 237 238 sc->sc_ethercom.ec_mii = mii; 239 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 240 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 241 242 /* Choose a default media. */ 243 if (LIST_FIRST(&mii->mii_phys) == NULL) { 244 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 245 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 246 } else 247 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 248 249 if_attach(ifp); 250 ether_ifattach(ifp, laddr); 251 rnd_attach_source(&sc->sc_rnd_source, xname, RND_TYPE_NET, 0); 252 } 253 254 u_int 255 gmac_read_reg(struct gmac_softc *sc, int reg) 256 { 257 return in32rb(sc->sc_reg + reg); 258 } 259 260 void 261 gmac_write_reg(struct gmac_softc *sc, int reg, u_int val) 262 { 263 out32rb(sc->sc_reg + reg, val); 264 } 265 266 void 267 gmac_start_txdma(struct gmac_softc *sc) 268 { 269 u_int x; 270 271 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 272 x |= 1; 273 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 274 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 275 x |= 1; 276 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 277 } 278 279 void 280 gmac_start_rxdma(struct gmac_softc *sc) 281 { 282 u_int x; 283 284 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 285 x |= 1; 286 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 287 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 288 x |= 1; 289 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 290 } 291 292 void 293 gmac_stop_txdma(struct gmac_softc *sc) 294 { 295 u_int x; 296 297 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 298 x &= ~1; 299 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 300 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 301 x &= ~1; 302 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 303 } 304 305 void 306 gmac_stop_rxdma(struct gmac_softc *sc) 307 { 308 u_int x; 309 310 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 311 x &= ~1; 312 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 313 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 314 x &= ~1; 315 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 316 } 317 318 int 319 gmac_intr(void *v) 320 { 321 struct gmac_softc *sc = v; 322 u_int status; 323 324 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 325 if (status == 0) 326 return 0; 327 328 if (status & GMAC_INT_RXDONE) 329 gmac_rint(sc); 330 331 if (status & GMAC_INT_TXEMPTY) 332 gmac_tint(sc); 333 334 rnd_add_uint32(&sc->sc_rnd_source, status); 335 return 1; 336 } 337 338 void 339 gmac_tint(struct gmac_softc *sc) 340 { 341 struct ifnet *ifp = &sc->sc_if; 342 343 ifp->if_flags &= ~IFF_OACTIVE; 344 ifp->if_timer = 0; 345 gmac_start(ifp); 346 } 347 348 void 349 gmac_rint(struct gmac_softc *sc) 350 { 351 struct ifnet *ifp = &sc->sc_if; 352 volatile struct gmac_dma *dp; 353 struct mbuf *m; 354 int i, j, len; 355 u_int cmd; 356 357 for (i = sc->sc_rxlast;; i++) { 358 if (i == NRXBUF) 359 i = 0; 360 361 dp = &sc->sc_rxlist[i]; 362 cmd = le32toh(dp->cmd); 363 if (cmd & GMAC_OWN) 364 break; 365 len = (cmd >> 16) & GMAC_LEN_MASK; 366 len -= 4; /* CRC */ 367 368 if (le32toh(dp->cmd_hi) & 0x40000000) { 369 ifp->if_ierrors++; 370 goto next; 371 } 372 373 m = gmac_get(sc, sc->sc_rxbuf[i], len); 374 if (m == NULL) { 375 ifp->if_ierrors++; 376 goto next; 377 } 378 379 /* 380 * Check if there's a BPF listener on this interface. 381 * If so, hand off the raw packet to BPF. 382 */ 383 bpf_mtap(ifp, m); 384 (*ifp->if_input)(ifp, m); 385 ifp->if_ipackets++; 386 387 next: 388 dp->cmd_hi = 0; 389 __asm volatile ("sync"); 390 dp->cmd = htole32(GMAC_OWN); 391 } 392 sc->sc_rxlast = i; 393 394 /* XXX Make sure free buffers have GMAC_OWN. */ 395 i++; 396 for (j = 1; j < NRXBUF; j++) { 397 if (i == NRXBUF) 398 i = 0; 399 dp = &sc->sc_rxlist[i++]; 400 dp->cmd = htole32(GMAC_OWN); 401 } 402 } 403 404 struct mbuf * 405 gmac_get(struct gmac_softc *sc, void *pkt, int totlen) 406 { 407 struct mbuf *m; 408 struct mbuf *top, **mp; 409 int len; 410 411 MGETHDR(m, M_DONTWAIT, MT_DATA); 412 if (m == 0) 413 return 0; 414 m->m_pkthdr.rcvif = &sc->sc_if; 415 m->m_pkthdr.len = totlen; 416 len = MHLEN; 417 top = 0; 418 mp = ⊤ 419 420 while (totlen > 0) { 421 if (top) { 422 MGET(m, M_DONTWAIT, MT_DATA); 423 if (m == 0) { 424 m_freem(top); 425 return 0; 426 } 427 len = MLEN; 428 } 429 if (totlen >= MINCLSIZE) { 430 MCLGET(m, M_DONTWAIT); 431 if ((m->m_flags & M_EXT) == 0) { 432 m_free(m); 433 m_freem(top); 434 return 0; 435 } 436 len = MCLBYTES; 437 } 438 m->m_len = len = min(totlen, len); 439 memcpy(mtod(m, void *), pkt, len); 440 pkt += len; 441 totlen -= len; 442 *mp = m; 443 mp = &m->m_next; 444 } 445 446 return top; 447 } 448 449 void 450 gmac_start(struct ifnet *ifp) 451 { 452 struct gmac_softc *sc = ifp->if_softc; 453 struct mbuf *m; 454 void *buff; 455 int i, tlen; 456 volatile struct gmac_dma *dp; 457 458 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 459 return; 460 461 for (;;) { 462 if (ifp->if_flags & IFF_OACTIVE) 463 break; 464 465 IFQ_DEQUEUE(&ifp->if_snd, m); 466 if (m == 0) 467 break; 468 469 /* 5 seconds to watch for failing to transmit */ 470 ifp->if_timer = 5; 471 ifp->if_opackets++; /* # of pkts */ 472 473 i = sc->sc_txnext; 474 buff = sc->sc_txbuf[i]; 475 tlen = gmac_put(sc, buff, m); 476 477 dp = &sc->sc_txlist[i]; 478 dp->cmd_hi = 0; 479 dp->address_hi = 0; 480 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 481 482 i++; 483 if (i == NTXBUF) 484 i = 0; 485 __asm volatile ("sync"); 486 487 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 488 sc->sc_txnext = i; 489 490 /* 491 * If BPF is listening on this interface, let it see the 492 * packet before we commit it to the wire. 493 */ 494 bpf_mtap(ifp, m); 495 m_freem(m); 496 497 i++; 498 if (i == NTXBUF) 499 i = 0; 500 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 501 ifp->if_flags |= IFF_OACTIVE; 502 break; 503 } 504 } 505 } 506 507 int 508 gmac_put(struct gmac_softc *sc, void *buff, struct mbuf *m) 509 { 510 int len, tlen = 0; 511 512 for (; m; m = m->m_next) { 513 len = m->m_len; 514 if (len == 0) 515 continue; 516 memcpy(buff, mtod(m, void *), len); 517 buff += len; 518 tlen += len; 519 } 520 if (tlen > 2048) 521 panic("%s: gmac_put packet overflow", device_xname(sc->sc_dev)); 522 523 return tlen; 524 } 525 526 void 527 gmac_reset(struct gmac_softc *sc) 528 { 529 int i, s; 530 531 s = splnet(); 532 533 gmac_stop_txdma(sc); 534 gmac_stop_rxdma(sc); 535 536 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 537 for (i = 10; i > 0; i--) { 538 delay(300000); /* XXX long delay */ 539 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 540 break; 541 } 542 if (i == 0) 543 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 544 545 sc->sc_txnext = 0; 546 sc->sc_rxlast = 0; 547 for (i = 0; i < NRXBUF; i++) 548 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 549 __asm volatile ("sync"); 550 551 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 552 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 553 vtophys((vaddr_t)sc->sc_txlist)); 554 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 555 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 556 vtophys((vaddr_t)sc->sc_rxlist)); 557 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 558 559 splx(s); 560 } 561 562 void 563 gmac_stop(struct gmac_softc *sc) 564 { 565 struct ifnet *ifp = &sc->sc_if; 566 int s; 567 568 s = splnet(); 569 570 callout_stop(&sc->sc_tick_ch); 571 mii_down(&sc->sc_mii); 572 573 gmac_stop_txdma(sc); 574 gmac_stop_rxdma(sc); 575 576 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 577 578 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 579 ifp->if_timer = 0; 580 581 splx(s); 582 } 583 584 void 585 gmac_init_mac(struct gmac_softc *sc) 586 { 587 int i, tb; 588 char *laddr = sc->sc_laddr; 589 590 if ((mfpvr() >> 16) == MPC601) 591 tb = mfrtcl(); 592 else 593 tb = mftbl(); 594 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 595 596 /* init-mii */ 597 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 598 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 599 600 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 601 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 602 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 603 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 604 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 605 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 606 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 607 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 608 gmac_write_reg(sc, GMAC_PASIZE, 7); 609 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 610 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 611 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 612 613 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 614 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 615 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 616 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 617 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 618 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 619 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 620 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 621 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 622 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 623 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 624 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 625 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 626 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 627 628 for (i = 0; i < 0x6c; i += 4) 629 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 630 631 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 632 633 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 634 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 635 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 636 } else { 637 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 638 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 639 } 640 641 if (0) /* g-bit? */ 642 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 643 else 644 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 645 } 646 647 void 648 gmac_setladrf(struct gmac_softc *sc) 649 { 650 struct ifnet *ifp = &sc->sc_if; 651 struct ether_multi *enm; 652 struct ether_multistep step; 653 struct ethercom *ec = &sc->sc_ethercom; 654 u_int32_t crc; 655 u_int32_t hash[16]; 656 u_int v; 657 int i; 658 659 /* Clear hash table */ 660 for (i = 0; i < 16; i++) 661 hash[i] = 0; 662 663 /* Get current RX configuration */ 664 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 665 666 if ((ifp->if_flags & IFF_PROMISC) != 0) { 667 /* Turn on promiscuous mode; turn off the hash filter */ 668 v |= GMAC_RXMAC_PR; 669 v &= ~GMAC_RXMAC_HEN; 670 ifp->if_flags |= IFF_ALLMULTI; 671 goto chipit; 672 } 673 674 /* Turn off promiscuous mode; turn on the hash filter */ 675 v &= ~GMAC_RXMAC_PR; 676 v |= GMAC_RXMAC_HEN; 677 678 /* 679 * Set up multicast address filter by passing all multicast addresses 680 * through a crc generator, and then using the high order 8 bits as an 681 * index into the 256 bit logical address filter. The high order bit 682 * selects the word, while the rest of the bits select the bit within 683 * the word. 684 */ 685 686 ETHER_FIRST_MULTI(step, ec, enm); 687 while (enm != NULL) { 688 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 689 /* 690 * We must listen to a range of multicast addresses. 691 * For now, just accept all multicasts, rather than 692 * trying to set only those filter bits needed to match 693 * the range. (At this time, the only use of address 694 * ranges is for IP multicast routing, for which the 695 * range is big enough to require all bits set.) 696 */ 697 for (i = 0; i < 16; i++) 698 hash[i] = 0xffff; 699 ifp->if_flags |= IFF_ALLMULTI; 700 goto chipit; 701 } 702 703 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 704 705 /* Just want the 8 most significant bits. */ 706 crc >>= 24; 707 708 /* Set the corresponding bit in the filter. */ 709 hash[crc >> 4] |= 1 << (crc & 0xf); 710 711 ETHER_NEXT_MULTI(step, enm); 712 } 713 714 ifp->if_flags &= ~IFF_ALLMULTI; 715 716 chipit: 717 /* Now load the hash table into the chip */ 718 for (i = 0; i < 16; i++) 719 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 720 721 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 722 } 723 724 void 725 gmac_init(struct gmac_softc *sc) 726 { 727 struct ifnet *ifp = &sc->sc_if; 728 729 gmac_stop_txdma(sc); 730 gmac_stop_rxdma(sc); 731 732 gmac_init_mac(sc); 733 gmac_setladrf(sc); 734 735 gmac_start_txdma(sc); 736 gmac_start_rxdma(sc); 737 738 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 739 740 ifp->if_flags |= IFF_RUNNING; 741 ifp->if_flags &= ~IFF_OACTIVE; 742 ifp->if_timer = 0; 743 744 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 745 746 gmac_start(ifp); 747 } 748 749 int 750 gmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 751 { 752 struct gmac_softc *sc = ifp->if_softc; 753 struct ifaddr *ifa = (struct ifaddr *)data; 754 struct ifreq *ifr = (struct ifreq *)data; 755 int s, error = 0; 756 757 s = splnet(); 758 759 switch (cmd) { 760 761 case SIOCINITIFADDR: 762 ifp->if_flags |= IFF_UP; 763 764 gmac_init(sc); 765 switch (ifa->ifa_addr->sa_family) { 766 #ifdef INET 767 case AF_INET: 768 arp_ifinit(ifp, ifa); 769 break; 770 #endif 771 default: 772 break; 773 } 774 break; 775 776 case SIOCSIFFLAGS: 777 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 778 break; 779 /* XXX see the comment in ed_ioctl() about code re-use */ 780 if ((ifp->if_flags & IFF_UP) == 0 && 781 (ifp->if_flags & IFF_RUNNING) != 0) { 782 /* 783 * If interface is marked down and it is running, then 784 * stop it. 785 */ 786 gmac_stop(sc); 787 ifp->if_flags &= ~IFF_RUNNING; 788 } else if ((ifp->if_flags & IFF_UP) != 0 && 789 (ifp->if_flags & IFF_RUNNING) == 0) { 790 /* 791 * If interface is marked up and it is stopped, then 792 * start it. 793 */ 794 gmac_init(sc); 795 } else { 796 /* 797 * Reset the interface to pick up changes in any other 798 * flags that affect hardware registers. 799 */ 800 gmac_reset(sc); 801 gmac_init(sc); 802 } 803 #ifdef GMAC_DEBUG 804 if (ifp->if_flags & IFF_DEBUG) 805 sc->sc_flags |= GMAC_DEBUGFLAG; 806 #endif 807 break; 808 809 case SIOCADDMULTI: 810 case SIOCDELMULTI: 811 case SIOCGIFMEDIA: 812 case SIOCSIFMEDIA: 813 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 814 /* 815 * Multicast list has changed; set the hardware filter 816 * accordingly. 817 */ 818 if (ifp->if_flags & IFF_RUNNING) { 819 gmac_init(sc); 820 /* gmac_setladrf(sc); */ 821 } 822 error = 0; 823 } 824 break; 825 default: 826 error = ether_ioctl(ifp, cmd, data); 827 break; 828 } 829 830 splx(s); 831 return error; 832 } 833 834 void 835 gmac_watchdog(struct ifnet *ifp) 836 { 837 struct gmac_softc *sc = ifp->if_softc; 838 839 printf("%s: device timeout\n", ifp->if_xname); 840 ifp->if_oerrors++; 841 842 gmac_reset(sc); 843 gmac_init(sc); 844 } 845 846 int 847 gmac_mii_readreg(device_t self, int phy, int reg) 848 { 849 struct gmac_softc *sc = device_private(self); 850 int i; 851 852 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 853 0x60020000 | (phy << 23) | (reg << 18)); 854 855 for (i = 1000; i >= 0; i -= 10) { 856 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 857 break; 858 delay(10); 859 } 860 if (i < 0) { 861 aprint_error_dev(sc->sc_dev, "gmac_mii_readreg: timeout\n"); 862 return 0; 863 } 864 865 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 866 } 867 868 void 869 gmac_mii_writereg(device_t self, int phy, int reg, int val) 870 { 871 struct gmac_softc *sc = device_private(self); 872 int i; 873 874 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 875 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 876 877 for (i = 1000; i >= 0; i -= 10) { 878 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 879 break; 880 delay(10); 881 } 882 if (i < 0) 883 aprint_error_dev(sc->sc_dev, "gmac_mii_writereg: timeout\n"); 884 } 885 886 void 887 gmac_mii_statchg(struct ifnet *ifp) 888 { 889 struct gmac_softc *sc = ifp->if_softc; 890 891 gmac_stop_txdma(sc); 892 gmac_stop_rxdma(sc); 893 894 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 895 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 896 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 897 } else { 898 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 899 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 900 } 901 902 if (0) /* g-bit? */ 903 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 904 else 905 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 906 907 gmac_start_txdma(sc); 908 gmac_start_rxdma(sc); 909 } 910 911 void 912 gmac_mii_tick(void *v) 913 { 914 struct gmac_softc *sc = v; 915 int s; 916 917 s = splnet(); 918 mii_tick(&sc->sc_mii); 919 splx(s); 920 921 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 922 } 923