1 /* $NetBSD: if_gm.c,v 1.39 2011/06/18 08:08:28 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.39 2011/06/18 08:08:28 matt Exp $"); 31 32 #include "opt_inet.h" 33 #include "rnd.h" 34 35 #include <sys/param.h> 36 #include <sys/device.h> 37 #include <sys/ioctl.h> 38 #include <sys/kernel.h> 39 #include <sys/mbuf.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/callout.h> 43 44 #if NRND > 0 45 #include <sys/rnd.h> 46 #endif 47 48 #include <uvm/uvm_extern.h> 49 50 #include <net/if.h> 51 #include <net/if_ether.h> 52 #include <net/if_media.h> 53 54 #include <net/bpf.h> 55 56 #ifdef INET 57 #include <netinet/in.h> 58 #include <netinet/if_inarp.h> 59 #endif 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcidevs.h> 67 68 #include <dev/ofw/openfirm.h> 69 #include <macppc/dev/if_gmreg.h> 70 #include <machine/pio.h> 71 72 #define NTXBUF 4 73 #define NRXBUF 32 74 75 struct gmac_softc { 76 device_t sc_dev; 77 struct ethercom sc_ethercom; 78 vaddr_t sc_reg; 79 struct gmac_dma *sc_txlist; 80 struct gmac_dma *sc_rxlist; 81 int sc_txnext; 82 int sc_rxlast; 83 void *sc_txbuf[NTXBUF]; 84 void *sc_rxbuf[NRXBUF]; 85 struct mii_data sc_mii; 86 struct callout sc_tick_ch; 87 char sc_laddr[6]; 88 89 #if NRND > 0 90 rndsource_element_t sc_rnd_source; /* random source */ 91 #endif 92 }; 93 94 #define sc_if sc_ethercom.ec_if 95 96 int gmac_match(device_t, cfdata_t, void *); 97 void gmac_attach(device_t, device_t, void *); 98 99 static inline u_int gmac_read_reg(struct gmac_softc *, int); 100 static inline void gmac_write_reg(struct gmac_softc *, int, u_int); 101 102 static inline void gmac_start_txdma(struct gmac_softc *); 103 static inline void gmac_start_rxdma(struct gmac_softc *); 104 static inline void gmac_stop_txdma(struct gmac_softc *); 105 static inline void gmac_stop_rxdma(struct gmac_softc *); 106 107 int gmac_intr(void *); 108 void gmac_tint(struct gmac_softc *); 109 void gmac_rint(struct gmac_softc *); 110 struct mbuf * gmac_get(struct gmac_softc *, void *, int); 111 void gmac_start(struct ifnet *); 112 int gmac_put(struct gmac_softc *, void *, struct mbuf *); 113 114 void gmac_stop(struct gmac_softc *); 115 void gmac_reset(struct gmac_softc *); 116 void gmac_init(struct gmac_softc *); 117 void gmac_init_mac(struct gmac_softc *); 118 void gmac_setladrf(struct gmac_softc *); 119 120 int gmac_ioctl(struct ifnet *, u_long, void *); 121 void gmac_watchdog(struct ifnet *); 122 123 int gmac_mii_readreg(device_t, int, int); 124 void gmac_mii_writereg(device_t, int, int, int); 125 void gmac_mii_statchg(device_t); 126 void gmac_mii_tick(void *); 127 128 CFATTACH_DECL_NEW(gm, sizeof(struct gmac_softc), 129 gmac_match, gmac_attach, NULL, NULL); 130 131 int 132 gmac_match(device_t parent, cfdata_t match, void *aux) 133 { 134 struct pci_attach_args *pa = aux; 135 136 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 137 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 138 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 139 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 140 return 1; 141 142 return 0; 143 } 144 145 void 146 gmac_attach(device_t parent, device_t self, void *aux) 147 { 148 struct gmac_softc * const sc = device_private(self); 149 struct pci_attach_args * const pa = aux; 150 struct ifnet * const ifp = &sc->sc_if; 151 struct mii_data * const mii = &sc->sc_mii; 152 pci_intr_handle_t ih; 153 const char *intrstr = NULL; 154 const char * const xname = device_xname(self); 155 int node, i; 156 char *p; 157 struct gmac_dma *dp; 158 u_int32_t reg[10]; 159 u_char laddr[6]; 160 161 sc->sc_dev = self; 162 163 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 164 if (node == 0) { 165 printf(": cannot find gmac node\n"); 166 return; 167 } 168 169 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 170 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 171 172 memcpy(sc->sc_laddr, laddr, sizeof laddr); 173 sc->sc_reg = reg[2]; 174 175 if (pci_intr_map(pa, &ih)) { 176 printf(": unable to map interrupt\n"); 177 return; 178 } 179 intrstr = pci_intr_string(pa->pa_pc, ih); 180 181 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 182 printf(": unable to establish interrupt"); 183 if (intrstr) 184 printf(" at %s", intrstr); 185 printf("\n"); 186 return; 187 } 188 189 /* Setup packet buffers and DMA descriptors. */ 190 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 191 if (p == NULL) { 192 printf(": cannot malloc buffers\n"); 193 return; 194 } 195 p = (void *)roundup((vaddr_t)p, 0x800); 196 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 197 198 sc->sc_rxlist = (void *)p; 199 p += 0x800; 200 sc->sc_txlist = (void *)p; 201 p += 0x800; 202 203 dp = sc->sc_rxlist; 204 for (i = 0; i < NRXBUF; i++) { 205 sc->sc_rxbuf[i] = p; 206 dp->address = htole32(vtophys((vaddr_t)p)); 207 dp->cmd = htole32(GMAC_OWN); 208 dp++; 209 p += 2048; 210 } 211 212 dp = sc->sc_txlist; 213 for (i = 0; i < NTXBUF; i++) { 214 sc->sc_txbuf[i] = p; 215 dp->address = htole32(vtophys((vaddr_t)p)); 216 dp++; 217 p += 2048; 218 } 219 220 aprint_normal(": Ethernet address %s\n", ether_sprintf(laddr)); 221 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 222 223 callout_init(&sc->sc_tick_ch, 0); 224 225 gmac_reset(sc); 226 gmac_init_mac(sc); 227 228 memcpy(ifp->if_xname, xname, IFNAMSIZ); 229 ifp->if_softc = sc; 230 ifp->if_ioctl = gmac_ioctl; 231 ifp->if_start = gmac_start; 232 ifp->if_watchdog = gmac_watchdog; 233 ifp->if_flags = 234 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 235 IFQ_SET_READY(&ifp->if_snd); 236 237 mii->mii_ifp = ifp; 238 mii->mii_readreg = gmac_mii_readreg; 239 mii->mii_writereg = gmac_mii_writereg; 240 mii->mii_statchg = gmac_mii_statchg; 241 242 sc->sc_ethercom.ec_mii = mii; 243 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 244 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 245 246 /* Choose a default media. */ 247 if (LIST_FIRST(&mii->mii_phys) == NULL) { 248 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 249 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 250 } else 251 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 252 253 if_attach(ifp); 254 ether_ifattach(ifp, laddr); 255 #if NRND > 0 256 rnd_attach_source(&sc->sc_rnd_source, xname, RND_TYPE_NET, 0); 257 #endif 258 } 259 260 u_int 261 gmac_read_reg(struct gmac_softc *sc, int reg) 262 { 263 return in32rb(sc->sc_reg + reg); 264 } 265 266 void 267 gmac_write_reg(struct gmac_softc *sc, int reg, u_int val) 268 { 269 out32rb(sc->sc_reg + reg, val); 270 } 271 272 void 273 gmac_start_txdma(struct gmac_softc *sc) 274 { 275 u_int x; 276 277 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 278 x |= 1; 279 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 280 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 281 x |= 1; 282 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 283 } 284 285 void 286 gmac_start_rxdma(struct gmac_softc *sc) 287 { 288 u_int x; 289 290 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 291 x |= 1; 292 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 293 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 294 x |= 1; 295 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 296 } 297 298 void 299 gmac_stop_txdma(struct gmac_softc *sc) 300 { 301 u_int x; 302 303 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 304 x &= ~1; 305 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 306 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 307 x &= ~1; 308 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 309 } 310 311 void 312 gmac_stop_rxdma(struct gmac_softc *sc) 313 { 314 u_int x; 315 316 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 317 x &= ~1; 318 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 319 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 320 x &= ~1; 321 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 322 } 323 324 int 325 gmac_intr(void *v) 326 { 327 struct gmac_softc *sc = v; 328 u_int status; 329 330 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 331 if (status == 0) 332 return 0; 333 334 if (status & GMAC_INT_RXDONE) 335 gmac_rint(sc); 336 337 if (status & GMAC_INT_TXEMPTY) 338 gmac_tint(sc); 339 340 #if NRND > 0 341 rnd_add_uint32(&sc->sc_rnd_source, status); 342 #endif 343 return 1; 344 } 345 346 void 347 gmac_tint(struct gmac_softc *sc) 348 { 349 struct ifnet *ifp = &sc->sc_if; 350 351 ifp->if_flags &= ~IFF_OACTIVE; 352 ifp->if_timer = 0; 353 gmac_start(ifp); 354 } 355 356 void 357 gmac_rint(struct gmac_softc *sc) 358 { 359 struct ifnet *ifp = &sc->sc_if; 360 volatile struct gmac_dma *dp; 361 struct mbuf *m; 362 int i, j, len; 363 u_int cmd; 364 365 for (i = sc->sc_rxlast;; i++) { 366 if (i == NRXBUF) 367 i = 0; 368 369 dp = &sc->sc_rxlist[i]; 370 cmd = le32toh(dp->cmd); 371 if (cmd & GMAC_OWN) 372 break; 373 len = (cmd >> 16) & GMAC_LEN_MASK; 374 len -= 4; /* CRC */ 375 376 if (le32toh(dp->cmd_hi) & 0x40000000) { 377 ifp->if_ierrors++; 378 goto next; 379 } 380 381 m = gmac_get(sc, sc->sc_rxbuf[i], len); 382 if (m == NULL) { 383 ifp->if_ierrors++; 384 goto next; 385 } 386 387 /* 388 * Check if there's a BPF listener on this interface. 389 * If so, hand off the raw packet to BPF. 390 */ 391 bpf_mtap(ifp, m); 392 (*ifp->if_input)(ifp, m); 393 ifp->if_ipackets++; 394 395 next: 396 dp->cmd_hi = 0; 397 __asm volatile ("sync"); 398 dp->cmd = htole32(GMAC_OWN); 399 } 400 sc->sc_rxlast = i; 401 402 /* XXX Make sure free buffers have GMAC_OWN. */ 403 i++; 404 for (j = 1; j < NRXBUF; j++) { 405 if (i == NRXBUF) 406 i = 0; 407 dp = &sc->sc_rxlist[i++]; 408 dp->cmd = htole32(GMAC_OWN); 409 } 410 } 411 412 struct mbuf * 413 gmac_get(struct gmac_softc *sc, void *pkt, int totlen) 414 { 415 struct mbuf *m; 416 struct mbuf *top, **mp; 417 int len; 418 419 MGETHDR(m, M_DONTWAIT, MT_DATA); 420 if (m == 0) 421 return 0; 422 m->m_pkthdr.rcvif = &sc->sc_if; 423 m->m_pkthdr.len = totlen; 424 len = MHLEN; 425 top = 0; 426 mp = ⊤ 427 428 while (totlen > 0) { 429 if (top) { 430 MGET(m, M_DONTWAIT, MT_DATA); 431 if (m == 0) { 432 m_freem(top); 433 return 0; 434 } 435 len = MLEN; 436 } 437 if (totlen >= MINCLSIZE) { 438 MCLGET(m, M_DONTWAIT); 439 if ((m->m_flags & M_EXT) == 0) { 440 m_free(m); 441 m_freem(top); 442 return 0; 443 } 444 len = MCLBYTES; 445 } 446 m->m_len = len = min(totlen, len); 447 memcpy(mtod(m, void *), pkt, len); 448 pkt += len; 449 totlen -= len; 450 *mp = m; 451 mp = &m->m_next; 452 } 453 454 return top; 455 } 456 457 void 458 gmac_start(struct ifnet *ifp) 459 { 460 struct gmac_softc *sc = ifp->if_softc; 461 struct mbuf *m; 462 void *buff; 463 int i, tlen; 464 volatile struct gmac_dma *dp; 465 466 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 467 return; 468 469 for (;;) { 470 if (ifp->if_flags & IFF_OACTIVE) 471 break; 472 473 IFQ_DEQUEUE(&ifp->if_snd, m); 474 if (m == 0) 475 break; 476 477 /* 5 seconds to watch for failing to transmit */ 478 ifp->if_timer = 5; 479 ifp->if_opackets++; /* # of pkts */ 480 481 i = sc->sc_txnext; 482 buff = sc->sc_txbuf[i]; 483 tlen = gmac_put(sc, buff, m); 484 485 dp = &sc->sc_txlist[i]; 486 dp->cmd_hi = 0; 487 dp->address_hi = 0; 488 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 489 490 i++; 491 if (i == NTXBUF) 492 i = 0; 493 __asm volatile ("sync"); 494 495 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 496 sc->sc_txnext = i; 497 498 /* 499 * If BPF is listening on this interface, let it see the 500 * packet before we commit it to the wire. 501 */ 502 bpf_mtap(ifp, m); 503 m_freem(m); 504 505 i++; 506 if (i == NTXBUF) 507 i = 0; 508 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 509 ifp->if_flags |= IFF_OACTIVE; 510 break; 511 } 512 } 513 } 514 515 int 516 gmac_put(struct gmac_softc *sc, void *buff, struct mbuf *m) 517 { 518 int len, tlen = 0; 519 520 for (; m; m = m->m_next) { 521 len = m->m_len; 522 if (len == 0) 523 continue; 524 memcpy(buff, mtod(m, void *), len); 525 buff += len; 526 tlen += len; 527 } 528 if (tlen > 2048) 529 panic("%s: gmac_put packet overflow", device_xname(sc->sc_dev)); 530 531 return tlen; 532 } 533 534 void 535 gmac_reset(struct gmac_softc *sc) 536 { 537 int i, s; 538 539 s = splnet(); 540 541 gmac_stop_txdma(sc); 542 gmac_stop_rxdma(sc); 543 544 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 545 for (i = 10; i > 0; i--) { 546 delay(300000); /* XXX long delay */ 547 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 548 break; 549 } 550 if (i == 0) 551 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 552 553 sc->sc_txnext = 0; 554 sc->sc_rxlast = 0; 555 for (i = 0; i < NRXBUF; i++) 556 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 557 __asm volatile ("sync"); 558 559 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 560 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 561 vtophys((vaddr_t)sc->sc_txlist)); 562 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 563 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 564 vtophys((vaddr_t)sc->sc_rxlist)); 565 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 566 567 splx(s); 568 } 569 570 void 571 gmac_stop(struct gmac_softc *sc) 572 { 573 struct ifnet *ifp = &sc->sc_if; 574 int s; 575 576 s = splnet(); 577 578 callout_stop(&sc->sc_tick_ch); 579 mii_down(&sc->sc_mii); 580 581 gmac_stop_txdma(sc); 582 gmac_stop_rxdma(sc); 583 584 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 585 586 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 587 ifp->if_timer = 0; 588 589 splx(s); 590 } 591 592 void 593 gmac_init_mac(struct gmac_softc *sc) 594 { 595 int i, tb; 596 char *laddr = sc->sc_laddr; 597 598 if ((mfpvr() >> 16) == MPC601) 599 tb = mfrtcl(); 600 else 601 tb = mftbl(); 602 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 603 604 /* init-mii */ 605 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 606 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 607 608 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 609 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 610 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 611 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 612 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 613 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 614 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 615 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 616 gmac_write_reg(sc, GMAC_PASIZE, 7); 617 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 618 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 619 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 620 621 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 622 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 623 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 624 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 625 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 626 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 627 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 628 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 629 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 630 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 631 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 632 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 633 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 634 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 635 636 for (i = 0; i < 0x6c; i += 4) 637 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 638 639 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 640 641 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 642 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 643 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 644 } else { 645 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 646 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 647 } 648 649 if (0) /* g-bit? */ 650 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 651 else 652 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 653 } 654 655 void 656 gmac_setladrf(struct gmac_softc *sc) 657 { 658 struct ifnet *ifp = &sc->sc_if; 659 struct ether_multi *enm; 660 struct ether_multistep step; 661 struct ethercom *ec = &sc->sc_ethercom; 662 u_int32_t crc; 663 u_int32_t hash[16]; 664 u_int v; 665 int i; 666 667 /* Clear hash table */ 668 for (i = 0; i < 16; i++) 669 hash[i] = 0; 670 671 /* Get current RX configuration */ 672 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 673 674 if ((ifp->if_flags & IFF_PROMISC) != 0) { 675 /* Turn on promiscuous mode; turn off the hash filter */ 676 v |= GMAC_RXMAC_PR; 677 v &= ~GMAC_RXMAC_HEN; 678 ifp->if_flags |= IFF_ALLMULTI; 679 goto chipit; 680 } 681 682 /* Turn off promiscuous mode; turn on the hash filter */ 683 v &= ~GMAC_RXMAC_PR; 684 v |= GMAC_RXMAC_HEN; 685 686 /* 687 * Set up multicast address filter by passing all multicast addresses 688 * through a crc generator, and then using the high order 8 bits as an 689 * index into the 256 bit logical address filter. The high order bit 690 * selects the word, while the rest of the bits select the bit within 691 * the word. 692 */ 693 694 ETHER_FIRST_MULTI(step, ec, enm); 695 while (enm != NULL) { 696 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 697 /* 698 * We must listen to a range of multicast addresses. 699 * For now, just accept all multicasts, rather than 700 * trying to set only those filter bits needed to match 701 * the range. (At this time, the only use of address 702 * ranges is for IP multicast routing, for which the 703 * range is big enough to require all bits set.) 704 */ 705 for (i = 0; i < 16; i++) 706 hash[i] = 0xffff; 707 ifp->if_flags |= IFF_ALLMULTI; 708 goto chipit; 709 } 710 711 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 712 713 /* Just want the 8 most significant bits. */ 714 crc >>= 24; 715 716 /* Set the corresponding bit in the filter. */ 717 hash[crc >> 4] |= 1 << (crc & 0xf); 718 719 ETHER_NEXT_MULTI(step, enm); 720 } 721 722 ifp->if_flags &= ~IFF_ALLMULTI; 723 724 chipit: 725 /* Now load the hash table into the chip */ 726 for (i = 0; i < 16; i++) 727 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 728 729 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 730 } 731 732 void 733 gmac_init(struct gmac_softc *sc) 734 { 735 struct ifnet *ifp = &sc->sc_if; 736 737 gmac_stop_txdma(sc); 738 gmac_stop_rxdma(sc); 739 740 gmac_init_mac(sc); 741 gmac_setladrf(sc); 742 743 gmac_start_txdma(sc); 744 gmac_start_rxdma(sc); 745 746 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 747 748 ifp->if_flags |= IFF_RUNNING; 749 ifp->if_flags &= ~IFF_OACTIVE; 750 ifp->if_timer = 0; 751 752 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 753 754 gmac_start(ifp); 755 } 756 757 int 758 gmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 759 { 760 struct gmac_softc *sc = ifp->if_softc; 761 struct ifaddr *ifa = (struct ifaddr *)data; 762 struct ifreq *ifr = (struct ifreq *)data; 763 int s, error = 0; 764 765 s = splnet(); 766 767 switch (cmd) { 768 769 case SIOCINITIFADDR: 770 ifp->if_flags |= IFF_UP; 771 772 gmac_init(sc); 773 switch (ifa->ifa_addr->sa_family) { 774 #ifdef INET 775 case AF_INET: 776 arp_ifinit(ifp, ifa); 777 break; 778 #endif 779 default: 780 break; 781 } 782 break; 783 784 case SIOCSIFFLAGS: 785 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 786 break; 787 /* XXX see the comment in ed_ioctl() about code re-use */ 788 if ((ifp->if_flags & IFF_UP) == 0 && 789 (ifp->if_flags & IFF_RUNNING) != 0) { 790 /* 791 * If interface is marked down and it is running, then 792 * stop it. 793 */ 794 gmac_stop(sc); 795 ifp->if_flags &= ~IFF_RUNNING; 796 } else if ((ifp->if_flags & IFF_UP) != 0 && 797 (ifp->if_flags & IFF_RUNNING) == 0) { 798 /* 799 * If interface is marked up and it is stopped, then 800 * start it. 801 */ 802 gmac_init(sc); 803 } else { 804 /* 805 * Reset the interface to pick up changes in any other 806 * flags that affect hardware registers. 807 */ 808 gmac_reset(sc); 809 gmac_init(sc); 810 } 811 #ifdef GMAC_DEBUG 812 if (ifp->if_flags & IFF_DEBUG) 813 sc->sc_flags |= GMAC_DEBUGFLAG; 814 #endif 815 break; 816 817 case SIOCADDMULTI: 818 case SIOCDELMULTI: 819 case SIOCGIFMEDIA: 820 case SIOCSIFMEDIA: 821 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 822 /* 823 * Multicast list has changed; set the hardware filter 824 * accordingly. 825 */ 826 if (ifp->if_flags & IFF_RUNNING) { 827 gmac_init(sc); 828 /* gmac_setladrf(sc); */ 829 } 830 error = 0; 831 } 832 break; 833 default: 834 error = ether_ioctl(ifp, cmd, data); 835 break; 836 } 837 838 splx(s); 839 return error; 840 } 841 842 void 843 gmac_watchdog(struct ifnet *ifp) 844 { 845 struct gmac_softc *sc = ifp->if_softc; 846 847 printf("%s: device timeout\n", ifp->if_xname); 848 ifp->if_oerrors++; 849 850 gmac_reset(sc); 851 gmac_init(sc); 852 } 853 854 int 855 gmac_mii_readreg(device_t self, int phy, int reg) 856 { 857 struct gmac_softc *sc = device_private(self); 858 int i; 859 860 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 861 0x60020000 | (phy << 23) | (reg << 18)); 862 863 for (i = 1000; i >= 0; i -= 10) { 864 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 865 break; 866 delay(10); 867 } 868 if (i < 0) { 869 aprint_error_dev(sc->sc_dev, "gmac_mii_readreg: timeout\n"); 870 return 0; 871 } 872 873 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 874 } 875 876 void 877 gmac_mii_writereg(device_t self, int phy, int reg, int val) 878 { 879 struct gmac_softc *sc = device_private(self); 880 int i; 881 882 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 883 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 884 885 for (i = 1000; i >= 0; i -= 10) { 886 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 887 break; 888 delay(10); 889 } 890 if (i < 0) 891 aprint_error_dev(sc->sc_dev, "gmac_mii_writereg: timeout\n"); 892 } 893 894 void 895 gmac_mii_statchg(device_t self) 896 { 897 struct gmac_softc *sc = device_private(self); 898 899 gmac_stop_txdma(sc); 900 gmac_stop_rxdma(sc); 901 902 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 903 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 904 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 905 } else { 906 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 907 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 908 } 909 910 if (0) /* g-bit? */ 911 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 912 else 913 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 914 915 gmac_start_txdma(sc); 916 gmac_start_rxdma(sc); 917 } 918 919 void 920 gmac_mii_tick(void *v) 921 { 922 struct gmac_softc *sc = v; 923 int s; 924 925 s = splnet(); 926 mii_tick(&sc->sc_mii); 927 splx(s); 928 929 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 930 } 931