1 /* $NetBSD: if_gm.c,v 1.42 2012/07/22 14:32:51 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_gm.c,v 1.42 2012/07/22 14:32:51 matt Exp $"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/device.h> 36 #include <sys/ioctl.h> 37 #include <sys/kernel.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 43 #include <sys/rnd.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <net/if.h> 48 #include <net/if_ether.h> 49 #include <net/if_media.h> 50 51 #include <net/bpf.h> 52 53 #ifdef INET 54 #include <netinet/in.h> 55 #include <netinet/if_inarp.h> 56 #endif 57 58 #include <dev/mii/mii.h> 59 #include <dev/mii/miivar.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/ofw/openfirm.h> 66 #include <macppc/dev/if_gmreg.h> 67 #include <machine/pio.h> 68 69 #define NTXBUF 4 70 #define NRXBUF 32 71 72 struct gmac_softc { 73 device_t sc_dev; 74 struct ethercom sc_ethercom; 75 vaddr_t sc_reg; 76 struct gmac_dma *sc_txlist; 77 struct gmac_dma *sc_rxlist; 78 int sc_txnext; 79 int sc_rxlast; 80 void *sc_txbuf[NTXBUF]; 81 void *sc_rxbuf[NRXBUF]; 82 struct mii_data sc_mii; 83 struct callout sc_tick_ch; 84 char sc_laddr[6]; 85 86 krndsource_t sc_rnd_source; /* random source */ 87 }; 88 89 #define sc_if sc_ethercom.ec_if 90 91 int gmac_match(device_t, cfdata_t, void *); 92 void gmac_attach(device_t, device_t, void *); 93 94 static inline u_int gmac_read_reg(struct gmac_softc *, int); 95 static inline void gmac_write_reg(struct gmac_softc *, int, u_int); 96 97 static inline void gmac_start_txdma(struct gmac_softc *); 98 static inline void gmac_start_rxdma(struct gmac_softc *); 99 static inline void gmac_stop_txdma(struct gmac_softc *); 100 static inline void gmac_stop_rxdma(struct gmac_softc *); 101 102 int gmac_intr(void *); 103 void gmac_tint(struct gmac_softc *); 104 void gmac_rint(struct gmac_softc *); 105 struct mbuf * gmac_get(struct gmac_softc *, void *, int); 106 void gmac_start(struct ifnet *); 107 int gmac_put(struct gmac_softc *, void *, struct mbuf *); 108 109 void gmac_stop(struct gmac_softc *); 110 void gmac_reset(struct gmac_softc *); 111 void gmac_init(struct gmac_softc *); 112 void gmac_init_mac(struct gmac_softc *); 113 void gmac_setladrf(struct gmac_softc *); 114 115 int gmac_ioctl(struct ifnet *, u_long, void *); 116 void gmac_watchdog(struct ifnet *); 117 118 int gmac_mii_readreg(device_t, int, int); 119 void gmac_mii_writereg(device_t, int, int, int); 120 void gmac_mii_statchg(struct ifnet *); 121 void gmac_mii_tick(void *); 122 123 CFATTACH_DECL_NEW(gm, sizeof(struct gmac_softc), 124 gmac_match, gmac_attach, NULL, NULL); 125 126 int 127 gmac_match(device_t parent, cfdata_t match, void *aux) 128 { 129 struct pci_attach_args *pa = aux; 130 131 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 132 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC || 133 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC2 || 134 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC3)) 135 return 1; 136 137 return 0; 138 } 139 140 void 141 gmac_attach(device_t parent, device_t self, void *aux) 142 { 143 struct gmac_softc * const sc = device_private(self); 144 struct pci_attach_args * const pa = aux; 145 struct ifnet * const ifp = &sc->sc_if; 146 struct mii_data * const mii = &sc->sc_mii; 147 pci_intr_handle_t ih; 148 const char *intrstr = NULL; 149 const char * const xname = device_xname(self); 150 int node, i; 151 char *p; 152 struct gmac_dma *dp; 153 u_int32_t reg[10]; 154 u_char laddr[6]; 155 156 sc->sc_dev = self; 157 158 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 159 if (node == 0) { 160 printf(": cannot find gmac node\n"); 161 return; 162 } 163 164 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 165 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 166 167 memcpy(sc->sc_laddr, laddr, sizeof laddr); 168 sc->sc_reg = reg[2]; 169 170 if (pci_intr_map(pa, &ih)) { 171 printf(": unable to map interrupt\n"); 172 return; 173 } 174 intrstr = pci_intr_string(pa->pa_pc, ih); 175 176 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 177 printf(": unable to establish interrupt"); 178 if (intrstr) 179 printf(" at %s", intrstr); 180 printf("\n"); 181 return; 182 } 183 184 /* Setup packet buffers and DMA descriptors. */ 185 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 186 if (p == NULL) { 187 printf(": cannot malloc buffers\n"); 188 return; 189 } 190 p = (void *)roundup((vaddr_t)p, 0x800); 191 memset(p, 0, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 192 193 sc->sc_rxlist = (void *)p; 194 p += 0x800; 195 sc->sc_txlist = (void *)p; 196 p += 0x800; 197 198 dp = sc->sc_rxlist; 199 for (i = 0; i < NRXBUF; i++) { 200 sc->sc_rxbuf[i] = p; 201 dp->address = htole32(vtophys((vaddr_t)p)); 202 dp->cmd = htole32(GMAC_OWN); 203 dp++; 204 p += 2048; 205 } 206 207 dp = sc->sc_txlist; 208 for (i = 0; i < NTXBUF; i++) { 209 sc->sc_txbuf[i] = p; 210 dp->address = htole32(vtophys((vaddr_t)p)); 211 dp++; 212 p += 2048; 213 } 214 215 aprint_normal(": Ethernet address %s\n", ether_sprintf(laddr)); 216 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 217 218 callout_init(&sc->sc_tick_ch, 0); 219 220 gmac_reset(sc); 221 gmac_init_mac(sc); 222 223 memcpy(ifp->if_xname, xname, IFNAMSIZ); 224 ifp->if_softc = sc; 225 ifp->if_ioctl = gmac_ioctl; 226 ifp->if_start = gmac_start; 227 ifp->if_watchdog = gmac_watchdog; 228 ifp->if_flags = 229 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 230 IFQ_SET_READY(&ifp->if_snd); 231 232 mii->mii_ifp = ifp; 233 mii->mii_readreg = gmac_mii_readreg; 234 mii->mii_writereg = gmac_mii_writereg; 235 mii->mii_statchg = gmac_mii_statchg; 236 237 sc->sc_ethercom.ec_mii = mii; 238 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 239 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 240 241 /* Choose a default media. */ 242 if (LIST_FIRST(&mii->mii_phys) == NULL) { 243 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 244 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 245 } else 246 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 247 248 if_attach(ifp); 249 ether_ifattach(ifp, laddr); 250 rnd_attach_source(&sc->sc_rnd_source, xname, RND_TYPE_NET, 0); 251 } 252 253 u_int 254 gmac_read_reg(struct gmac_softc *sc, int reg) 255 { 256 return in32rb(sc->sc_reg + reg); 257 } 258 259 void 260 gmac_write_reg(struct gmac_softc *sc, int reg, u_int val) 261 { 262 out32rb(sc->sc_reg + reg, val); 263 } 264 265 void 266 gmac_start_txdma(struct gmac_softc *sc) 267 { 268 u_int x; 269 270 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 271 x |= 1; 272 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 273 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 274 x |= 1; 275 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 276 } 277 278 void 279 gmac_start_rxdma(struct gmac_softc *sc) 280 { 281 u_int x; 282 283 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 284 x |= 1; 285 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 286 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 287 x |= 1; 288 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 289 } 290 291 void 292 gmac_stop_txdma(struct gmac_softc *sc) 293 { 294 u_int x; 295 296 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 297 x &= ~1; 298 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 299 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 300 x &= ~1; 301 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 302 } 303 304 void 305 gmac_stop_rxdma(struct gmac_softc *sc) 306 { 307 u_int x; 308 309 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 310 x &= ~1; 311 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 312 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 313 x &= ~1; 314 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 315 } 316 317 int 318 gmac_intr(void *v) 319 { 320 struct gmac_softc *sc = v; 321 u_int status; 322 323 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 324 if (status == 0) 325 return 0; 326 327 if (status & GMAC_INT_RXDONE) 328 gmac_rint(sc); 329 330 if (status & GMAC_INT_TXEMPTY) 331 gmac_tint(sc); 332 333 rnd_add_uint32(&sc->sc_rnd_source, status); 334 return 1; 335 } 336 337 void 338 gmac_tint(struct gmac_softc *sc) 339 { 340 struct ifnet *ifp = &sc->sc_if; 341 342 ifp->if_flags &= ~IFF_OACTIVE; 343 ifp->if_timer = 0; 344 gmac_start(ifp); 345 } 346 347 void 348 gmac_rint(struct gmac_softc *sc) 349 { 350 struct ifnet *ifp = &sc->sc_if; 351 volatile struct gmac_dma *dp; 352 struct mbuf *m; 353 int i, j, len; 354 u_int cmd; 355 356 for (i = sc->sc_rxlast;; i++) { 357 if (i == NRXBUF) 358 i = 0; 359 360 dp = &sc->sc_rxlist[i]; 361 cmd = le32toh(dp->cmd); 362 if (cmd & GMAC_OWN) 363 break; 364 len = (cmd >> 16) & GMAC_LEN_MASK; 365 len -= 4; /* CRC */ 366 367 if (le32toh(dp->cmd_hi) & 0x40000000) { 368 ifp->if_ierrors++; 369 goto next; 370 } 371 372 m = gmac_get(sc, sc->sc_rxbuf[i], len); 373 if (m == NULL) { 374 ifp->if_ierrors++; 375 goto next; 376 } 377 378 /* 379 * Check if there's a BPF listener on this interface. 380 * If so, hand off the raw packet to BPF. 381 */ 382 bpf_mtap(ifp, m); 383 (*ifp->if_input)(ifp, m); 384 ifp->if_ipackets++; 385 386 next: 387 dp->cmd_hi = 0; 388 __asm volatile ("sync"); 389 dp->cmd = htole32(GMAC_OWN); 390 } 391 sc->sc_rxlast = i; 392 393 /* XXX Make sure free buffers have GMAC_OWN. */ 394 i++; 395 for (j = 1; j < NRXBUF; j++) { 396 if (i == NRXBUF) 397 i = 0; 398 dp = &sc->sc_rxlist[i++]; 399 dp->cmd = htole32(GMAC_OWN); 400 } 401 } 402 403 struct mbuf * 404 gmac_get(struct gmac_softc *sc, void *pkt, int totlen) 405 { 406 struct mbuf *m; 407 struct mbuf *top, **mp; 408 int len; 409 410 MGETHDR(m, M_DONTWAIT, MT_DATA); 411 if (m == 0) 412 return 0; 413 m->m_pkthdr.rcvif = &sc->sc_if; 414 m->m_pkthdr.len = totlen; 415 len = MHLEN; 416 top = 0; 417 mp = ⊤ 418 419 while (totlen > 0) { 420 if (top) { 421 MGET(m, M_DONTWAIT, MT_DATA); 422 if (m == 0) { 423 m_freem(top); 424 return 0; 425 } 426 len = MLEN; 427 } 428 if (totlen >= MINCLSIZE) { 429 MCLGET(m, M_DONTWAIT); 430 if ((m->m_flags & M_EXT) == 0) { 431 m_free(m); 432 m_freem(top); 433 return 0; 434 } 435 len = MCLBYTES; 436 } 437 m->m_len = len = min(totlen, len); 438 memcpy(mtod(m, void *), pkt, len); 439 pkt += len; 440 totlen -= len; 441 *mp = m; 442 mp = &m->m_next; 443 } 444 445 return top; 446 } 447 448 void 449 gmac_start(struct ifnet *ifp) 450 { 451 struct gmac_softc *sc = ifp->if_softc; 452 struct mbuf *m; 453 void *buff; 454 int i, tlen; 455 volatile struct gmac_dma *dp; 456 457 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 458 return; 459 460 for (;;) { 461 if (ifp->if_flags & IFF_OACTIVE) 462 break; 463 464 IFQ_DEQUEUE(&ifp->if_snd, m); 465 if (m == 0) 466 break; 467 468 /* 5 seconds to watch for failing to transmit */ 469 ifp->if_timer = 5; 470 ifp->if_opackets++; /* # of pkts */ 471 472 i = sc->sc_txnext; 473 buff = sc->sc_txbuf[i]; 474 tlen = gmac_put(sc, buff, m); 475 476 dp = &sc->sc_txlist[i]; 477 dp->cmd_hi = 0; 478 dp->address_hi = 0; 479 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 480 481 i++; 482 if (i == NTXBUF) 483 i = 0; 484 __asm volatile ("sync"); 485 486 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 487 sc->sc_txnext = i; 488 489 /* 490 * If BPF is listening on this interface, let it see the 491 * packet before we commit it to the wire. 492 */ 493 bpf_mtap(ifp, m); 494 m_freem(m); 495 496 i++; 497 if (i == NTXBUF) 498 i = 0; 499 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 500 ifp->if_flags |= IFF_OACTIVE; 501 break; 502 } 503 } 504 } 505 506 int 507 gmac_put(struct gmac_softc *sc, void *buff, struct mbuf *m) 508 { 509 int len, tlen = 0; 510 511 for (; m; m = m->m_next) { 512 len = m->m_len; 513 if (len == 0) 514 continue; 515 memcpy(buff, mtod(m, void *), len); 516 buff += len; 517 tlen += len; 518 } 519 if (tlen > 2048) 520 panic("%s: gmac_put packet overflow", device_xname(sc->sc_dev)); 521 522 return tlen; 523 } 524 525 void 526 gmac_reset(struct gmac_softc *sc) 527 { 528 int i, s; 529 530 s = splnet(); 531 532 gmac_stop_txdma(sc); 533 gmac_stop_rxdma(sc); 534 535 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 536 for (i = 10; i > 0; i--) { 537 delay(300000); /* XXX long delay */ 538 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 539 break; 540 } 541 if (i == 0) 542 aprint_error_dev(sc->sc_dev, "reset timeout\n"); 543 544 sc->sc_txnext = 0; 545 sc->sc_rxlast = 0; 546 for (i = 0; i < NRXBUF; i++) 547 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 548 __asm volatile ("sync"); 549 550 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 551 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 552 vtophys((vaddr_t)sc->sc_txlist)); 553 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 554 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 555 vtophys((vaddr_t)sc->sc_rxlist)); 556 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 557 558 splx(s); 559 } 560 561 void 562 gmac_stop(struct gmac_softc *sc) 563 { 564 struct ifnet *ifp = &sc->sc_if; 565 int s; 566 567 s = splnet(); 568 569 callout_stop(&sc->sc_tick_ch); 570 mii_down(&sc->sc_mii); 571 572 gmac_stop_txdma(sc); 573 gmac_stop_rxdma(sc); 574 575 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 576 577 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 578 ifp->if_timer = 0; 579 580 splx(s); 581 } 582 583 void 584 gmac_init_mac(struct gmac_softc *sc) 585 { 586 int i, tb; 587 char *laddr = sc->sc_laddr; 588 589 if ((mfpvr() >> 16) == MPC601) 590 tb = mfrtcl(); 591 else 592 tb = mftbl(); 593 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 594 595 /* init-mii */ 596 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 597 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 598 599 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 600 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 601 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 602 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 603 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 604 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 605 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 606 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 607 gmac_write_reg(sc, GMAC_PASIZE, 7); 608 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 609 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 610 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 611 612 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 613 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 614 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 615 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 616 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 617 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 618 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 619 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 620 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 621 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 622 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 623 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 624 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 625 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 626 627 for (i = 0; i < 0x6c; i += 4) 628 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 629 630 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 631 632 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 633 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 634 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 635 } else { 636 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 637 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 638 } 639 640 if (0) /* g-bit? */ 641 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 642 else 643 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 644 } 645 646 void 647 gmac_setladrf(struct gmac_softc *sc) 648 { 649 struct ifnet *ifp = &sc->sc_if; 650 struct ether_multi *enm; 651 struct ether_multistep step; 652 struct ethercom *ec = &sc->sc_ethercom; 653 u_int32_t crc; 654 u_int32_t hash[16]; 655 u_int v; 656 int i; 657 658 /* Clear hash table */ 659 for (i = 0; i < 16; i++) 660 hash[i] = 0; 661 662 /* Get current RX configuration */ 663 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 664 665 if ((ifp->if_flags & IFF_PROMISC) != 0) { 666 /* Turn on promiscuous mode; turn off the hash filter */ 667 v |= GMAC_RXMAC_PR; 668 v &= ~GMAC_RXMAC_HEN; 669 ifp->if_flags |= IFF_ALLMULTI; 670 goto chipit; 671 } 672 673 /* Turn off promiscuous mode; turn on the hash filter */ 674 v &= ~GMAC_RXMAC_PR; 675 v |= GMAC_RXMAC_HEN; 676 677 /* 678 * Set up multicast address filter by passing all multicast addresses 679 * through a crc generator, and then using the high order 8 bits as an 680 * index into the 256 bit logical address filter. The high order bit 681 * selects the word, while the rest of the bits select the bit within 682 * the word. 683 */ 684 685 ETHER_FIRST_MULTI(step, ec, enm); 686 while (enm != NULL) { 687 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 688 /* 689 * We must listen to a range of multicast addresses. 690 * For now, just accept all multicasts, rather than 691 * trying to set only those filter bits needed to match 692 * the range. (At this time, the only use of address 693 * ranges is for IP multicast routing, for which the 694 * range is big enough to require all bits set.) 695 */ 696 for (i = 0; i < 16; i++) 697 hash[i] = 0xffff; 698 ifp->if_flags |= IFF_ALLMULTI; 699 goto chipit; 700 } 701 702 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 703 704 /* Just want the 8 most significant bits. */ 705 crc >>= 24; 706 707 /* Set the corresponding bit in the filter. */ 708 hash[crc >> 4] |= 1 << (crc & 0xf); 709 710 ETHER_NEXT_MULTI(step, enm); 711 } 712 713 ifp->if_flags &= ~IFF_ALLMULTI; 714 715 chipit: 716 /* Now load the hash table into the chip */ 717 for (i = 0; i < 16; i++) 718 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 719 720 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 721 } 722 723 void 724 gmac_init(struct gmac_softc *sc) 725 { 726 struct ifnet *ifp = &sc->sc_if; 727 728 gmac_stop_txdma(sc); 729 gmac_stop_rxdma(sc); 730 731 gmac_init_mac(sc); 732 gmac_setladrf(sc); 733 734 gmac_start_txdma(sc); 735 gmac_start_rxdma(sc); 736 737 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 738 739 ifp->if_flags |= IFF_RUNNING; 740 ifp->if_flags &= ~IFF_OACTIVE; 741 ifp->if_timer = 0; 742 743 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 744 745 gmac_start(ifp); 746 } 747 748 int 749 gmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 750 { 751 struct gmac_softc *sc = ifp->if_softc; 752 struct ifaddr *ifa = (struct ifaddr *)data; 753 struct ifreq *ifr = (struct ifreq *)data; 754 int s, error = 0; 755 756 s = splnet(); 757 758 switch (cmd) { 759 760 case SIOCINITIFADDR: 761 ifp->if_flags |= IFF_UP; 762 763 gmac_init(sc); 764 switch (ifa->ifa_addr->sa_family) { 765 #ifdef INET 766 case AF_INET: 767 arp_ifinit(ifp, ifa); 768 break; 769 #endif 770 default: 771 break; 772 } 773 break; 774 775 case SIOCSIFFLAGS: 776 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 777 break; 778 /* XXX see the comment in ed_ioctl() about code re-use */ 779 if ((ifp->if_flags & IFF_UP) == 0 && 780 (ifp->if_flags & IFF_RUNNING) != 0) { 781 /* 782 * If interface is marked down and it is running, then 783 * stop it. 784 */ 785 gmac_stop(sc); 786 ifp->if_flags &= ~IFF_RUNNING; 787 } else if ((ifp->if_flags & IFF_UP) != 0 && 788 (ifp->if_flags & IFF_RUNNING) == 0) { 789 /* 790 * If interface is marked up and it is stopped, then 791 * start it. 792 */ 793 gmac_init(sc); 794 } else { 795 /* 796 * Reset the interface to pick up changes in any other 797 * flags that affect hardware registers. 798 */ 799 gmac_reset(sc); 800 gmac_init(sc); 801 } 802 #ifdef GMAC_DEBUG 803 if (ifp->if_flags & IFF_DEBUG) 804 sc->sc_flags |= GMAC_DEBUGFLAG; 805 #endif 806 break; 807 808 case SIOCADDMULTI: 809 case SIOCDELMULTI: 810 case SIOCGIFMEDIA: 811 case SIOCSIFMEDIA: 812 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 813 /* 814 * Multicast list has changed; set the hardware filter 815 * accordingly. 816 */ 817 if (ifp->if_flags & IFF_RUNNING) { 818 gmac_init(sc); 819 /* gmac_setladrf(sc); */ 820 } 821 error = 0; 822 } 823 break; 824 default: 825 error = ether_ioctl(ifp, cmd, data); 826 break; 827 } 828 829 splx(s); 830 return error; 831 } 832 833 void 834 gmac_watchdog(struct ifnet *ifp) 835 { 836 struct gmac_softc *sc = ifp->if_softc; 837 838 printf("%s: device timeout\n", ifp->if_xname); 839 ifp->if_oerrors++; 840 841 gmac_reset(sc); 842 gmac_init(sc); 843 } 844 845 int 846 gmac_mii_readreg(device_t self, int phy, int reg) 847 { 848 struct gmac_softc *sc = device_private(self); 849 int i; 850 851 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 852 0x60020000 | (phy << 23) | (reg << 18)); 853 854 for (i = 1000; i >= 0; i -= 10) { 855 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 856 break; 857 delay(10); 858 } 859 if (i < 0) { 860 aprint_error_dev(sc->sc_dev, "gmac_mii_readreg: timeout\n"); 861 return 0; 862 } 863 864 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 865 } 866 867 void 868 gmac_mii_writereg(device_t self, int phy, int reg, int val) 869 { 870 struct gmac_softc *sc = device_private(self); 871 int i; 872 873 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 874 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 875 876 for (i = 1000; i >= 0; i -= 10) { 877 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 878 break; 879 delay(10); 880 } 881 if (i < 0) 882 aprint_error_dev(sc->sc_dev, "gmac_mii_writereg: timeout\n"); 883 } 884 885 void 886 gmac_mii_statchg(struct ifnet *ifp) 887 { 888 struct gmac_softc *sc = ifp->if_softc; 889 890 gmac_stop_txdma(sc); 891 gmac_stop_rxdma(sc); 892 893 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 894 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 895 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 896 } else { 897 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 898 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 899 } 900 901 if (0) /* g-bit? */ 902 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 903 else 904 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 905 906 gmac_start_txdma(sc); 907 gmac_start_rxdma(sc); 908 } 909 910 void 911 gmac_mii_tick(void *v) 912 { 913 struct gmac_softc *sc = v; 914 int s; 915 916 s = splnet(); 917 mii_tick(&sc->sc_mii); 918 splx(s); 919 920 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 921 } 922