1 /* $NetBSD: if_gm.c,v 1.8 2000/06/29 08:10:45 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include "opt_inet.h" 30 #include "opt_ns.h" 31 #include "bpfilter.h" 32 33 #include <sys/param.h> 34 #include <sys/device.h> 35 #include <sys/ioctl.h> 36 #include <sys/kernel.h> 37 #include <sys/mbuf.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/callout.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <net/if.h> 45 #include <net/if_ether.h> 46 #include <net/if_media.h> 47 48 #if NBPFILTER > 0 49 #include <net/bpf.h> 50 #endif 51 52 #ifdef INET 53 #include <netinet/in.h> 54 #include <netinet/if_inarp.h> 55 #endif 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 64 #include <dev/ofw/openfirm.h> 65 #include <macppc/dev/if_gmreg.h> 66 #include <machine/pio.h> 67 68 #define NTXBUF 4 69 #define NRXBUF 32 70 71 struct gmac_softc { 72 struct device sc_dev; 73 struct ethercom sc_ethercom; 74 vaddr_t sc_reg; 75 struct gmac_dma *sc_txlist; 76 struct gmac_dma *sc_rxlist; 77 int sc_txnext; 78 int sc_rxlast; 79 caddr_t sc_txbuf[NTXBUF]; 80 caddr_t sc_rxbuf[NRXBUF]; 81 struct mii_data sc_mii; 82 struct callout sc_tick_ch; 83 char sc_laddr[6]; 84 }; 85 86 #define sc_if sc_ethercom.ec_if 87 88 int gmac_match __P((struct device *, struct cfdata *, void *)); 89 void gmac_attach __P((struct device *, struct device *, void *)); 90 91 static __inline u_int gmac_read_reg __P((struct gmac_softc *, int)); 92 static __inline void gmac_write_reg __P((struct gmac_softc *, int, u_int)); 93 94 static __inline void gmac_start_txdma __P((struct gmac_softc *)); 95 static __inline void gmac_start_rxdma __P((struct gmac_softc *)); 96 static __inline void gmac_stop_txdma __P((struct gmac_softc *)); 97 static __inline void gmac_stop_rxdma __P((struct gmac_softc *)); 98 99 int gmac_intr __P((void *)); 100 void gmac_tint __P((struct gmac_softc *)); 101 void gmac_rint __P((struct gmac_softc *)); 102 struct mbuf * gmac_get __P((struct gmac_softc *, caddr_t, int)); 103 void gmac_start __P((struct ifnet *)); 104 int gmac_put __P((struct gmac_softc *, caddr_t, struct mbuf *)); 105 106 void gmac_stop __P((struct gmac_softc *)); 107 void gmac_reset __P((struct gmac_softc *)); 108 void gmac_init __P((struct gmac_softc *)); 109 void gmac_init_mac __P((struct gmac_softc *)); 110 void gmac_setladrf __P((struct gmac_softc *)); 111 112 int gmac_ioctl __P((struct ifnet *, u_long, caddr_t)); 113 void gmac_watchdog __P((struct ifnet *)); 114 115 int gmac_mediachange __P((struct ifnet *)); 116 void gmac_mediastatus __P((struct ifnet *, struct ifmediareq *)); 117 int gmac_mii_readreg __P((struct device *, int, int)); 118 void gmac_mii_writereg __P((struct device *, int, int, int)); 119 void gmac_mii_statchg __P((struct device *)); 120 void gmac_mii_tick __P((void *)); 121 122 struct cfattach gm_ca = { 123 sizeof(struct gmac_softc), gmac_match, gmac_attach 124 }; 125 126 int 127 gmac_match(parent, match, aux) 128 struct device *parent; 129 struct cfdata *match; 130 void *aux; 131 { 132 struct pci_attach_args *pa = aux; 133 134 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_APPLE && 135 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_APPLE_GMAC) 136 return 1; 137 138 return 0; 139 } 140 141 void 142 gmac_attach(parent, self, aux) 143 struct device *parent, *self; 144 void *aux; 145 { 146 struct gmac_softc *sc = (void *)self; 147 struct pci_attach_args *pa = aux; 148 struct ifnet *ifp = &sc->sc_if; 149 struct mii_data *mii = &sc->sc_mii; 150 pci_intr_handle_t ih; 151 const char *intrstr = NULL; 152 int node, i; 153 char *p; 154 struct gmac_dma *dp; 155 u_int32_t reg[10]; 156 u_char laddr[6]; 157 158 node = pcidev_to_ofdev(pa->pa_pc, pa->pa_tag); 159 if (node == 0) { 160 printf(": cannot find gmac node\n"); 161 return; 162 } 163 164 OF_getprop(node, "local-mac-address", laddr, sizeof laddr); 165 OF_getprop(node, "assigned-addresses", reg, sizeof reg); 166 167 bcopy(laddr, sc->sc_laddr, sizeof laddr); 168 sc->sc_reg = reg[2]; 169 170 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 171 pa->pa_intrline, &ih)) { 172 printf(": unable to map interrupt\n"); 173 return; 174 } 175 intrstr = pci_intr_string(pa->pa_pc, ih); 176 177 if (pci_intr_establish(pa->pa_pc, ih, IPL_NET, gmac_intr, sc) == NULL) { 178 printf(": unable to establish interrupt"); 179 if (intrstr) 180 printf(" at %s", intrstr); 181 printf("\n"); 182 return; 183 } 184 185 /* Setup packet buffers and dma descriptors. */ 186 p = malloc((NRXBUF + NTXBUF) * 2048 + 3 * 0x800, M_DEVBUF, M_NOWAIT); 187 if (p == NULL) { 188 printf(": cannot malloc buffers\n"); 189 return; 190 } 191 p = (void *)roundup((vaddr_t)p, 0x800); 192 bzero(p, 2048 * (NRXBUF + NTXBUF) + 2 * 0x800); 193 194 sc->sc_rxlist = (void *)p; 195 p += 0x800; 196 sc->sc_txlist = (void *)p; 197 p += 0x800; 198 199 dp = sc->sc_rxlist; 200 for (i = 0; i < NRXBUF; i++) { 201 sc->sc_rxbuf[i] = p; 202 dp->address = htole32(vtophys((vaddr_t)p)); 203 dp->cmd = htole32(GMAC_OWN); 204 dp++; 205 p += 2048; 206 } 207 208 dp = sc->sc_txlist; 209 for (i = 0; i < NTXBUF; i++) { 210 sc->sc_txbuf[i] = p; 211 dp->address = htole32(vtophys((vaddr_t)p)); 212 dp++; 213 p += 2048; 214 } 215 216 printf(": Ethernet address %s\n", ether_sprintf(laddr)); 217 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr); 218 219 callout_init(&sc->sc_tick_ch); 220 221 gmac_reset(sc); 222 gmac_init_mac(sc); 223 224 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 225 ifp->if_softc = sc; 226 ifp->if_ioctl = gmac_ioctl; 227 ifp->if_start = gmac_start; 228 ifp->if_watchdog = gmac_watchdog; 229 ifp->if_flags = 230 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 231 232 mii->mii_ifp = ifp; 233 mii->mii_readreg = gmac_mii_readreg; 234 mii->mii_writereg = gmac_mii_writereg; 235 mii->mii_statchg = gmac_mii_statchg; 236 237 ifmedia_init(&mii->mii_media, 0, gmac_mediachange, gmac_mediastatus); 238 mii_attach(self, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 239 240 /* Choose a default media. */ 241 if (LIST_FIRST(&mii->mii_phys) == NULL) { 242 ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 243 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE); 244 } else 245 ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO); 246 247 if_attach(ifp); 248 ether_ifattach(ifp, laddr); 249 250 #if NBPFILTER > 0 251 bpfattach(&ifp->if_bpf, ifp, DLT_EN10MB, sizeof(struct ether_header)); 252 #endif 253 } 254 255 u_int 256 gmac_read_reg(sc, reg) 257 struct gmac_softc *sc; 258 int reg; 259 { 260 return in32rb(sc->sc_reg + reg); 261 } 262 263 void 264 gmac_write_reg(sc, reg, val) 265 struct gmac_softc *sc; 266 int reg; 267 u_int val; 268 { 269 out32rb(sc->sc_reg + reg, val); 270 } 271 272 void 273 gmac_start_txdma(sc) 274 struct gmac_softc *sc; 275 { 276 u_int x; 277 278 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 279 x |= 1; 280 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 281 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 282 x |= 1; 283 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 284 } 285 286 void 287 gmac_start_rxdma(sc) 288 struct gmac_softc *sc; 289 { 290 u_int x; 291 292 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 293 x |= 1; 294 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 295 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 296 x |= 1; 297 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 298 } 299 300 void 301 gmac_stop_txdma(sc) 302 struct gmac_softc *sc; 303 { 304 u_int x; 305 306 x = gmac_read_reg(sc, GMAC_TXDMACONFIG); 307 x &= ~1; 308 gmac_write_reg(sc, GMAC_TXDMACONFIG, x); 309 x = gmac_read_reg(sc, GMAC_TXMACCONFIG); 310 x &= ~1; 311 gmac_write_reg(sc, GMAC_TXMACCONFIG, x); 312 } 313 314 void 315 gmac_stop_rxdma(sc) 316 struct gmac_softc *sc; 317 { 318 u_int x; 319 320 x = gmac_read_reg(sc, GMAC_RXDMACONFIG); 321 x &= ~1; 322 gmac_write_reg(sc, GMAC_RXDMACONFIG, x); 323 x = gmac_read_reg(sc, GMAC_RXMACCONFIG); 324 x &= ~1; 325 gmac_write_reg(sc, GMAC_RXMACCONFIG, x); 326 } 327 328 int 329 gmac_intr(v) 330 void *v; 331 { 332 struct gmac_softc *sc = v; 333 u_int status; 334 335 status = gmac_read_reg(sc, GMAC_STATUS) & 0xff; 336 if (status == 0) 337 return 0; 338 339 if (status & GMAC_INT_RXDONE) 340 gmac_rint(sc); 341 342 if (status & GMAC_INT_TXEMPTY) 343 gmac_tint(sc); 344 345 return 1; 346 } 347 348 void 349 gmac_tint(sc) 350 struct gmac_softc *sc; 351 { 352 struct ifnet *ifp = &sc->sc_if; 353 354 ifp->if_flags &= ~IFF_OACTIVE; 355 ifp->if_timer = 0; 356 gmac_start(ifp); 357 } 358 359 void 360 gmac_rint(sc) 361 struct gmac_softc *sc; 362 { 363 struct ifnet *ifp = &sc->sc_if; 364 volatile struct gmac_dma *dp; 365 struct mbuf *m; 366 int i, len; 367 u_int cmd; 368 369 for (i = sc->sc_rxlast;; i++) { 370 if (i == NRXBUF) 371 i = 0; 372 373 dp = &sc->sc_rxlist[i]; 374 cmd = le32toh(dp->cmd); 375 if (cmd & GMAC_OWN) 376 break; 377 len = (cmd >> 16) & GMAC_LEN_MASK; 378 len -= 4; /* CRC */ 379 380 if (le32toh(dp->cmd_hi) & 0x40000000) { 381 ifp->if_ierrors++; 382 goto next; 383 } 384 385 m = gmac_get(sc, sc->sc_rxbuf[i], len); 386 if (m == NULL) { 387 ifp->if_ierrors++; 388 goto next; 389 } 390 391 #if NBPFILTER > 0 392 /* 393 * Check if there's a BPF listener on this interface. 394 * If so, hand off the raw packet to BPF. 395 */ 396 if (ifp->if_bpf) 397 bpf_tap(ifp->if_bpf, sc->sc_rxbuf[i], len); 398 #endif 399 (*ifp->if_input)(ifp, m); 400 ifp->if_ipackets++; 401 402 next: 403 dp->cmd_hi = 0; 404 __asm __volatile ("sync"); 405 dp->cmd = htole32(GMAC_OWN); 406 } 407 sc->sc_rxlast = i; 408 } 409 410 struct mbuf * 411 gmac_get(sc, pkt, totlen) 412 struct gmac_softc *sc; 413 caddr_t pkt; 414 int totlen; 415 { 416 struct mbuf *m; 417 struct mbuf *top, **mp; 418 int len; 419 420 MGETHDR(m, M_DONTWAIT, MT_DATA); 421 if (m == 0) 422 return 0; 423 m->m_pkthdr.rcvif = &sc->sc_if; 424 m->m_pkthdr.len = totlen; 425 len = MHLEN; 426 top = 0; 427 mp = ⊤ 428 429 while (totlen > 0) { 430 if (top) { 431 MGET(m, M_DONTWAIT, MT_DATA); 432 if (m == 0) { 433 m_freem(top); 434 return 0; 435 } 436 len = MLEN; 437 } 438 if (totlen >= MINCLSIZE) { 439 MCLGET(m, M_DONTWAIT); 440 if ((m->m_flags & M_EXT) == 0) { 441 m_free(m); 442 m_freem(top); 443 return 0; 444 } 445 len = MCLBYTES; 446 } 447 m->m_len = len = min(totlen, len); 448 bcopy(pkt, mtod(m, caddr_t), len); 449 pkt += len; 450 totlen -= len; 451 *mp = m; 452 mp = &m->m_next; 453 } 454 455 return top; 456 } 457 458 void 459 gmac_start(ifp) 460 struct ifnet *ifp; 461 { 462 struct gmac_softc *sc = ifp->if_softc; 463 struct mbuf *m; 464 caddr_t buff; 465 int i, tlen; 466 volatile struct gmac_dma *dp; 467 468 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 469 return; 470 471 for (;;) { 472 if (ifp->if_flags & IFF_OACTIVE) 473 break; 474 475 IF_DEQUEUE(&ifp->if_snd, m); 476 if (m == 0) 477 break; 478 479 /* 5 seconds to watch for failing to transmit */ 480 ifp->if_timer = 5; 481 ifp->if_opackets++; /* # of pkts */ 482 483 i = sc->sc_txnext; 484 buff = sc->sc_txbuf[i]; 485 tlen = gmac_put(sc, buff, m); 486 487 dp = &sc->sc_txlist[i]; 488 dp->cmd_hi = 0; 489 dp->address_hi = 0; 490 dp->cmd = htole32(tlen | GMAC_OWN | GMAC_SOP); 491 492 i++; 493 if (i == NTXBUF) 494 i = 0; 495 __asm __volatile ("sync"); 496 497 gmac_write_reg(sc, GMAC_TXDMAKICK, i); 498 sc->sc_txnext = i; 499 500 #if NBPFILTER > 0 501 /* 502 * If BPF is listening on this interface, let it see the 503 * packet before we commit it to the wire. 504 */ 505 if (ifp->if_bpf) 506 bpf_tap(ifp->if_bpf, buff, tlen); 507 #endif 508 509 i++; 510 if (i == NTXBUF) 511 i = 0; 512 if (i == gmac_read_reg(sc, GMAC_TXDMACOMPLETE)) { 513 ifp->if_flags |= IFF_OACTIVE; 514 break; 515 } 516 } 517 } 518 519 int 520 gmac_put(sc, buff, m) 521 struct gmac_softc *sc; 522 caddr_t buff; 523 struct mbuf *m; 524 { 525 struct mbuf *n; 526 int len, tlen = 0; 527 528 for (; m; m = n) { 529 len = m->m_len; 530 if (len == 0) { 531 MFREE(m, n); 532 continue; 533 } 534 bcopy(mtod(m, caddr_t), buff, len); 535 buff += len; 536 tlen += len; 537 MFREE(m, n); 538 } 539 if (tlen > 2048) 540 panic("%s: gmac_put packet overflow", sc->sc_dev.dv_xname); 541 542 return tlen; 543 } 544 545 void 546 gmac_reset(sc) 547 struct gmac_softc *sc; 548 { 549 int i, s; 550 551 s = splnet(); 552 553 gmac_stop_txdma(sc); 554 gmac_stop_rxdma(sc); 555 556 gmac_write_reg(sc, GMAC_SOFTWARERESET, 3); 557 for (i = 10; i > 0; i--) { 558 delay(300000); /* XXX long delay */ 559 if ((gmac_read_reg(sc, GMAC_SOFTWARERESET) & 3) == 0) 560 break; 561 } 562 if (i == 0) 563 printf("%s: reset timeout\n", sc->sc_dev.dv_xname); 564 565 sc->sc_txnext = 0; 566 sc->sc_rxlast = 0; 567 for (i = 0; i < NRXBUF; i++) 568 sc->sc_rxlist[i].cmd = htole32(GMAC_OWN); 569 __asm __volatile ("sync"); 570 571 gmac_write_reg(sc, GMAC_TXDMADESCBASEHI, 0); 572 gmac_write_reg(sc, GMAC_TXDMADESCBASELO, 573 vtophys((vaddr_t)sc->sc_txlist)); 574 gmac_write_reg(sc, GMAC_RXDMADESCBASEHI, 0); 575 gmac_write_reg(sc, GMAC_RXDMADESCBASELO, 576 vtophys((vaddr_t)sc->sc_rxlist)); 577 gmac_write_reg(sc, GMAC_RXDMAKICK, NRXBUF); 578 579 splx(s); 580 } 581 582 void 583 gmac_stop(sc) 584 struct gmac_softc *sc; 585 { 586 struct ifnet *ifp = &sc->sc_if; 587 int s; 588 589 s = splnet(); 590 591 callout_stop(&sc->sc_tick_ch); 592 mii_down(&sc->sc_mii); 593 594 gmac_stop_txdma(sc); 595 gmac_stop_rxdma(sc); 596 597 gmac_write_reg(sc, GMAC_INTMASK, 0xffffffff); 598 599 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 600 ifp->if_timer = 0; 601 602 splx(s); 603 } 604 605 void 606 gmac_init_mac(sc) 607 struct gmac_softc *sc; 608 { 609 int i, tb; 610 char *laddr = sc->sc_laddr; 611 612 __asm ("mftb %0" : "=r"(tb)); 613 gmac_write_reg(sc, GMAC_RANDOMSEED, tb); 614 615 /* init-mii */ 616 gmac_write_reg(sc, GMAC_DATAPATHMODE, 4); 617 gmac_mii_writereg(&sc->sc_dev, 0, 0, 0x1000); 618 619 gmac_write_reg(sc, GMAC_TXDMACONFIG, 0xffc00); 620 gmac_write_reg(sc, GMAC_RXDMACONFIG, 0); 621 gmac_write_reg(sc, GMAC_MACPAUSE, 0x1bf0); 622 gmac_write_reg(sc, GMAC_INTERPACKETGAP0, 0); 623 gmac_write_reg(sc, GMAC_INTERPACKETGAP1, 8); 624 gmac_write_reg(sc, GMAC_INTERPACKETGAP2, 4); 625 gmac_write_reg(sc, GMAC_MINFRAMESIZE, ETHER_MIN_LEN); 626 gmac_write_reg(sc, GMAC_MAXFRAMESIZE, ETHER_MAX_LEN); 627 gmac_write_reg(sc, GMAC_PASIZE, 7); 628 gmac_write_reg(sc, GMAC_JAMSIZE, 4); 629 gmac_write_reg(sc, GMAC_ATTEMPTLIMIT,0x10); 630 gmac_write_reg(sc, GMAC_MACCNTLTYPE, 0x8808); 631 632 gmac_write_reg(sc, GMAC_MACADDRESS0, (laddr[4] << 8) | laddr[5]); 633 gmac_write_reg(sc, GMAC_MACADDRESS1, (laddr[2] << 8) | laddr[3]); 634 gmac_write_reg(sc, GMAC_MACADDRESS2, (laddr[0] << 8) | laddr[1]); 635 gmac_write_reg(sc, GMAC_MACADDRESS3, 0); 636 gmac_write_reg(sc, GMAC_MACADDRESS4, 0); 637 gmac_write_reg(sc, GMAC_MACADDRESS5, 0); 638 gmac_write_reg(sc, GMAC_MACADDRESS6, 1); 639 gmac_write_reg(sc, GMAC_MACADDRESS7, 0xc200); 640 gmac_write_reg(sc, GMAC_MACADDRESS8, 0x0180); 641 gmac_write_reg(sc, GMAC_MACADDRFILT0, 0); 642 gmac_write_reg(sc, GMAC_MACADDRFILT1, 0); 643 gmac_write_reg(sc, GMAC_MACADDRFILT2, 0); 644 gmac_write_reg(sc, GMAC_MACADDRFILT2_1MASK, 0); 645 gmac_write_reg(sc, GMAC_MACADDRFILT0MASK, 0); 646 647 for (i = 0; i < 0x6c; i += 4) 648 gmac_write_reg(sc, GMAC_HASHTABLE0 + i, 0); 649 650 gmac_write_reg(sc, GMAC_SLOTTIME, 0x40); 651 652 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 653 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 654 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 655 } else { 656 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 657 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 658 } 659 660 if (0) /* g-bit? */ 661 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 662 else 663 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 664 } 665 666 void 667 gmac_setladrf(sc) 668 struct gmac_softc *sc; 669 { 670 struct ifnet *ifp = &sc->sc_if; 671 struct ether_multi *enm; 672 struct ether_multistep step; 673 struct ethercom *ec = &sc->sc_ethercom; 674 u_int32_t crc; 675 u_int32_t hash[16]; 676 u_int v; 677 int i; 678 679 /* Clear hash table */ 680 for (i = 0; i < 16; i++) 681 hash[i] = 0; 682 683 /* Get current RX configuration */ 684 v = gmac_read_reg(sc, GMAC_RXMACCONFIG); 685 686 if ((ifp->if_flags & IFF_PROMISC) != 0) { 687 /* Turn on promiscuous mode; turn off the hash filter */ 688 v |= GMAC_RXMAC_PR; 689 v &= ~GMAC_RXMAC_HEN; 690 ifp->if_flags |= IFF_ALLMULTI; 691 goto chipit; 692 } 693 694 /* Turn off promiscuous mode; turn on the hash filter */ 695 v &= ~GMAC_RXMAC_PR; 696 v |= GMAC_RXMAC_HEN; 697 698 /* 699 * Set up multicast address filter by passing all multicast addresses 700 * through a crc generator, and then using the high order 8 bits as an 701 * index into the 256 bit logical address filter. The high order bit 702 * selects the word, while the rest of the bits select the bit within 703 * the word. 704 */ 705 706 ETHER_FIRST_MULTI(step, ec, enm); 707 while (enm != NULL) { 708 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6)) { 709 /* 710 * We must listen to a range of multicast addresses. 711 * For now, just accept all multicasts, rather than 712 * trying to set only those filter bits needed to match 713 * the range. (At this time, the only use of address 714 * ranges is for IP multicast routing, for which the 715 * range is big enough to require all bits set.) 716 */ 717 for (i = 0; i < 16; i++) 718 hash[i] = 0xffff; 719 ifp->if_flags |= IFF_ALLMULTI; 720 goto chipit; 721 } 722 723 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 724 725 /* Just want the 8 most significant bits. */ 726 crc >>= 24; 727 728 /* Set the corresponding bit in the filter. */ 729 hash[crc >> 4] |= 1 << (crc & 0xf); 730 731 ETHER_NEXT_MULTI(step, enm); 732 } 733 734 ifp->if_flags &= ~IFF_ALLMULTI; 735 736 chipit: 737 /* Now load the hash table into the chip */ 738 for (i = 0; i < 16; i++) 739 gmac_write_reg(sc, GMAC_HASHTABLE0 + i * 4, hash[i]); 740 741 gmac_write_reg(sc, GMAC_RXMACCONFIG, v); 742 } 743 744 void 745 gmac_init(sc) 746 struct gmac_softc *sc; 747 { 748 struct ifnet *ifp = &sc->sc_if; 749 750 gmac_stop_txdma(sc); 751 gmac_stop_rxdma(sc); 752 753 gmac_init_mac(sc); 754 gmac_setladrf(sc); 755 756 gmac_start_txdma(sc); 757 gmac_start_rxdma(sc); 758 759 gmac_write_reg(sc, GMAC_INTMASK, ~(GMAC_INT_TXEMPTY | GMAC_INT_RXDONE)); 760 761 ifp->if_flags |= IFF_RUNNING; 762 ifp->if_flags &= ~IFF_OACTIVE; 763 ifp->if_timer = 0; 764 765 callout_reset(&sc->sc_tick_ch, 1, gmac_mii_tick, sc); 766 767 gmac_start(ifp); 768 } 769 770 int 771 gmac_ioctl(ifp, cmd, data) 772 struct ifnet *ifp; 773 u_long cmd; 774 caddr_t data; 775 { 776 struct gmac_softc *sc = ifp->if_softc; 777 struct ifaddr *ifa = (struct ifaddr *)data; 778 struct ifreq *ifr = (struct ifreq *)data; 779 int s, error = 0; 780 781 s = splnet(); 782 783 switch (cmd) { 784 785 case SIOCSIFADDR: 786 ifp->if_flags |= IFF_UP; 787 788 switch (ifa->ifa_addr->sa_family) { 789 #ifdef INET 790 case AF_INET: 791 gmac_init(sc); 792 arp_ifinit(ifp, ifa); 793 break; 794 #endif 795 #ifdef NS 796 case AF_NS: 797 { 798 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 799 800 if (ns_nullhost(*ina)) 801 ina->x_host = 802 *(union ns_host *)LLADDR(ifp->if_sadl); 803 else { 804 bcopy(ina->x_host.c_host, 805 LLADDR(ifp->if_sadl), 806 sizeof(sc->sc_enaddr)); 807 } 808 /* Set new address. */ 809 gmac_init(sc); 810 break; 811 } 812 #endif 813 default: 814 gmac_init(sc); 815 break; 816 } 817 break; 818 819 case SIOCSIFFLAGS: 820 if ((ifp->if_flags & IFF_UP) == 0 && 821 (ifp->if_flags & IFF_RUNNING) != 0) { 822 /* 823 * If interface is marked down and it is running, then 824 * stop it. 825 */ 826 gmac_stop(sc); 827 ifp->if_flags &= ~IFF_RUNNING; 828 } else if ((ifp->if_flags & IFF_UP) != 0 && 829 (ifp->if_flags & IFF_RUNNING) == 0) { 830 /* 831 * If interface is marked up and it is stopped, then 832 * start it. 833 */ 834 gmac_init(sc); 835 } else { 836 /* 837 * Reset the interface to pick up changes in any other 838 * flags that affect hardware registers. 839 */ 840 gmac_reset(sc); 841 gmac_init(sc); 842 } 843 #ifdef GMAC_DEBUG 844 if (ifp->if_flags & IFF_DEBUG) 845 sc->sc_flags |= GMAC_DEBUGFLAG; 846 #endif 847 break; 848 849 case SIOCADDMULTI: 850 case SIOCDELMULTI: 851 error = (cmd == SIOCADDMULTI) ? 852 ether_addmulti(ifr, &sc->sc_ethercom) : 853 ether_delmulti(ifr, &sc->sc_ethercom); 854 855 if (error == ENETRESET) { 856 /* 857 * Multicast list has changed; set the hardware filter 858 * accordingly. 859 */ 860 gmac_init(sc); 861 /* gmac_setladrf(sc); */ 862 error = 0; 863 } 864 break; 865 866 case SIOCGIFMEDIA: 867 case SIOCSIFMEDIA: 868 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 869 break; 870 871 default: 872 error = EINVAL; 873 } 874 875 splx(s); 876 return error; 877 } 878 879 void 880 gmac_watchdog(ifp) 881 struct ifnet *ifp; 882 { 883 struct gmac_softc *sc = ifp->if_softc; 884 885 printf("%s: device timeout\n", ifp->if_xname); 886 ifp->if_oerrors++; 887 888 gmac_reset(sc); 889 gmac_init(sc); 890 } 891 892 int 893 gmac_mediachange(ifp) 894 struct ifnet *ifp; 895 { 896 struct gmac_softc *sc = ifp->if_softc; 897 898 return mii_mediachg(&sc->sc_mii); 899 } 900 901 void 902 gmac_mediastatus(ifp, ifmr) 903 struct ifnet *ifp; 904 struct ifmediareq *ifmr; 905 { 906 struct gmac_softc *sc = ifp->if_softc; 907 908 mii_pollstat(&sc->sc_mii); 909 910 ifmr->ifm_status = sc->sc_mii.mii_media_status; 911 ifmr->ifm_active = sc->sc_mii.mii_media_active; 912 } 913 914 int 915 gmac_mii_readreg(dev, phy, reg) 916 struct device *dev; 917 int phy, reg; 918 { 919 struct gmac_softc *sc = (void *)dev; 920 int i; 921 922 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 923 0x60020000 | (phy << 23) | (reg << 18)); 924 925 for (i = 1000; i >= 0; i -= 10) { 926 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 927 break; 928 delay(10); 929 } 930 if (i < 0) { 931 printf("%s: gmac_mii_readreg: timeout\n", sc->sc_dev.dv_xname); 932 return 0; 933 } 934 935 return gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0xffff; 936 } 937 938 void 939 gmac_mii_writereg(dev, phy, reg, val) 940 struct device *dev; 941 int phy, reg, val; 942 { 943 struct gmac_softc *sc = (void *)dev; 944 int i; 945 946 gmac_write_reg(sc, GMAC_MIFFRAMEOUTPUT, 947 0x50020000 | (phy << 23) | (reg << 18) | (val & 0xffff)); 948 949 for (i = 1000; i >= 0; i -= 10) { 950 if (gmac_read_reg(sc, GMAC_MIFFRAMEOUTPUT) & 0x10000) 951 break; 952 delay(10); 953 } 954 if (i < 0) 955 printf("%s: gmac_mii_writereg: timeout\n", sc->sc_dev.dv_xname); 956 } 957 958 void 959 gmac_mii_statchg(dev) 960 struct device *dev; 961 { 962 struct gmac_softc *sc = (void *)dev; 963 964 gmac_stop_txdma(sc); 965 gmac_stop_rxdma(sc); 966 967 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) { 968 gmac_write_reg(sc, GMAC_TXMACCONFIG, 6); 969 gmac_write_reg(sc, GMAC_XIFCONFIG, 1); 970 } else { 971 gmac_write_reg(sc, GMAC_TXMACCONFIG, 0); 972 gmac_write_reg(sc, GMAC_XIFCONFIG, 5); 973 } 974 975 if (0) /* g-bit? */ 976 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 3); 977 else 978 gmac_write_reg(sc, GMAC_MACCTRLCONFIG, 0); 979 980 gmac_start_txdma(sc); 981 gmac_start_rxdma(sc); 982 } 983 984 void 985 gmac_mii_tick(v) 986 void *v; 987 { 988 struct gmac_softc *sc = v; 989 int s; 990 991 s = splnet(); 992 mii_tick(&sc->sc_mii); 993 splx(s); 994 995 callout_reset(&sc->sc_tick_ch, hz, gmac_mii_tick, sc); 996 } 997