1 /* $NetBSD: if_bm.c,v 1.63 2020/02/04 13:47:34 martin Exp $ */ 2 3 /*- 4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_bm.c,v 1.63 2020/02/04 13:47:34 martin Exp $"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/device.h> 36 #include <sys/ioctl.h> 37 #include <sys/kernel.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 52 #ifdef INET 53 #include <netinet/in.h> 54 #include <netinet/if_inarp.h> 55 #endif 56 57 58 #include <dev/ofw/openfirm.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/mii/miivar.h> 62 #include <dev/mii/mii_bitbang.h> 63 64 #include <powerpc/spr.h> 65 #include <powerpc/oea/spr.h> 66 67 #include <machine/autoconf.h> 68 #include <machine/pio.h> 69 70 #include <macppc/dev/dbdma.h> 71 #include <macppc/dev/if_bmreg.h> 72 #include <macppc/dev/obiovar.h> 73 74 #define BMAC_TXBUFS 2 75 #define BMAC_RXBUFS 16 76 #define BMAC_BUFLEN 2048 77 78 struct bmac_softc { 79 device_t sc_dev; 80 struct ethercom sc_ethercom; 81 #define sc_if sc_ethercom.ec_if 82 struct callout sc_tick_ch; 83 bus_space_tag_t sc_iot; 84 bus_space_handle_t sc_ioh; 85 dbdma_regmap_t *sc_txdma; 86 dbdma_regmap_t *sc_rxdma; 87 dbdma_command_t *sc_txcmd; 88 dbdma_command_t *sc_rxcmd; 89 void *sc_txbuf; 90 void *sc_rxbuf; 91 int sc_rxlast; 92 int sc_flags; 93 struct mii_data sc_mii; 94 u_char sc_enaddr[6]; 95 }; 96 97 #define BMAC_BMACPLUS 0x01 98 #define BMAC_DEBUGFLAG 0x02 99 100 int bmac_match(device_t, cfdata_t, void *); 101 void bmac_attach(device_t, device_t, void *); 102 void bmac_reset_chip(struct bmac_softc *); 103 void bmac_init(struct bmac_softc *); 104 void bmac_init_dma(struct bmac_softc *); 105 int bmac_intr(void *); 106 int bmac_rint(void *); 107 void bmac_reset(struct bmac_softc *); 108 void bmac_stop(struct bmac_softc *); 109 void bmac_start(struct ifnet *); 110 void bmac_transmit_packet(struct bmac_softc *, void *, int); 111 int bmac_put(struct bmac_softc *, void *, struct mbuf *); 112 struct mbuf *bmac_get(struct bmac_softc *, void *, int); 113 void bmac_watchdog(struct ifnet *); 114 int bmac_ioctl(struct ifnet *, u_long, void *); 115 void bmac_setladrf(struct bmac_softc *); 116 117 int bmac_mii_readreg(device_t, int, int, uint16_t *); 118 int bmac_mii_writereg(device_t, int, int, uint16_t); 119 void bmac_mii_statchg(struct ifnet *); 120 void bmac_mii_tick(void *); 121 uint32_t bmac_mbo_read(device_t); 122 void bmac_mbo_write(device_t, uint32_t); 123 124 CFATTACH_DECL_NEW(bm, sizeof(struct bmac_softc), 125 bmac_match, bmac_attach, NULL, NULL); 126 127 const struct mii_bitbang_ops bmac_mbo = { 128 bmac_mbo_read, bmac_mbo_write, 129 { MIFDO, MIFDI, MIFDC, MIFDIR, 0 } 130 }; 131 132 static inline uint16_t 133 bmac_read_reg(struct bmac_softc *sc, bus_size_t off) 134 { 135 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 136 } 137 138 static inline void 139 bmac_write_reg(struct bmac_softc *sc, bus_size_t off, uint16_t val) 140 { 141 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val); 142 } 143 144 static inline void 145 bmac_set_bits(struct bmac_softc *sc, bus_size_t off, uint16_t val) 146 { 147 val |= bmac_read_reg(sc, off); 148 bmac_write_reg(sc, off, val); 149 } 150 151 static inline void 152 bmac_reset_bits(struct bmac_softc *sc, bus_size_t off, uint16_t val) 153 { 154 bmac_write_reg(sc, off, bmac_read_reg(sc, off) & ~val); 155 } 156 157 int 158 bmac_match(device_t parent, cfdata_t cf, void *aux) 159 { 160 struct confargs *ca = aux; 161 162 if (ca->ca_nreg < 24 || ca->ca_nintr < 12) 163 return 0; 164 165 if (strcmp(ca->ca_name, "bmac") == 0) /* bmac */ 166 return 1; 167 if (strcmp(ca->ca_name, "ethernet") == 0) /* bmac+ */ 168 return 1; 169 170 return 0; 171 } 172 173 void 174 bmac_attach(device_t parent, device_t self, void *aux) 175 { 176 struct confargs *ca = aux; 177 struct bmac_softc *sc = device_private(self); 178 struct ifnet *ifp = &sc->sc_if; 179 struct mii_data *mii = &sc->sc_mii; 180 u_char laddr[6]; 181 182 callout_init(&sc->sc_tick_ch, 0); 183 184 sc->sc_dev = self; 185 sc->sc_flags = 0; 186 if (strcmp(ca->ca_name, "ethernet") == 0) { 187 char name[64]; 188 189 memset(name, 0, 64); 190 OF_package_to_path(ca->ca_node, name, sizeof(name)); 191 OF_open(name); 192 sc->sc_flags |= BMAC_BMACPLUS; 193 } 194 195 ca->ca_reg[0] += ca->ca_baseaddr; 196 ca->ca_reg[2] += ca->ca_baseaddr; 197 ca->ca_reg[4] += ca->ca_baseaddr; 198 199 sc->sc_iot = ca->ca_tag; 200 if (bus_space_map(sc->sc_iot, ca->ca_reg[0], ca->ca_reg[1], 0, 201 &sc->sc_ioh) != 0) { 202 aprint_error(": couldn't map %#x", ca->ca_reg[0]); 203 return; 204 } 205 206 bmac_write_reg(sc, INTDISABLE, NoEventsMask); 207 208 if (OF_getprop(ca->ca_node, "local-mac-address", laddr, 6) == -1 && 209 OF_getprop(ca->ca_node, "mac-address", laddr, 6) == -1) { 210 aprint_error(": cannot get mac-address\n"); 211 return; 212 } 213 memcpy(sc->sc_enaddr, laddr, 6); 214 215 sc->sc_txdma = mapiodev(ca->ca_reg[2], PAGE_SIZE, false); 216 sc->sc_rxdma = mapiodev(ca->ca_reg[4], PAGE_SIZE, false); 217 sc->sc_txcmd = dbdma_alloc(BMAC_TXBUFS * sizeof(dbdma_command_t), NULL); 218 sc->sc_rxcmd = dbdma_alloc((BMAC_RXBUFS + 1) * sizeof(dbdma_command_t), 219 NULL); 220 sc->sc_txbuf = malloc(BMAC_BUFLEN * BMAC_TXBUFS, M_DEVBUF, M_WAITOK); 221 sc->sc_rxbuf = malloc(BMAC_BUFLEN * BMAC_RXBUFS, M_DEVBUF, M_WAITOK); 222 223 aprint_normal(" irq %d,%d: address %s\n", 224 ca->ca_intr[0], ca->ca_intr[2], 225 ether_sprintf(laddr)); 226 227 intr_establish(ca->ca_intr[0], IST_EDGE, IPL_NET, bmac_intr, sc); 228 intr_establish(ca->ca_intr[2], IST_EDGE, IPL_NET, bmac_rint, sc); 229 230 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 231 ifp->if_softc = sc; 232 ifp->if_ioctl = bmac_ioctl; 233 ifp->if_start = bmac_start; 234 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 235 ifp->if_watchdog = bmac_watchdog; 236 IFQ_SET_READY(&ifp->if_snd); 237 238 mii->mii_ifp = ifp; 239 mii->mii_readreg = bmac_mii_readreg; 240 mii->mii_writereg = bmac_mii_writereg; 241 mii->mii_statchg = bmac_mii_statchg; 242 243 sc->sc_ethercom.ec_mii = mii; 244 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 245 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 246 247 /* Choose a default media. */ 248 if (LIST_FIRST(&mii->mii_phys) == NULL) { 249 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_10_T, 0, NULL); 250 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_10_T); 251 } else 252 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 253 254 bmac_reset_chip(sc); 255 256 if_attach(ifp); 257 if_deferred_start_init(ifp, NULL); 258 ether_ifattach(ifp, sc->sc_enaddr); 259 } 260 261 /* 262 * Reset and enable bmac by heathrow FCR. 263 */ 264 void 265 bmac_reset_chip(struct bmac_softc *sc) 266 { 267 u_int v; 268 269 dbdma_reset(sc->sc_txdma); 270 dbdma_reset(sc->sc_rxdma); 271 272 v = obio_read_4(HEATHROW_FCR); 273 274 v |= EnetEnable; 275 obio_write_4(HEATHROW_FCR, v); 276 delay(50000); 277 278 v |= ResetEnetCell; 279 obio_write_4(HEATHROW_FCR, v); 280 delay(50000); 281 282 v &= ~ResetEnetCell; 283 obio_write_4(HEATHROW_FCR, v); 284 delay(50000); 285 286 obio_write_4(HEATHROW_FCR, v); 287 } 288 289 void 290 bmac_init(struct bmac_softc *sc) 291 { 292 struct ifnet *ifp = &sc->sc_if; 293 struct ether_header *eh; 294 void *data; 295 int i, tb; 296 uint16_t bmcr; 297 u_short *p; 298 299 bmac_reset_chip(sc); 300 301 /* XXX */ 302 bmac_mii_readreg(sc->sc_dev, 0, MII_BMCR, &bmcr); 303 bmcr &= ~BMCR_ISO; 304 bmac_mii_writereg(sc->sc_dev, 0, MII_BMCR, bmcr); 305 306 bmac_write_reg(sc, RXRST, RxResetValue); 307 bmac_write_reg(sc, TXRST, TxResetBit); 308 309 /* Wait for reset completion. */ 310 for (i = 1000; i > 0; i -= 10) { 311 if ((bmac_read_reg(sc, TXRST) & TxResetBit) == 0) 312 break; 313 delay(10); 314 } 315 if (i <= 0) 316 printf("%s: reset timeout\n", ifp->if_xname); 317 318 if (! (sc->sc_flags & BMAC_BMACPLUS)) 319 bmac_set_bits(sc, XCVRIF, ClkBit | SerialMode | COLActiveLow); 320 321 if ((mfpvr() >> 16) == MPC601) 322 tb = mfrtcl(); 323 else 324 tb = mftbl(); 325 bmac_write_reg(sc, RSEED, tb); 326 bmac_set_bits(sc, XIFC, TxOutputEnable); 327 bmac_read_reg(sc, PAREG); 328 329 /* Reset various counters. */ 330 bmac_write_reg(sc, NCCNT, 0); 331 bmac_write_reg(sc, NTCNT, 0); 332 bmac_write_reg(sc, EXCNT, 0); 333 bmac_write_reg(sc, LTCNT, 0); 334 bmac_write_reg(sc, FRCNT, 0); 335 bmac_write_reg(sc, LECNT, 0); 336 bmac_write_reg(sc, AECNT, 0); 337 bmac_write_reg(sc, FECNT, 0); 338 bmac_write_reg(sc, RXCV, 0); 339 340 /* Set tx fifo information. */ 341 bmac_write_reg(sc, TXTH, 4); /* 4 octets before tx starts */ 342 343 bmac_write_reg(sc, TXFIFOCSR, 0); 344 bmac_write_reg(sc, TXFIFOCSR, TxFIFOEnable); 345 346 /* Set rx fifo information. */ 347 bmac_write_reg(sc, RXFIFOCSR, 0); 348 bmac_write_reg(sc, RXFIFOCSR, RxFIFOEnable); 349 350 /* Clear status register. */ 351 bmac_read_reg(sc, STATUS); 352 353 bmac_write_reg(sc, HASH3, 0); 354 bmac_write_reg(sc, HASH2, 0); 355 bmac_write_reg(sc, HASH1, 0); 356 bmac_write_reg(sc, HASH0, 0); 357 358 /* Set MAC address. */ 359 p = (u_short *)sc->sc_enaddr; 360 bmac_write_reg(sc, MADD0, *p++); 361 bmac_write_reg(sc, MADD1, *p++); 362 bmac_write_reg(sc, MADD2, *p); 363 364 bmac_write_reg(sc, RXCFG, 365 RxCRCEnable | RxHashFilterEnable | RxRejectOwnPackets); 366 367 if (ifp->if_flags & IFF_PROMISC) 368 bmac_set_bits(sc, RXCFG, RxPromiscEnable); 369 370 bmac_init_dma(sc); 371 372 /* Enable TX/RX */ 373 bmac_set_bits(sc, RXCFG, RxMACEnable); 374 bmac_set_bits(sc, TXCFG, TxMACEnable); 375 376 bmac_write_reg(sc, INTDISABLE, NormalIntEvents); 377 378 ifp->if_flags |= IFF_RUNNING; 379 ifp->if_flags &= ~IFF_OACTIVE; 380 ifp->if_timer = 0; 381 382 data = sc->sc_txbuf; 383 eh = (struct ether_header *)data; 384 385 memset(data, 0, sizeof(eh) + ETHERMIN); 386 memcpy(eh->ether_dhost, sc->sc_enaddr, ETHER_ADDR_LEN); 387 memcpy(eh->ether_shost, sc->sc_enaddr, ETHER_ADDR_LEN); 388 bmac_transmit_packet(sc, data, sizeof(eh) + ETHERMIN); 389 390 bmac_start(ifp); 391 392 callout_reset(&sc->sc_tick_ch, hz, bmac_mii_tick, sc); 393 } 394 395 void 396 bmac_init_dma(struct bmac_softc *sc) 397 { 398 dbdma_command_t *cmd = sc->sc_rxcmd; 399 int i; 400 401 dbdma_reset(sc->sc_txdma); 402 dbdma_reset(sc->sc_rxdma); 403 404 memset(sc->sc_txcmd, 0, BMAC_TXBUFS * sizeof(dbdma_command_t)); 405 memset(sc->sc_rxcmd, 0, (BMAC_RXBUFS + 1) * sizeof(dbdma_command_t)); 406 407 for (i = 0; i < BMAC_RXBUFS; i++) { 408 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, BMAC_BUFLEN, 409 vtophys((vaddr_t)sc->sc_rxbuf + BMAC_BUFLEN * i), 410 DBDMA_INT_ALWAYS, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 411 cmd++; 412 } 413 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 414 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 415 out32rb(&cmd->d_cmddep, vtophys((vaddr_t)sc->sc_rxcmd)); 416 417 sc->sc_rxlast = 0; 418 419 dbdma_start(sc->sc_rxdma, sc->sc_rxcmd); 420 } 421 422 int 423 bmac_intr(void *v) 424 { 425 struct bmac_softc *sc = v; 426 int stat; 427 428 stat = bmac_read_reg(sc, STATUS); 429 if (stat == 0) 430 return 0; 431 432 #ifdef BMAC_DEBUG 433 printf("bmac_intr status = 0x%x\n", stat); 434 #endif 435 436 if (stat & IntFrameSent) { 437 sc->sc_if.if_flags &= ~IFF_OACTIVE; 438 sc->sc_if.if_timer = 0; 439 if_statinc(&sc->sc_if, if_opackets); 440 if_schedule_deferred_start(&sc->sc_if); 441 } 442 443 /* XXX should do more! */ 444 445 return 1; 446 } 447 448 int 449 bmac_rint(void *v) 450 { 451 struct bmac_softc *sc = v; 452 struct ifnet *ifp = &sc->sc_if; 453 struct mbuf *m; 454 dbdma_command_t *cmd; 455 int status, resid, count, datalen; 456 int i, n; 457 void *data; 458 459 i = sc->sc_rxlast; 460 for (n = 0; n < BMAC_RXBUFS; n++, i++) { 461 if (i == BMAC_RXBUFS) 462 i = 0; 463 cmd = &sc->sc_rxcmd[i]; 464 status = in16rb(&cmd->d_status); 465 resid = in16rb(&cmd->d_resid); 466 467 #ifdef BMAC_DEBUG 468 if (status != 0 && status != 0x8440 && status != 0x9440) 469 printf("bmac_rint status = 0x%x\n", status); 470 #endif 471 472 if ((status & DBDMA_CNTRL_ACTIVE) == 0) /* 0x9440 | 0x8440 */ 473 continue; 474 count = in16rb(&cmd->d_count); 475 datalen = count - resid - 2; /* 2 == framelen */ 476 if (datalen < sizeof(struct ether_header)) { 477 printf("%s: short packet len = %d\n", 478 ifp->if_xname, datalen); 479 goto next; 480 } 481 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 482 data = (char *)sc->sc_rxbuf + BMAC_BUFLEN * i; 483 484 /* XXX Sometimes bmac reads one extra byte. */ 485 if (datalen == ETHER_MAX_LEN + 1) 486 datalen--; 487 488 /* Trim the CRC. */ 489 datalen -= ETHER_CRC_LEN; 490 491 m = bmac_get(sc, data, datalen); 492 if (m == NULL) { 493 if_statinc(ifp, if_ierrors); 494 goto next; 495 } 496 497 if_percpuq_enqueue(ifp->if_percpuq, m); 498 499 next: 500 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 501 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 502 503 cmd->d_status = 0; 504 cmd->d_resid = 0; 505 sc->sc_rxlast = i + 1; 506 } 507 ether_mediachange(ifp); 508 509 dbdma_continue(sc->sc_rxdma); 510 511 return 1; 512 } 513 514 void 515 bmac_reset(struct bmac_softc *sc) 516 { 517 int s; 518 519 s = splnet(); 520 bmac_init(sc); 521 splx(s); 522 } 523 524 void 525 bmac_stop(struct bmac_softc *sc) 526 { 527 struct ifnet *ifp = &sc->sc_if; 528 int s; 529 530 s = splnet(); 531 532 callout_stop(&sc->sc_tick_ch); 533 mii_down(&sc->sc_mii); 534 535 /* Disable TX/RX. */ 536 bmac_reset_bits(sc, TXCFG, TxMACEnable); 537 bmac_reset_bits(sc, RXCFG, RxMACEnable); 538 539 /* Disable all interrupts. */ 540 bmac_write_reg(sc, INTDISABLE, NoEventsMask); 541 542 dbdma_stop(sc->sc_txdma); 543 dbdma_stop(sc->sc_rxdma); 544 545 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 546 ifp->if_timer = 0; 547 548 splx(s); 549 } 550 551 void 552 bmac_start(struct ifnet *ifp) 553 { 554 struct bmac_softc *sc = ifp->if_softc; 555 struct mbuf *m; 556 int tlen; 557 558 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 559 return; 560 561 while (1) { 562 if (ifp->if_flags & IFF_OACTIVE) 563 return; 564 565 IFQ_DEQUEUE(&ifp->if_snd, m); 566 if (m == 0) 567 break; 568 /* 569 * If BPF is listening on this interface, let it see the 570 * packet before we commit it to the wire. 571 */ 572 bpf_mtap(ifp, m, BPF_D_OUT); 573 574 ifp->if_flags |= IFF_OACTIVE; 575 tlen = bmac_put(sc, sc->sc_txbuf, m); 576 577 /* 5 seconds to watch for failing to transmit */ 578 ifp->if_timer = 5; 579 if_statinc(ifp, if_opackets); /* # of pkts */ 580 581 bmac_transmit_packet(sc, sc->sc_txbuf, tlen); 582 } 583 } 584 585 void 586 bmac_transmit_packet(struct bmac_softc *sc, void *buff, int len) 587 { 588 dbdma_command_t *cmd = sc->sc_txcmd; 589 vaddr_t va = (vaddr_t)buff; 590 591 #ifdef BMAC_DEBUG 592 if (vtophys(va) + len - 1 != vtophys(va + len - 1)) 593 panic("bmac_transmit_packet"); 594 #endif 595 596 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, vtophys(va), 597 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 598 cmd++; 599 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 600 DBDMA_INT_ALWAYS, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 601 602 dbdma_start(sc->sc_txdma, sc->sc_txcmd); 603 } 604 605 int 606 bmac_put(struct bmac_softc *sc, void *buff, struct mbuf *m) 607 { 608 struct mbuf *n; 609 int len, tlen = 0; 610 611 for (; m; m = n) { 612 len = m->m_len; 613 if (len == 0) { 614 n = m_free(m); 615 continue; 616 } 617 memcpy(buff, mtod(m, void *), len); 618 buff = (char *)buff + len; 619 tlen += len; 620 n = m_free(m); 621 } 622 if (tlen > PAGE_SIZE) 623 panic("%s: putpacket packet overflow", 624 device_xname(sc->sc_dev)); 625 626 return tlen; 627 } 628 629 struct mbuf * 630 bmac_get(struct bmac_softc *sc, void *pkt, int totlen) 631 { 632 struct mbuf *m; 633 struct mbuf *top, **mp; 634 int len; 635 636 MGETHDR(m, M_DONTWAIT, MT_DATA); 637 if (m == 0) 638 return 0; 639 m_set_rcvif(m, &sc->sc_if); 640 m->m_pkthdr.len = totlen; 641 len = MHLEN; 642 top = 0; 643 mp = ⊤ 644 645 while (totlen > 0) { 646 if (top) { 647 MGET(m, M_DONTWAIT, MT_DATA); 648 if (m == 0) { 649 m_freem(top); 650 return 0; 651 } 652 len = MLEN; 653 } 654 if (totlen >= MINCLSIZE) { 655 MCLGET(m, M_DONTWAIT); 656 if ((m->m_flags & M_EXT) == 0) { 657 m_free(m); 658 m_freem(top); 659 return 0; 660 } 661 len = MCLBYTES; 662 } 663 m->m_len = len = uimin(totlen, len); 664 memcpy(mtod(m, void *), pkt, len); 665 pkt = (char *)pkt + len; 666 totlen -= len; 667 *mp = m; 668 mp = &m->m_next; 669 } 670 671 return top; 672 } 673 674 void 675 bmac_watchdog(struct ifnet *ifp) 676 { 677 struct bmac_softc *sc = ifp->if_softc; 678 679 bmac_reset_bits(sc, RXCFG, RxMACEnable); 680 bmac_reset_bits(sc, TXCFG, TxMACEnable); 681 682 printf("%s: device timeout\n", ifp->if_xname); 683 if_statinc(ifp, if_oerrors); 684 685 bmac_reset(sc); 686 } 687 688 int 689 bmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 690 { 691 struct bmac_softc *sc = ifp->if_softc; 692 struct ifaddr *ifa = (struct ifaddr *)data; 693 int s, error = 0; 694 695 s = splnet(); 696 697 switch (cmd) { 698 699 case SIOCINITIFADDR: 700 ifp->if_flags |= IFF_UP; 701 702 bmac_init(sc); 703 switch (ifa->ifa_addr->sa_family) { 704 #ifdef INET 705 case AF_INET: 706 arp_ifinit(ifp, ifa); 707 break; 708 #endif 709 default: 710 break; 711 } 712 break; 713 714 case SIOCSIFFLAGS: 715 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 716 break; 717 /* XXX see the comment in ed_ioctl() about code re-use */ 718 if ((ifp->if_flags & IFF_UP) == 0 && 719 (ifp->if_flags & IFF_RUNNING) != 0) { 720 /* 721 * If interface is marked down and it is running, then 722 * stop it. 723 */ 724 bmac_stop(sc); 725 ifp->if_flags &= ~IFF_RUNNING; 726 } else if ((ifp->if_flags & IFF_UP) != 0 && 727 (ifp->if_flags & IFF_RUNNING) == 0) { 728 /* 729 * If interface is marked up and it is stopped, then 730 * start it. 731 */ 732 bmac_init(sc); 733 } else { 734 /* 735 * Reset the interface to pick up changes in any other 736 * flags that affect hardware registers. 737 */ 738 /*bmac_stop(sc);*/ 739 bmac_init(sc); 740 } 741 #ifdef BMAC_DEBUG 742 if (ifp->if_flags & IFF_DEBUG) 743 sc->sc_flags |= BMAC_DEBUGFLAG; 744 #endif 745 break; 746 747 default: 748 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 749 /* 750 * Multicast list has changed; set the hardware filter 751 * accordingly. 752 */ 753 if (ifp->if_flags & IFF_RUNNING) { 754 bmac_init(sc); 755 bmac_setladrf(sc); 756 } 757 error = 0; 758 } 759 break; 760 } 761 762 splx(s); 763 return error; 764 } 765 766 /* 767 * Set up the logical address filter. 768 */ 769 void 770 bmac_setladrf(struct bmac_softc *sc) 771 { 772 struct ethercom *ec = &sc->sc_ethercom; 773 struct ifnet *ifp = &sc->sc_if; 774 struct ether_multi *enm; 775 struct ether_multistep step; 776 uint32_t crc; 777 uint16_t hash[4]; 778 int x; 779 780 /* 781 * Set up multicast address filter by passing all multicast addresses 782 * through a crc generator, and then using the high order 6 bits as an 783 * index into the 64 bit logical address filter. The high order bit 784 * selects the word, while the rest of the bits select the bit within 785 * the word. 786 */ 787 788 if (ifp->if_flags & IFF_PROMISC) { 789 bmac_set_bits(sc, RXCFG, RxPromiscEnable); 790 return; 791 } 792 793 if (ifp->if_flags & IFF_ALLMULTI) { 794 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 795 goto chipit; 796 } 797 798 hash[3] = hash[2] = hash[1] = hash[0] = 0; 799 800 ETHER_LOCK(ec); 801 ETHER_FIRST_MULTI(step, ec, enm); 802 while (enm != NULL) { 803 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 804 /* 805 * We must listen to a range of multicast addresses. 806 * For now, just accept all multicasts, rather than 807 * trying to set only those filter bits needed to match 808 * the range. (At this time, the only use of address 809 * ranges is for IP multicast routing, for which the 810 * range is big enough to require all bits set.) 811 */ 812 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 813 ifp->if_flags |= IFF_ALLMULTI; 814 ETHER_UNLOCK(ec); 815 goto chipit; 816 } 817 818 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 819 820 /* Just want the 6 most significant bits. */ 821 crc >>= 26; 822 823 /* Set the corresponding bit in the filter. */ 824 hash[crc >> 4] |= 1 << (crc & 0xf); 825 826 ETHER_NEXT_MULTI(step, enm); 827 } 828 ETHER_UNLOCK(ec); 829 830 ifp->if_flags &= ~IFF_ALLMULTI; 831 832 chipit: 833 bmac_write_reg(sc, HASH0, hash[0]); 834 bmac_write_reg(sc, HASH1, hash[1]); 835 bmac_write_reg(sc, HASH2, hash[2]); 836 bmac_write_reg(sc, HASH3, hash[3]); 837 x = bmac_read_reg(sc, RXCFG); 838 x &= ~RxPromiscEnable; 839 x |= RxHashFilterEnable; 840 bmac_write_reg(sc, RXCFG, x); 841 } 842 843 int 844 bmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 845 { 846 return mii_bitbang_readreg(self, &bmac_mbo, phy, reg, val); 847 } 848 849 int 850 bmac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 851 { 852 return mii_bitbang_writereg(self, &bmac_mbo, phy, reg, val); 853 } 854 855 uint32_t 856 bmac_mbo_read(device_t self) 857 { 858 struct bmac_softc *sc = device_private(self); 859 860 return bmac_read_reg(sc, MIFCSR); 861 } 862 863 void 864 bmac_mbo_write(device_t self, uint32_t val) 865 { 866 struct bmac_softc *sc = device_private(self); 867 868 bmac_write_reg(sc, MIFCSR, val); 869 } 870 871 void 872 bmac_mii_statchg(struct ifnet *ifp) 873 { 874 struct bmac_softc *sc = ifp->if_softc; 875 int x; 876 877 /* Update duplex mode in TX configuration */ 878 x = bmac_read_reg(sc, TXCFG); 879 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 880 x |= TxFullDuplex; 881 else 882 x &= ~TxFullDuplex; 883 bmac_write_reg(sc, TXCFG, x); 884 885 #ifdef BMAC_DEBUG 886 printf("bmac_mii_statchg 0x%x\n", 887 IFM_OPTIONS(sc->sc_mii.mii_media_active)); 888 #endif 889 } 890 891 void 892 bmac_mii_tick(void *v) 893 { 894 struct bmac_softc *sc = v; 895 int s; 896 897 s = splnet(); 898 mii_tick(&sc->sc_mii); 899 splx(s); 900 901 callout_reset(&sc->sc_tick_ch, hz, bmac_mii_tick, sc); 902 } 903