1 /* $NetBSD: if_bm.c,v 1.64 2021/03/05 07:15:53 rin Exp $ */ 2 3 /*- 4 * Copyright (C) 1998, 1999, 2000 Tsubai Masanari. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: if_bm.c,v 1.64 2021/03/05 07:15:53 rin Exp $"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/device.h> 36 #include <sys/ioctl.h> 37 #include <sys/kernel.h> 38 #include <sys/mbuf.h> 39 #include <sys/socket.h> 40 #include <sys/systm.h> 41 #include <sys/callout.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <net/if.h> 46 #include <net/if_dl.h> 47 #include <net/if_ether.h> 48 #include <net/if_media.h> 49 50 #include <net/bpf.h> 51 52 #ifdef INET 53 #include <netinet/in.h> 54 #include <netinet/if_inarp.h> 55 #endif 56 57 58 #include <dev/ofw/openfirm.h> 59 60 #include <dev/mii/mii.h> 61 #include <dev/mii/miivar.h> 62 #include <dev/mii/mii_bitbang.h> 63 64 #include <powerpc/spr.h> 65 #include <powerpc/oea/spr.h> 66 67 #include <machine/autoconf.h> 68 #include <machine/pio.h> 69 70 #include <macppc/dev/dbdma.h> 71 #include <macppc/dev/if_bmreg.h> 72 #include <macppc/dev/obiovar.h> 73 74 #define BMAC_TXBUFS 2 75 #define BMAC_RXBUFS 16 76 #define BMAC_BUFLEN 2048 77 78 struct bmac_softc { 79 device_t sc_dev; 80 struct ethercom sc_ethercom; 81 #define sc_if sc_ethercom.ec_if 82 struct callout sc_tick_ch; 83 bus_space_tag_t sc_iot; 84 bus_space_handle_t sc_ioh; 85 dbdma_regmap_t *sc_txdma; 86 dbdma_regmap_t *sc_rxdma; 87 dbdma_command_t *sc_txcmd; 88 dbdma_command_t *sc_rxcmd; 89 void *sc_txbuf; 90 void *sc_rxbuf; 91 int sc_rxlast; 92 int sc_flags; 93 struct mii_data sc_mii; 94 u_char sc_enaddr[6]; 95 }; 96 97 #define BMAC_BMACPLUS 0x01 98 #define BMAC_DEBUGFLAG 0x02 99 100 int bmac_match(device_t, cfdata_t, void *); 101 void bmac_attach(device_t, device_t, void *); 102 void bmac_reset_chip(struct bmac_softc *); 103 void bmac_init(struct bmac_softc *); 104 void bmac_init_dma(struct bmac_softc *); 105 int bmac_intr(void *); 106 int bmac_rint(void *); 107 void bmac_reset(struct bmac_softc *); 108 void bmac_stop(struct bmac_softc *); 109 void bmac_start(struct ifnet *); 110 void bmac_transmit_packet(struct bmac_softc *, void *, int); 111 int bmac_put(struct bmac_softc *, void *, struct mbuf *); 112 struct mbuf *bmac_get(struct bmac_softc *, void *, int); 113 void bmac_watchdog(struct ifnet *); 114 int bmac_ioctl(struct ifnet *, u_long, void *); 115 void bmac_setladrf(struct bmac_softc *); 116 117 int bmac_mii_readreg(device_t, int, int, uint16_t *); 118 int bmac_mii_writereg(device_t, int, int, uint16_t); 119 void bmac_mii_statchg(struct ifnet *); 120 void bmac_mii_tick(void *); 121 uint32_t bmac_mbo_read(device_t); 122 void bmac_mbo_write(device_t, uint32_t); 123 124 CFATTACH_DECL_NEW(bm, sizeof(struct bmac_softc), 125 bmac_match, bmac_attach, NULL, NULL); 126 127 const struct mii_bitbang_ops bmac_mbo = { 128 bmac_mbo_read, bmac_mbo_write, 129 { MIFDO, MIFDI, MIFDC, MIFDIR, 0 } 130 }; 131 132 static inline uint16_t 133 bmac_read_reg(struct bmac_softc *sc, bus_size_t off) 134 { 135 return bus_space_read_2(sc->sc_iot, sc->sc_ioh, off); 136 } 137 138 static inline void 139 bmac_write_reg(struct bmac_softc *sc, bus_size_t off, uint16_t val) 140 { 141 bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, val); 142 } 143 144 static inline void 145 bmac_set_bits(struct bmac_softc *sc, bus_size_t off, uint16_t val) 146 { 147 val |= bmac_read_reg(sc, off); 148 bmac_write_reg(sc, off, val); 149 } 150 151 static inline void 152 bmac_reset_bits(struct bmac_softc *sc, bus_size_t off, uint16_t val) 153 { 154 bmac_write_reg(sc, off, bmac_read_reg(sc, off) & ~val); 155 } 156 157 int 158 bmac_match(device_t parent, cfdata_t cf, void *aux) 159 { 160 struct confargs *ca = aux; 161 162 if (ca->ca_nreg < 24 || ca->ca_nintr < 12) 163 return 0; 164 165 if (strcmp(ca->ca_name, "bmac") == 0) /* bmac */ 166 return 1; 167 if (strcmp(ca->ca_name, "ethernet") == 0) /* bmac+ */ 168 return 1; 169 170 return 0; 171 } 172 173 void 174 bmac_attach(device_t parent, device_t self, void *aux) 175 { 176 struct confargs *ca = aux; 177 struct bmac_softc *sc = device_private(self); 178 struct ifnet *ifp = &sc->sc_if; 179 struct mii_data *mii = &sc->sc_mii; 180 u_char laddr[6]; 181 char intr_xname[INTRDEVNAMEBUF]; 182 183 callout_init(&sc->sc_tick_ch, 0); 184 185 sc->sc_dev = self; 186 sc->sc_flags = 0; 187 if (strcmp(ca->ca_name, "ethernet") == 0) { 188 char name[64]; 189 190 memset(name, 0, 64); 191 OF_package_to_path(ca->ca_node, name, sizeof(name)); 192 OF_open(name); 193 sc->sc_flags |= BMAC_BMACPLUS; 194 } 195 196 ca->ca_reg[0] += ca->ca_baseaddr; 197 ca->ca_reg[2] += ca->ca_baseaddr; 198 ca->ca_reg[4] += ca->ca_baseaddr; 199 200 sc->sc_iot = ca->ca_tag; 201 if (bus_space_map(sc->sc_iot, ca->ca_reg[0], ca->ca_reg[1], 0, 202 &sc->sc_ioh) != 0) { 203 aprint_error(": couldn't map %#x", ca->ca_reg[0]); 204 return; 205 } 206 207 bmac_write_reg(sc, INTDISABLE, NoEventsMask); 208 209 if (OF_getprop(ca->ca_node, "local-mac-address", laddr, 6) == -1 && 210 OF_getprop(ca->ca_node, "mac-address", laddr, 6) == -1) { 211 aprint_error(": cannot get mac-address\n"); 212 return; 213 } 214 memcpy(sc->sc_enaddr, laddr, 6); 215 216 sc->sc_txdma = mapiodev(ca->ca_reg[2], PAGE_SIZE, false); 217 sc->sc_rxdma = mapiodev(ca->ca_reg[4], PAGE_SIZE, false); 218 sc->sc_txcmd = dbdma_alloc(BMAC_TXBUFS * sizeof(dbdma_command_t), NULL); 219 sc->sc_rxcmd = dbdma_alloc((BMAC_RXBUFS + 1) * sizeof(dbdma_command_t), 220 NULL); 221 sc->sc_txbuf = malloc(BMAC_BUFLEN * BMAC_TXBUFS, M_DEVBUF, M_WAITOK); 222 sc->sc_rxbuf = malloc(BMAC_BUFLEN * BMAC_RXBUFS, M_DEVBUF, M_WAITOK); 223 224 aprint_normal(" irq %d,%d: address %s\n", 225 ca->ca_intr[0], ca->ca_intr[2], 226 ether_sprintf(laddr)); 227 228 snprintf(intr_xname, sizeof(intr_xname), "%s tx", device_xname(self)); 229 intr_establish_xname(ca->ca_intr[0], IST_EDGE, IPL_NET, bmac_intr, sc, 230 intr_xname); 231 232 snprintf(intr_xname, sizeof(intr_xname), "%s rx", device_xname(self)); 233 intr_establish_xname(ca->ca_intr[2], IST_EDGE, IPL_NET, bmac_rint, sc, 234 intr_xname); 235 236 memcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 237 ifp->if_softc = sc; 238 ifp->if_ioctl = bmac_ioctl; 239 ifp->if_start = bmac_start; 240 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 241 ifp->if_watchdog = bmac_watchdog; 242 IFQ_SET_READY(&ifp->if_snd); 243 244 mii->mii_ifp = ifp; 245 mii->mii_readreg = bmac_mii_readreg; 246 mii->mii_writereg = bmac_mii_writereg; 247 mii->mii_statchg = bmac_mii_statchg; 248 249 sc->sc_ethercom.ec_mii = mii; 250 ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus); 251 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, 0); 252 253 /* Choose a default media. */ 254 if (LIST_FIRST(&mii->mii_phys) == NULL) { 255 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_10_T, 0, NULL); 256 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_10_T); 257 } else 258 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 259 260 bmac_reset_chip(sc); 261 262 if_attach(ifp); 263 if_deferred_start_init(ifp, NULL); 264 ether_ifattach(ifp, sc->sc_enaddr); 265 } 266 267 /* 268 * Reset and enable bmac by heathrow FCR. 269 */ 270 void 271 bmac_reset_chip(struct bmac_softc *sc) 272 { 273 u_int v; 274 275 dbdma_reset(sc->sc_txdma); 276 dbdma_reset(sc->sc_rxdma); 277 278 v = obio_read_4(HEATHROW_FCR); 279 280 v |= EnetEnable; 281 obio_write_4(HEATHROW_FCR, v); 282 delay(50000); 283 284 v |= ResetEnetCell; 285 obio_write_4(HEATHROW_FCR, v); 286 delay(50000); 287 288 v &= ~ResetEnetCell; 289 obio_write_4(HEATHROW_FCR, v); 290 delay(50000); 291 292 obio_write_4(HEATHROW_FCR, v); 293 } 294 295 void 296 bmac_init(struct bmac_softc *sc) 297 { 298 struct ifnet *ifp = &sc->sc_if; 299 struct ether_header *eh; 300 void *data; 301 int i, tb; 302 uint16_t bmcr; 303 u_short *p; 304 305 bmac_reset_chip(sc); 306 307 /* XXX */ 308 bmac_mii_readreg(sc->sc_dev, 0, MII_BMCR, &bmcr); 309 bmcr &= ~BMCR_ISO; 310 bmac_mii_writereg(sc->sc_dev, 0, MII_BMCR, bmcr); 311 312 bmac_write_reg(sc, RXRST, RxResetValue); 313 bmac_write_reg(sc, TXRST, TxResetBit); 314 315 /* Wait for reset completion. */ 316 for (i = 1000; i > 0; i -= 10) { 317 if ((bmac_read_reg(sc, TXRST) & TxResetBit) == 0) 318 break; 319 delay(10); 320 } 321 if (i <= 0) 322 printf("%s: reset timeout\n", ifp->if_xname); 323 324 if (! (sc->sc_flags & BMAC_BMACPLUS)) 325 bmac_set_bits(sc, XCVRIF, ClkBit | SerialMode | COLActiveLow); 326 327 if ((mfpvr() >> 16) == MPC601) 328 tb = mfrtcl(); 329 else 330 tb = mftbl(); 331 bmac_write_reg(sc, RSEED, tb); 332 bmac_set_bits(sc, XIFC, TxOutputEnable); 333 bmac_read_reg(sc, PAREG); 334 335 /* Reset various counters. */ 336 bmac_write_reg(sc, NCCNT, 0); 337 bmac_write_reg(sc, NTCNT, 0); 338 bmac_write_reg(sc, EXCNT, 0); 339 bmac_write_reg(sc, LTCNT, 0); 340 bmac_write_reg(sc, FRCNT, 0); 341 bmac_write_reg(sc, LECNT, 0); 342 bmac_write_reg(sc, AECNT, 0); 343 bmac_write_reg(sc, FECNT, 0); 344 bmac_write_reg(sc, RXCV, 0); 345 346 /* Set tx fifo information. */ 347 bmac_write_reg(sc, TXTH, 4); /* 4 octets before tx starts */ 348 349 bmac_write_reg(sc, TXFIFOCSR, 0); 350 bmac_write_reg(sc, TXFIFOCSR, TxFIFOEnable); 351 352 /* Set rx fifo information. */ 353 bmac_write_reg(sc, RXFIFOCSR, 0); 354 bmac_write_reg(sc, RXFIFOCSR, RxFIFOEnable); 355 356 /* Clear status register. */ 357 bmac_read_reg(sc, STATUS); 358 359 bmac_write_reg(sc, HASH3, 0); 360 bmac_write_reg(sc, HASH2, 0); 361 bmac_write_reg(sc, HASH1, 0); 362 bmac_write_reg(sc, HASH0, 0); 363 364 /* Set MAC address. */ 365 p = (u_short *)sc->sc_enaddr; 366 bmac_write_reg(sc, MADD0, *p++); 367 bmac_write_reg(sc, MADD1, *p++); 368 bmac_write_reg(sc, MADD2, *p); 369 370 bmac_write_reg(sc, RXCFG, 371 RxCRCEnable | RxHashFilterEnable | RxRejectOwnPackets); 372 373 if (ifp->if_flags & IFF_PROMISC) 374 bmac_set_bits(sc, RXCFG, RxPromiscEnable); 375 376 bmac_init_dma(sc); 377 378 /* Enable TX/RX */ 379 bmac_set_bits(sc, RXCFG, RxMACEnable); 380 bmac_set_bits(sc, TXCFG, TxMACEnable); 381 382 bmac_write_reg(sc, INTDISABLE, NormalIntEvents); 383 384 ifp->if_flags |= IFF_RUNNING; 385 ifp->if_flags &= ~IFF_OACTIVE; 386 ifp->if_timer = 0; 387 388 data = sc->sc_txbuf; 389 eh = (struct ether_header *)data; 390 391 memset(data, 0, sizeof(eh) + ETHERMIN); 392 memcpy(eh->ether_dhost, sc->sc_enaddr, ETHER_ADDR_LEN); 393 memcpy(eh->ether_shost, sc->sc_enaddr, ETHER_ADDR_LEN); 394 bmac_transmit_packet(sc, data, sizeof(eh) + ETHERMIN); 395 396 bmac_start(ifp); 397 398 callout_reset(&sc->sc_tick_ch, hz, bmac_mii_tick, sc); 399 } 400 401 void 402 bmac_init_dma(struct bmac_softc *sc) 403 { 404 dbdma_command_t *cmd = sc->sc_rxcmd; 405 int i; 406 407 dbdma_reset(sc->sc_txdma); 408 dbdma_reset(sc->sc_rxdma); 409 410 memset(sc->sc_txcmd, 0, BMAC_TXBUFS * sizeof(dbdma_command_t)); 411 memset(sc->sc_rxcmd, 0, (BMAC_RXBUFS + 1) * sizeof(dbdma_command_t)); 412 413 for (i = 0; i < BMAC_RXBUFS; i++) { 414 DBDMA_BUILD(cmd, DBDMA_CMD_IN_LAST, 0, BMAC_BUFLEN, 415 vtophys((vaddr_t)sc->sc_rxbuf + BMAC_BUFLEN * i), 416 DBDMA_INT_ALWAYS, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 417 cmd++; 418 } 419 DBDMA_BUILD(cmd, DBDMA_CMD_NOP, 0, 0, 0, 420 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_ALWAYS); 421 out32rb(&cmd->d_cmddep, vtophys((vaddr_t)sc->sc_rxcmd)); 422 423 sc->sc_rxlast = 0; 424 425 dbdma_start(sc->sc_rxdma, sc->sc_rxcmd); 426 } 427 428 int 429 bmac_intr(void *v) 430 { 431 struct bmac_softc *sc = v; 432 int stat; 433 434 stat = bmac_read_reg(sc, STATUS); 435 if (stat == 0) 436 return 0; 437 438 #ifdef BMAC_DEBUG 439 printf("bmac_intr status = 0x%x\n", stat); 440 #endif 441 442 if (stat & IntFrameSent) { 443 sc->sc_if.if_flags &= ~IFF_OACTIVE; 444 sc->sc_if.if_timer = 0; 445 if_statinc(&sc->sc_if, if_opackets); 446 if_schedule_deferred_start(&sc->sc_if); 447 } 448 449 /* XXX should do more! */ 450 451 return 1; 452 } 453 454 int 455 bmac_rint(void *v) 456 { 457 struct bmac_softc *sc = v; 458 struct ifnet *ifp = &sc->sc_if; 459 struct mbuf *m; 460 dbdma_command_t *cmd; 461 int status, resid, count, datalen; 462 int i, n; 463 void *data; 464 465 i = sc->sc_rxlast; 466 for (n = 0; n < BMAC_RXBUFS; n++, i++) { 467 if (i == BMAC_RXBUFS) 468 i = 0; 469 cmd = &sc->sc_rxcmd[i]; 470 status = in16rb(&cmd->d_status); 471 resid = in16rb(&cmd->d_resid); 472 473 #ifdef BMAC_DEBUG 474 if (status != 0 && status != 0x8440 && status != 0x9440) 475 printf("bmac_rint status = 0x%x\n", status); 476 #endif 477 478 if ((status & DBDMA_CNTRL_ACTIVE) == 0) /* 0x9440 | 0x8440 */ 479 continue; 480 count = in16rb(&cmd->d_count); 481 datalen = count - resid - 2; /* 2 == framelen */ 482 if (datalen < sizeof(struct ether_header)) { 483 printf("%s: short packet len = %d\n", 484 ifp->if_xname, datalen); 485 goto next; 486 } 487 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 0); 488 data = (char *)sc->sc_rxbuf + BMAC_BUFLEN * i; 489 490 /* XXX Sometimes bmac reads one extra byte. */ 491 if (datalen == ETHER_MAX_LEN + 1) 492 datalen--; 493 494 /* Trim the CRC. */ 495 datalen -= ETHER_CRC_LEN; 496 497 m = bmac_get(sc, data, datalen); 498 if (m == NULL) { 499 if_statinc(ifp, if_ierrors); 500 goto next; 501 } 502 503 if_percpuq_enqueue(ifp->if_percpuq, m); 504 505 next: 506 DBDMA_BUILD_CMD(cmd, DBDMA_CMD_IN_LAST, 0, DBDMA_INT_ALWAYS, 507 DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 508 509 cmd->d_status = 0; 510 cmd->d_resid = 0; 511 sc->sc_rxlast = i + 1; 512 } 513 ether_mediachange(ifp); 514 515 dbdma_continue(sc->sc_rxdma); 516 517 return 1; 518 } 519 520 void 521 bmac_reset(struct bmac_softc *sc) 522 { 523 int s; 524 525 s = splnet(); 526 bmac_init(sc); 527 splx(s); 528 } 529 530 void 531 bmac_stop(struct bmac_softc *sc) 532 { 533 struct ifnet *ifp = &sc->sc_if; 534 int s; 535 536 s = splnet(); 537 538 callout_stop(&sc->sc_tick_ch); 539 mii_down(&sc->sc_mii); 540 541 /* Disable TX/RX. */ 542 bmac_reset_bits(sc, TXCFG, TxMACEnable); 543 bmac_reset_bits(sc, RXCFG, RxMACEnable); 544 545 /* Disable all interrupts. */ 546 bmac_write_reg(sc, INTDISABLE, NoEventsMask); 547 548 dbdma_stop(sc->sc_txdma); 549 dbdma_stop(sc->sc_rxdma); 550 551 ifp->if_flags &= ~(IFF_UP | IFF_RUNNING); 552 ifp->if_timer = 0; 553 554 splx(s); 555 } 556 557 void 558 bmac_start(struct ifnet *ifp) 559 { 560 struct bmac_softc *sc = ifp->if_softc; 561 struct mbuf *m; 562 int tlen; 563 564 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 565 return; 566 567 while (1) { 568 if (ifp->if_flags & IFF_OACTIVE) 569 return; 570 571 IFQ_DEQUEUE(&ifp->if_snd, m); 572 if (m == 0) 573 break; 574 /* 575 * If BPF is listening on this interface, let it see the 576 * packet before we commit it to the wire. 577 */ 578 bpf_mtap(ifp, m, BPF_D_OUT); 579 580 ifp->if_flags |= IFF_OACTIVE; 581 tlen = bmac_put(sc, sc->sc_txbuf, m); 582 583 /* 5 seconds to watch for failing to transmit */ 584 ifp->if_timer = 5; 585 if_statinc(ifp, if_opackets); /* # of pkts */ 586 587 bmac_transmit_packet(sc, sc->sc_txbuf, tlen); 588 } 589 } 590 591 void 592 bmac_transmit_packet(struct bmac_softc *sc, void *buff, int len) 593 { 594 dbdma_command_t *cmd = sc->sc_txcmd; 595 vaddr_t va = (vaddr_t)buff; 596 597 #ifdef BMAC_DEBUG 598 if (vtophys(va) + len - 1 != vtophys(va + len - 1)) 599 panic("bmac_transmit_packet"); 600 #endif 601 602 DBDMA_BUILD(cmd, DBDMA_CMD_OUT_LAST, 0, len, vtophys(va), 603 DBDMA_INT_NEVER, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 604 cmd++; 605 DBDMA_BUILD(cmd, DBDMA_CMD_STOP, 0, 0, 0, 606 DBDMA_INT_ALWAYS, DBDMA_WAIT_NEVER, DBDMA_BRANCH_NEVER); 607 608 dbdma_start(sc->sc_txdma, sc->sc_txcmd); 609 } 610 611 int 612 bmac_put(struct bmac_softc *sc, void *buff, struct mbuf *m) 613 { 614 struct mbuf *n; 615 int len, tlen = 0; 616 617 for (; m; m = n) { 618 len = m->m_len; 619 if (len == 0) { 620 n = m_free(m); 621 continue; 622 } 623 memcpy(buff, mtod(m, void *), len); 624 buff = (char *)buff + len; 625 tlen += len; 626 n = m_free(m); 627 } 628 if (tlen > PAGE_SIZE) 629 panic("%s: putpacket packet overflow", 630 device_xname(sc->sc_dev)); 631 632 return tlen; 633 } 634 635 struct mbuf * 636 bmac_get(struct bmac_softc *sc, void *pkt, int totlen) 637 { 638 struct mbuf *m; 639 struct mbuf *top, **mp; 640 int len; 641 642 MGETHDR(m, M_DONTWAIT, MT_DATA); 643 if (m == 0) 644 return 0; 645 m_set_rcvif(m, &sc->sc_if); 646 m->m_pkthdr.len = totlen; 647 len = MHLEN; 648 top = 0; 649 mp = ⊤ 650 651 while (totlen > 0) { 652 if (top) { 653 MGET(m, M_DONTWAIT, MT_DATA); 654 if (m == 0) { 655 m_freem(top); 656 return 0; 657 } 658 len = MLEN; 659 } 660 if (totlen >= MINCLSIZE) { 661 MCLGET(m, M_DONTWAIT); 662 if ((m->m_flags & M_EXT) == 0) { 663 m_free(m); 664 m_freem(top); 665 return 0; 666 } 667 len = MCLBYTES; 668 } 669 m->m_len = len = uimin(totlen, len); 670 memcpy(mtod(m, void *), pkt, len); 671 pkt = (char *)pkt + len; 672 totlen -= len; 673 *mp = m; 674 mp = &m->m_next; 675 } 676 677 return top; 678 } 679 680 void 681 bmac_watchdog(struct ifnet *ifp) 682 { 683 struct bmac_softc *sc = ifp->if_softc; 684 685 bmac_reset_bits(sc, RXCFG, RxMACEnable); 686 bmac_reset_bits(sc, TXCFG, TxMACEnable); 687 688 printf("%s: device timeout\n", ifp->if_xname); 689 if_statinc(ifp, if_oerrors); 690 691 bmac_reset(sc); 692 } 693 694 int 695 bmac_ioctl(struct ifnet *ifp, unsigned long cmd, void *data) 696 { 697 struct bmac_softc *sc = ifp->if_softc; 698 struct ifaddr *ifa = (struct ifaddr *)data; 699 int s, error = 0; 700 701 s = splnet(); 702 703 switch (cmd) { 704 705 case SIOCINITIFADDR: 706 ifp->if_flags |= IFF_UP; 707 708 bmac_init(sc); 709 switch (ifa->ifa_addr->sa_family) { 710 #ifdef INET 711 case AF_INET: 712 arp_ifinit(ifp, ifa); 713 break; 714 #endif 715 default: 716 break; 717 } 718 break; 719 720 case SIOCSIFFLAGS: 721 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 722 break; 723 /* XXX see the comment in ed_ioctl() about code re-use */ 724 if ((ifp->if_flags & IFF_UP) == 0 && 725 (ifp->if_flags & IFF_RUNNING) != 0) { 726 /* 727 * If interface is marked down and it is running, then 728 * stop it. 729 */ 730 bmac_stop(sc); 731 ifp->if_flags &= ~IFF_RUNNING; 732 } else if ((ifp->if_flags & IFF_UP) != 0 && 733 (ifp->if_flags & IFF_RUNNING) == 0) { 734 /* 735 * If interface is marked up and it is stopped, then 736 * start it. 737 */ 738 bmac_init(sc); 739 } else { 740 /* 741 * Reset the interface to pick up changes in any other 742 * flags that affect hardware registers. 743 */ 744 /*bmac_stop(sc);*/ 745 bmac_init(sc); 746 } 747 #ifdef BMAC_DEBUG 748 if (ifp->if_flags & IFF_DEBUG) 749 sc->sc_flags |= BMAC_DEBUGFLAG; 750 #endif 751 break; 752 753 default: 754 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 755 /* 756 * Multicast list has changed; set the hardware filter 757 * accordingly. 758 */ 759 if (ifp->if_flags & IFF_RUNNING) { 760 bmac_init(sc); 761 bmac_setladrf(sc); 762 } 763 error = 0; 764 } 765 break; 766 } 767 768 splx(s); 769 return error; 770 } 771 772 /* 773 * Set up the logical address filter. 774 */ 775 void 776 bmac_setladrf(struct bmac_softc *sc) 777 { 778 struct ethercom *ec = &sc->sc_ethercom; 779 struct ifnet *ifp = &sc->sc_if; 780 struct ether_multi *enm; 781 struct ether_multistep step; 782 uint32_t crc; 783 uint16_t hash[4]; 784 int x; 785 786 /* 787 * Set up multicast address filter by passing all multicast addresses 788 * through a crc generator, and then using the high order 6 bits as an 789 * index into the 64 bit logical address filter. The high order bit 790 * selects the word, while the rest of the bits select the bit within 791 * the word. 792 */ 793 794 if (ifp->if_flags & IFF_PROMISC) { 795 bmac_set_bits(sc, RXCFG, RxPromiscEnable); 796 return; 797 } 798 799 if (ifp->if_flags & IFF_ALLMULTI) { 800 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 801 goto chipit; 802 } 803 804 hash[3] = hash[2] = hash[1] = hash[0] = 0; 805 806 ETHER_LOCK(ec); 807 ETHER_FIRST_MULTI(step, ec, enm); 808 while (enm != NULL) { 809 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 810 /* 811 * We must listen to a range of multicast addresses. 812 * For now, just accept all multicasts, rather than 813 * trying to set only those filter bits needed to match 814 * the range. (At this time, the only use of address 815 * ranges is for IP multicast routing, for which the 816 * range is big enough to require all bits set.) 817 */ 818 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff; 819 ifp->if_flags |= IFF_ALLMULTI; 820 ETHER_UNLOCK(ec); 821 goto chipit; 822 } 823 824 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); 825 826 /* Just want the 6 most significant bits. */ 827 crc >>= 26; 828 829 /* Set the corresponding bit in the filter. */ 830 hash[crc >> 4] |= 1 << (crc & 0xf); 831 832 ETHER_NEXT_MULTI(step, enm); 833 } 834 ETHER_UNLOCK(ec); 835 836 ifp->if_flags &= ~IFF_ALLMULTI; 837 838 chipit: 839 bmac_write_reg(sc, HASH0, hash[0]); 840 bmac_write_reg(sc, HASH1, hash[1]); 841 bmac_write_reg(sc, HASH2, hash[2]); 842 bmac_write_reg(sc, HASH3, hash[3]); 843 x = bmac_read_reg(sc, RXCFG); 844 x &= ~RxPromiscEnable; 845 x |= RxHashFilterEnable; 846 bmac_write_reg(sc, RXCFG, x); 847 } 848 849 int 850 bmac_mii_readreg(device_t self, int phy, int reg, uint16_t *val) 851 { 852 return mii_bitbang_readreg(self, &bmac_mbo, phy, reg, val); 853 } 854 855 int 856 bmac_mii_writereg(device_t self, int phy, int reg, uint16_t val) 857 { 858 return mii_bitbang_writereg(self, &bmac_mbo, phy, reg, val); 859 } 860 861 uint32_t 862 bmac_mbo_read(device_t self) 863 { 864 struct bmac_softc *sc = device_private(self); 865 866 return bmac_read_reg(sc, MIFCSR); 867 } 868 869 void 870 bmac_mbo_write(device_t self, uint32_t val) 871 { 872 struct bmac_softc *sc = device_private(self); 873 874 bmac_write_reg(sc, MIFCSR, val); 875 } 876 877 void 878 bmac_mii_statchg(struct ifnet *ifp) 879 { 880 struct bmac_softc *sc = ifp->if_softc; 881 int x; 882 883 /* Update duplex mode in TX configuration */ 884 x = bmac_read_reg(sc, TXCFG); 885 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) 886 x |= TxFullDuplex; 887 else 888 x &= ~TxFullDuplex; 889 bmac_write_reg(sc, TXCFG, x); 890 891 #ifdef BMAC_DEBUG 892 printf("bmac_mii_statchg 0x%x\n", 893 IFM_OPTIONS(sc->sc_mii.mii_media_active)); 894 #endif 895 } 896 897 void 898 bmac_mii_tick(void *v) 899 { 900 struct bmac_softc *sc = v; 901 int s; 902 903 s = splnet(); 904 mii_tick(&sc->sc_mii); 905 splx(s); 906 907 callout_reset(&sc->sc_tick_ch, hz, bmac_mii_tick, sc); 908 } 909