1 /* $NetBSD: cuda.c,v 1.21 2016/02/14 19:54:20 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: cuda.c,v 1.21 2016/02/14 19:54:20 chs Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/proc.h> 37 #include <sys/mutex.h> 38 39 #include <sys/bus.h> 40 #include <machine/autoconf.h> 41 #include <machine/pio.h> 42 #include <dev/clock_subr.h> 43 #include <dev/i2c/i2cvar.h> 44 45 #include <macppc/dev/viareg.h> 46 #include <macppc/dev/cudavar.h> 47 48 #include <dev/ofw/openfirm.h> 49 #include <dev/adb/adbvar.h> 50 #include "opt_cuda.h" 51 52 #ifdef CUDA_DEBUG 53 #define DPRINTF printf 54 #else 55 #define DPRINTF while (0) printf 56 #endif 57 58 #define CUDA_NOTREADY 0x1 /* has not been initialized yet */ 59 #define CUDA_IDLE 0x2 /* the bus is currently idle */ 60 #define CUDA_OUT 0x3 /* sending out a command */ 61 #define CUDA_IN 0x4 /* receiving data */ 62 #define CUDA_POLLING 0x5 /* polling - II only */ 63 64 static void cuda_attach(device_t, device_t, void *); 65 static int cuda_match(device_t, struct cfdata *, void *); 66 static void cuda_autopoll(void *, int); 67 68 static int cuda_intr(void *); 69 70 typedef struct _cuda_handler { 71 int (*handler)(void *, int, uint8_t *); 72 void *cookie; 73 } CudaHandler; 74 75 struct cuda_softc { 76 device_t sc_dev; 77 void *sc_ih; 78 CudaHandler sc_handlers[16]; 79 struct todr_chip_handle sc_todr; 80 struct adb_bus_accessops sc_adbops; 81 struct i2c_controller sc_i2c; 82 kmutex_t sc_buslock; 83 bus_space_tag_t sc_memt; 84 bus_space_handle_t sc_memh; 85 int sc_node; 86 int sc_state; 87 int sc_waiting; 88 int sc_polling; 89 int sc_sent; 90 int sc_out_length; 91 int sc_received; 92 int sc_iic_done; 93 int sc_error; 94 /* time */ 95 uint32_t sc_tod; 96 uint32_t sc_autopoll; 97 uint32_t sc_todev; 98 /* ADB */ 99 void (*sc_adb_handler)(void *, int, uint8_t *); 100 void *sc_adb_cookie; 101 uint32_t sc_i2c_read_len; 102 /* internal buffers */ 103 uint8_t sc_in[256]; 104 uint8_t sc_out[256]; 105 }; 106 107 CFATTACH_DECL_NEW(cuda, sizeof(struct cuda_softc), 108 cuda_match, cuda_attach, NULL, NULL); 109 110 static inline void cuda_write_reg(struct cuda_softc *, int, uint8_t); 111 static inline uint8_t cuda_read_reg(struct cuda_softc *, int); 112 static void cuda_idle(struct cuda_softc *); 113 static void cuda_tip(struct cuda_softc *); 114 static void cuda_clear_tip(struct cuda_softc *); 115 static void cuda_in(struct cuda_softc *); 116 static void cuda_out(struct cuda_softc *); 117 static void cuda_toggle_ack(struct cuda_softc *); 118 static void cuda_ack_off(struct cuda_softc *); 119 static int cuda_intr_state(struct cuda_softc *); 120 121 static void cuda_init(struct cuda_softc *); 122 123 /* 124 * send a message to Cuda. 125 */ 126 /* cookie, flags, length, data */ 127 static int cuda_send(void *, int, int, uint8_t *); 128 static void cuda_poll(void *); 129 static void cuda_adb_poll(void *); 130 static int cuda_set_handler(void *, int, int (*)(void *, int, uint8_t *), void *); 131 132 static int cuda_error_handler(void *, int, uint8_t *); 133 134 static int cuda_todr_handler(void *, int, uint8_t *); 135 static int cuda_todr_set(todr_chip_handle_t, struct timeval *); 136 static int cuda_todr_get(todr_chip_handle_t, struct timeval *); 137 138 static int cuda_adb_handler(void *, int, uint8_t *); 139 static void cuda_final(device_t); 140 141 static struct cuda_attach_args *cuda0 = NULL; 142 143 /* ADB bus attachment stuff */ 144 static int cuda_adb_send(void *, int, int, int, uint8_t *); 145 static int cuda_adb_set_handler(void *, void (*)(void *, int, uint8_t *), void *); 146 147 /* i2c stuff */ 148 static int cuda_i2c_acquire_bus(void *, int); 149 static void cuda_i2c_release_bus(void *, int); 150 static int cuda_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *, size_t, 151 void *, size_t, int); 152 153 static int 154 cuda_match(device_t parent, struct cfdata *cf, void *aux) 155 { 156 struct confargs *ca = aux; 157 158 if (ca->ca_nreg < 8) 159 return 0; 160 161 if (ca->ca_nintr < 4) 162 return 0; 163 164 if (strcmp(ca->ca_name, "via-cuda") == 0) { 165 return 10; /* beat adb* at obio? */ 166 } 167 168 return 0; 169 } 170 171 static void 172 cuda_attach(device_t parent, device_t self, void *aux) 173 { 174 struct confargs *ca = aux; 175 struct cuda_softc *sc = device_private(self); 176 struct i2cbus_attach_args iba; 177 static struct cuda_attach_args caa; 178 int irq = ca->ca_intr[0]; 179 int node, i, child; 180 char name[32]; 181 182 sc->sc_dev = self; 183 node = of_getnode_byname(OF_parent(ca->ca_node), "extint-gpio1"); 184 if (node) 185 OF_getprop(node, "interrupts", &irq, 4); 186 187 aprint_normal(" irq %d", irq); 188 189 sc->sc_node = ca->ca_node; 190 sc->sc_memt = ca->ca_tag; 191 192 sc->sc_sent = 0; 193 sc->sc_received = 0; 194 sc->sc_waiting = 0; 195 sc->sc_polling = 0; 196 sc->sc_state = CUDA_NOTREADY; 197 sc->sc_error = 0; 198 sc->sc_i2c_read_len = 0; 199 200 if (bus_space_map(sc->sc_memt, ca->ca_reg[0] + ca->ca_baseaddr, 201 ca->ca_reg[1], 0, &sc->sc_memh) != 0) { 202 203 aprint_normal(": unable to map registers\n"); 204 return; 205 } 206 sc->sc_ih = intr_establish(irq, IST_EDGE, IPL_TTY, cuda_intr, sc); 207 printf("\n"); 208 209 for (i = 0; i < 16; i++) { 210 sc->sc_handlers[i].handler = NULL; 211 sc->sc_handlers[i].cookie = NULL; 212 } 213 214 cuda_init(sc); 215 216 /* now attach children */ 217 config_interrupts(self, cuda_final); 218 cuda_set_handler(sc, CUDA_ERROR, cuda_error_handler, sc); 219 cuda_set_handler(sc, CUDA_PSEUDO, cuda_todr_handler, sc); 220 221 child = OF_child(ca->ca_node); 222 while (child != 0) { 223 224 if (OF_getprop(child, "name", name, 32) == 0) 225 continue; 226 if (strncmp(name, "adb", 4) == 0) { 227 228 cuda_set_handler(sc, CUDA_ADB, cuda_adb_handler, sc); 229 sc->sc_adbops.cookie = sc; 230 sc->sc_adbops.send = cuda_adb_send; 231 sc->sc_adbops.poll = cuda_adb_poll; 232 sc->sc_adbops.autopoll = cuda_autopoll; 233 sc->sc_adbops.set_handler = cuda_adb_set_handler; 234 config_found_ia(self, "adb_bus", &sc->sc_adbops, 235 nadb_print); 236 } else if (strncmp(name, "rtc", 4) == 0) { 237 238 sc->sc_todr.todr_gettime = cuda_todr_get; 239 sc->sc_todr.todr_settime = cuda_todr_set; 240 sc->sc_todr.cookie = sc; 241 todr_attach(&sc->sc_todr); 242 } 243 child = OF_peer(child); 244 } 245 246 caa.cookie = sc; 247 caa.set_handler = cuda_set_handler; 248 caa.send = cuda_send; 249 caa.poll = cuda_poll; 250 #if notyet 251 config_found(self, &caa, cuda_print); 252 #endif 253 mutex_init(&sc->sc_buslock, MUTEX_DEFAULT, IPL_NONE); 254 memset(&iba, 0, sizeof(iba)); 255 iba.iba_tag = &sc->sc_i2c; 256 sc->sc_i2c.ic_cookie = sc; 257 sc->sc_i2c.ic_acquire_bus = cuda_i2c_acquire_bus; 258 sc->sc_i2c.ic_release_bus = cuda_i2c_release_bus; 259 sc->sc_i2c.ic_send_start = NULL; 260 sc->sc_i2c.ic_send_stop = NULL; 261 sc->sc_i2c.ic_initiate_xfer = NULL; 262 sc->sc_i2c.ic_read_byte = NULL; 263 sc->sc_i2c.ic_write_byte = NULL; 264 sc->sc_i2c.ic_exec = cuda_i2c_exec; 265 config_found_ia(self, "i2cbus", &iba, iicbus_print); 266 267 if (cuda0 == NULL) 268 cuda0 = &caa; 269 } 270 271 static void 272 cuda_init(struct cuda_softc *sc) 273 { 274 uint8_t reg; 275 276 reg = cuda_read_reg(sc, vDirB); 277 reg |= 0x30; /* register B bits 4 and 5: outputs */ 278 cuda_write_reg(sc, vDirB, reg); 279 280 reg = cuda_read_reg(sc, vDirB); 281 reg &= 0xf7; /* register B bit 3: input */ 282 cuda_write_reg(sc, vDirB, reg); 283 284 reg = cuda_read_reg(sc, vACR); 285 reg &= ~vSR_OUT; /* make sure SR is set to IN */ 286 cuda_write_reg(sc, vACR, reg); 287 288 cuda_write_reg(sc, vACR, (cuda_read_reg(sc, vACR) | 0x0c) & ~0x10); 289 290 sc->sc_state = CUDA_IDLE; /* used by all types of hardware */ 291 292 cuda_write_reg(sc, vIER, 0x84); /* make sure VIA interrupts are on */ 293 cuda_idle(sc); /* set ADB bus state to idle */ 294 295 /* sort of a device reset */ 296 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 297 cuda_write_reg(sc, vIER, 0x04); /* no interrupts while clearing */ 298 cuda_idle(sc); /* reset state to idle */ 299 delay(150); 300 cuda_tip(sc); /* signal start of frame */ 301 delay(150); 302 cuda_toggle_ack(sc); 303 delay(150); 304 cuda_clear_tip(sc); 305 delay(150); 306 cuda_idle(sc); /* back to idle state */ 307 (void)cuda_read_reg(sc, vSR); /* clear interrupt */ 308 cuda_write_reg(sc, vIER, 0x84); /* ints ok now */ 309 } 310 311 static void 312 cuda_final(device_t dev) 313 { 314 struct cuda_softc *sc = device_private(dev); 315 316 sc->sc_polling = 0; 317 } 318 319 static inline void 320 cuda_write_reg(struct cuda_softc *sc, int offset, uint8_t value) 321 { 322 323 bus_space_write_1(sc->sc_memt, sc->sc_memh, offset, value); 324 } 325 326 static inline uint8_t 327 cuda_read_reg(struct cuda_softc *sc, int offset) 328 { 329 330 return bus_space_read_1(sc->sc_memt, sc->sc_memh, offset); 331 } 332 333 static int 334 cuda_set_handler(void *cookie, int type, 335 int (*handler)(void *, int, uint8_t *), void *hcookie) 336 { 337 struct cuda_softc *sc = cookie; 338 CudaHandler *me; 339 340 if ((type >= 0) && (type < 16)) { 341 me = &sc->sc_handlers[type]; 342 me->handler = handler; 343 me->cookie = hcookie; 344 return 0; 345 } 346 return -1; 347 } 348 349 static int 350 cuda_send(void *cookie, int poll, int length, uint8_t *msg) 351 { 352 struct cuda_softc *sc = cookie; 353 int s; 354 355 DPRINTF("cuda_send %08x\n", (uint32_t)cookie); 356 if (sc->sc_state == CUDA_NOTREADY) 357 return -1; 358 359 s = splhigh(); 360 361 if (sc->sc_state == CUDA_IDLE /*&& 362 (cuda_read_reg(sc, vBufB) & vPB3) == vPB3*/) { 363 /* fine */ 364 DPRINTF("chip is idle\n"); 365 } else { 366 DPRINTF("cuda state is %d\n", sc->sc_state); 367 if (sc->sc_waiting == 0) { 368 sc->sc_waiting = 1; 369 } else { 370 splx(s); 371 return -1; 372 } 373 } 374 375 sc->sc_error = 0; 376 memcpy(sc->sc_out, msg, length); 377 sc->sc_out_length = length; 378 sc->sc_sent = 0; 379 380 if (sc->sc_waiting != 1) { 381 382 delay(150); 383 sc->sc_state = CUDA_OUT; 384 cuda_out(sc); 385 cuda_write_reg(sc, vSR, sc->sc_out[0]); 386 cuda_ack_off(sc); 387 cuda_tip(sc); 388 } 389 sc->sc_waiting = 1; 390 391 if (sc->sc_polling || poll || cold) { 392 cuda_poll(sc); 393 } 394 395 splx(s); 396 397 return 0; 398 } 399 400 static void 401 cuda_poll(void *cookie) 402 { 403 struct cuda_softc *sc = cookie; 404 int s; 405 406 DPRINTF("polling\n"); 407 while ((sc->sc_state != CUDA_IDLE) || 408 (cuda_intr_state(sc)) || 409 (sc->sc_waiting == 1)) { 410 if ((cuda_read_reg(sc, vIFR) & vSR_INT) == vSR_INT) { 411 s = splhigh(); 412 cuda_intr(sc); 413 splx(s); 414 } 415 } 416 } 417 418 static void 419 cuda_adb_poll(void *cookie) 420 { 421 struct cuda_softc *sc = cookie; 422 int s; 423 424 s = splhigh(); 425 cuda_intr(sc); 426 splx(s); 427 } 428 429 static void 430 cuda_idle(struct cuda_softc *sc) 431 { 432 uint8_t reg; 433 434 reg = cuda_read_reg(sc, vBufB); 435 reg |= (vPB4 | vPB5); 436 cuda_write_reg(sc, vBufB, reg); 437 } 438 439 static void 440 cuda_tip(struct cuda_softc *sc) 441 { 442 uint8_t reg; 443 444 reg = cuda_read_reg(sc, vBufB); 445 reg &= ~vPB5; 446 cuda_write_reg(sc, vBufB, reg); 447 } 448 449 static void 450 cuda_clear_tip(struct cuda_softc *sc) 451 { 452 uint8_t reg; 453 454 reg = cuda_read_reg(sc, vBufB); 455 reg |= vPB5; 456 cuda_write_reg(sc, vBufB, reg); 457 } 458 459 static void 460 cuda_in(struct cuda_softc *sc) 461 { 462 uint8_t reg; 463 464 reg = cuda_read_reg(sc, vACR); 465 reg &= ~vSR_OUT; 466 cuda_write_reg(sc, vACR, reg); 467 } 468 469 static void 470 cuda_out(struct cuda_softc *sc) 471 { 472 uint8_t reg; 473 474 reg = cuda_read_reg(sc, vACR); 475 reg |= vSR_OUT; 476 cuda_write_reg(sc, vACR, reg); 477 } 478 479 static void 480 cuda_toggle_ack(struct cuda_softc *sc) 481 { 482 uint8_t reg; 483 484 reg = cuda_read_reg(sc, vBufB); 485 reg ^= vPB4; 486 cuda_write_reg(sc, vBufB, reg); 487 } 488 489 static void 490 cuda_ack_off(struct cuda_softc *sc) 491 { 492 uint8_t reg; 493 494 reg = cuda_read_reg(sc, vBufB); 495 reg |= vPB4; 496 cuda_write_reg(sc, vBufB, reg); 497 } 498 499 static int 500 cuda_intr_state(struct cuda_softc *sc) 501 { 502 return ((cuda_read_reg(sc, vBufB) & vPB3) == 0); 503 } 504 505 static int 506 cuda_intr(void *arg) 507 { 508 struct cuda_softc *sc = arg; 509 int ending, type; 510 uint8_t reg; 511 512 reg = cuda_read_reg(sc, vIFR); /* Read the interrupts */ 513 DPRINTF("["); 514 if ((reg & 0x80) == 0) { 515 DPRINTF("irq %02x]", reg); 516 return 0; /* No interrupts to process */ 517 } 518 DPRINTF(":"); 519 520 cuda_write_reg(sc, vIFR, 0x7f); /* Clear 'em */ 521 522 switch_start: 523 switch (sc->sc_state) { 524 case CUDA_IDLE: 525 /* 526 * This is an unexpected packet, so grab the first (dummy) 527 * byte, set up the proper vars, and tell the chip we are 528 * starting to receive the packet by setting the TIP bit. 529 */ 530 sc->sc_in[1] = cuda_read_reg(sc, vSR); 531 DPRINTF("start: %02x", sc->sc_in[1]); 532 if (cuda_intr_state(sc) == 0) { 533 /* must have been a fake start */ 534 DPRINTF(" ... fake start\n"); 535 if (sc->sc_waiting) { 536 /* start over */ 537 delay(150); 538 sc->sc_state = CUDA_OUT; 539 sc->sc_sent = 0; 540 cuda_out(sc); 541 cuda_write_reg(sc, vSR, sc->sc_out[1]); 542 cuda_ack_off(sc); 543 cuda_tip(sc); 544 } 545 break; 546 } 547 548 cuda_in(sc); 549 cuda_tip(sc); 550 551 sc->sc_received = 1; 552 sc->sc_state = CUDA_IN; 553 DPRINTF(" CUDA_IN"); 554 break; 555 556 case CUDA_IN: 557 sc->sc_in[sc->sc_received] = cuda_read_reg(sc, vSR); 558 DPRINTF(" %02x", sc->sc_in[sc->sc_received]); 559 ending = 0; 560 if (sc->sc_received > 255) { 561 /* bitch only once */ 562 if (sc->sc_received == 256) { 563 aprint_error_dev(sc->sc_dev, 564 "input overflow\n"); 565 ending = 1; 566 } 567 } else 568 sc->sc_received++; 569 if (sc->sc_received > 3) { 570 if ((sc->sc_in[3] == CMD_IIC) && 571 (sc->sc_received > (sc->sc_i2c_read_len + 4))) { 572 ending = 1; 573 } 574 } 575 576 /* intr off means this is the last byte (end of frame) */ 577 if (cuda_intr_state(sc) == 0) { 578 ending = 1; 579 DPRINTF(".\n"); 580 } else { 581 cuda_toggle_ack(sc); 582 } 583 584 if (ending == 1) { /* end of message? */ 585 586 sc->sc_in[0] = sc->sc_received - 1; 587 588 /* reset vars and signal the end of this frame */ 589 cuda_idle(sc); 590 591 /* check if we have a handler for this message */ 592 type = sc->sc_in[1]; 593 if ((type >= 0) && (type < 16)) { 594 CudaHandler *me = &sc->sc_handlers[type]; 595 596 if (me->handler != NULL) { 597 me->handler(me->cookie, 598 sc->sc_received - 1, &sc->sc_in[1]); 599 } else { 600 aprint_error_dev(sc->sc_dev, 601 "no handler for type %02x\n", type); 602 panic("barf"); 603 } 604 } 605 606 DPRINTF("CUDA_IDLE"); 607 sc->sc_state = CUDA_IDLE; 608 609 sc->sc_received = 0; 610 611 /* 612 * If there is something waiting to be sent out, 613 * set everything up and send the first byte. 614 */ 615 if (sc->sc_waiting == 1) { 616 617 DPRINTF("pending write\n"); 618 delay(1500); /* required */ 619 sc->sc_sent = 0; 620 sc->sc_state = CUDA_OUT; 621 622 /* 623 * If the interrupt is on, we were too slow 624 * and the chip has already started to send 625 * something to us, so back out of the write 626 * and start a read cycle. 627 */ 628 if (cuda_intr_state(sc)) { 629 cuda_in(sc); 630 cuda_idle(sc); 631 sc->sc_sent = 0; 632 sc->sc_state = CUDA_IDLE; 633 sc->sc_received = 0; 634 delay(150); 635 DPRINTF("too slow - incoming message\n"); 636 goto switch_start; 637 } 638 /* 639 * If we got here, it's ok to start sending 640 * so load the first byte and tell the chip 641 * we want to send. 642 */ 643 DPRINTF("sending "); 644 645 cuda_out(sc); 646 cuda_write_reg(sc, vSR, 647 sc->sc_out[sc->sc_sent]); 648 cuda_ack_off(sc); 649 cuda_tip(sc); 650 } 651 } 652 break; 653 654 case CUDA_OUT: 655 (void)cuda_read_reg(sc, vSR); /* reset SR-intr in IFR */ 656 657 sc->sc_sent++; 658 if (cuda_intr_state(sc)) { /* ADB intr low during write */ 659 660 DPRINTF("incoming msg during send\n"); 661 cuda_in(sc); /* make sure SR is set to IN */ 662 cuda_idle(sc); 663 sc->sc_sent = 0; /* must start all over */ 664 sc->sc_state = CUDA_IDLE; /* new state */ 665 sc->sc_received = 0; 666 sc->sc_waiting = 1; /* must retry when done with 667 * read */ 668 delay(150); 669 goto switch_start; /* process next state right 670 * now */ 671 break; 672 } 673 if (sc->sc_out_length == sc->sc_sent) { /* check for done */ 674 675 sc->sc_waiting = 0; /* done writing */ 676 sc->sc_state = CUDA_IDLE; /* signal bus is idle */ 677 cuda_in(sc); 678 cuda_idle(sc); 679 DPRINTF("done sending\n"); 680 } else { 681 /* send next byte */ 682 cuda_write_reg(sc, vSR, sc->sc_out[sc->sc_sent]); 683 DPRINTF("%02x", sc->sc_out[sc->sc_sent]); 684 cuda_toggle_ack(sc); /* signal byte ready to 685 * shift */ 686 } 687 break; 688 689 case CUDA_NOTREADY: 690 DPRINTF("adb: not yet initialized\n"); 691 break; 692 693 default: 694 DPRINTF("intr: unknown ADB state\n"); 695 break; 696 } 697 698 DPRINTF("]"); 699 return 1; 700 } 701 702 static int 703 cuda_error_handler(void *cookie, int len, uint8_t *data) 704 { 705 struct cuda_softc *sc = cookie; 706 707 /* 708 * something went wrong 709 * byte 3 seems to be the failed command 710 */ 711 sc->sc_error = 1; 712 wakeup(&sc->sc_todev); 713 return 0; 714 } 715 716 717 /* real time clock */ 718 719 static int 720 cuda_todr_handler(void *cookie, int len, uint8_t *data) 721 { 722 struct cuda_softc *sc = cookie; 723 724 #ifdef CUDA_DEBUG 725 int i; 726 printf("msg: %02x", data[0]); 727 for (i = 1; i < len; i++) { 728 printf(" %02x", data[i]); 729 } 730 printf("\n"); 731 #endif 732 733 switch(data[2]) { 734 case CMD_READ_RTC: 735 memcpy(&sc->sc_tod, &data[3], 4); 736 break; 737 case CMD_WRITE_RTC: 738 sc->sc_tod = 0xffffffff; 739 break; 740 case CMD_AUTOPOLL: 741 sc->sc_autopoll = 1; 742 break; 743 case CMD_IIC: 744 sc->sc_iic_done = len; 745 break; 746 } 747 wakeup(&sc->sc_todev); 748 return 0; 749 } 750 751 #define DIFF19041970 2082844800 752 753 static int 754 cuda_todr_get(todr_chip_handle_t tch, struct timeval *tvp) 755 { 756 struct cuda_softc *sc = tch->cookie; 757 int cnt = 0; 758 uint8_t cmd[] = { CUDA_PSEUDO, CMD_READ_RTC}; 759 760 sc->sc_tod = 0; 761 while (sc->sc_tod == 0) { 762 cuda_send(sc, 0, 2, cmd); 763 764 while ((sc->sc_tod == 0) && (cnt < 10)) { 765 tsleep(&sc->sc_todev, 0, "todr", 10); 766 cnt++; 767 } 768 769 if (sc->sc_tod == 0) { 770 aprint_error_dev(sc->sc_dev, 771 "unable to read a sane RTC value\n"); 772 return EIO; 773 } 774 if ((sc->sc_tod > 0xf0000000UL) || 775 (sc->sc_tod < DIFF19041970)) { 776 /* huh? try again */ 777 sc->sc_tod = 0; 778 aprint_verbose_dev(sc->sc_dev, 779 "got garbage reading RTC, trying again\n"); 780 } 781 } 782 783 tvp->tv_sec = sc->sc_tod - DIFF19041970; 784 DPRINTF("tod: %" PRIo64 "\n", tvp->tv_sec); 785 tvp->tv_usec = 0; 786 return 0; 787 } 788 789 static int 790 cuda_todr_set(todr_chip_handle_t tch, struct timeval *tvp) 791 { 792 struct cuda_softc *sc = tch->cookie; 793 uint32_t sec; 794 uint8_t cmd[] = {CUDA_PSEUDO, CMD_WRITE_RTC, 0, 0, 0, 0}; 795 796 sec = tvp->tv_sec + DIFF19041970; 797 memcpy(&cmd[2], &sec, 4); 798 sc->sc_tod = 0; 799 if (cuda_send(sc, 0, 6, cmd) == 0) { 800 while (sc->sc_tod == 0) { 801 tsleep(&sc->sc_todev, 0, "todr", 10); 802 } 803 return 0; 804 } 805 aprint_error_dev(sc->sc_dev, "%s failed\n", __func__); 806 return -1; 807 808 } 809 810 /* poweroff and reboot */ 811 812 void 813 cuda_poweroff(void) 814 { 815 struct cuda_softc *sc; 816 uint8_t cmd[] = {CUDA_PSEUDO, CMD_POWEROFF}; 817 818 if (cuda0 == NULL) 819 return; 820 sc = cuda0->cookie; 821 sc->sc_polling = 1; 822 cuda0->poll(sc); 823 if (cuda0->send(sc, 1, 2, cmd) == 0) 824 while (1); 825 } 826 827 void 828 cuda_restart(void) 829 { 830 struct cuda_softc *sc; 831 uint8_t cmd[] = {CUDA_PSEUDO, CMD_RESET}; 832 833 if (cuda0 == NULL) 834 return; 835 sc = cuda0->cookie; 836 sc->sc_polling = 1; 837 cuda0->poll(sc); 838 if (cuda0->send(sc, 1, 2, cmd) == 0) 839 while (1); 840 } 841 842 /* ADB message handling */ 843 844 static void 845 cuda_autopoll(void *cookie, int flag) 846 { 847 struct cuda_softc *sc = cookie; 848 uint8_t cmd[] = {CUDA_PSEUDO, CMD_AUTOPOLL, (flag != 0)}; 849 850 if (cmd[2] == sc->sc_autopoll) 851 return; 852 853 sc->sc_autopoll = -1; 854 cuda_send(sc, 0, 3, cmd); 855 while(sc->sc_autopoll == -1) { 856 if (sc->sc_polling || cold) { 857 cuda_poll(sc); 858 } else 859 tsleep(&sc->sc_todev, 0, "autopoll", 100); 860 } 861 } 862 863 static int 864 cuda_adb_handler(void *cookie, int len, uint8_t *data) 865 { 866 struct cuda_softc *sc = cookie; 867 868 if (sc->sc_adb_handler != NULL) { 869 sc->sc_adb_handler(sc->sc_adb_cookie, len - 1, 870 &data[1]); 871 return 0; 872 } 873 return -1; 874 } 875 876 static int 877 cuda_adb_send(void *cookie, int poll, int command, int len, uint8_t *data) 878 { 879 struct cuda_softc *sc = cookie; 880 int i, s = 0; 881 uint8_t packet[16]; 882 883 /* construct an ADB command packet and send it */ 884 packet[0] = CUDA_ADB; 885 packet[1] = command; 886 for (i = 0; i < len; i++) 887 packet[i + 2] = data[i]; 888 if (poll || cold) { 889 s = splhigh(); 890 cuda_poll(sc); 891 } 892 cuda_send(sc, poll, len + 2, packet); 893 if (poll || cold) { 894 cuda_poll(sc); 895 splx(s); 896 } 897 return 0; 898 } 899 900 static int 901 cuda_adb_set_handler(void *cookie, void (*handler)(void *, int, uint8_t *), 902 void *hcookie) 903 { 904 struct cuda_softc *sc = cookie; 905 906 /* register a callback for incoming ADB messages */ 907 sc->sc_adb_handler = handler; 908 sc->sc_adb_cookie = hcookie; 909 return 0; 910 } 911 912 /* i2c message handling */ 913 914 static int 915 cuda_i2c_acquire_bus(void *cookie, int flags) 916 { 917 struct cuda_softc *sc = cookie; 918 919 mutex_enter(&sc->sc_buslock); 920 return 0; 921 } 922 923 static void 924 cuda_i2c_release_bus(void *cookie, int flags) 925 { 926 struct cuda_softc *sc = cookie; 927 928 mutex_exit(&sc->sc_buslock); 929 } 930 931 static int 932 cuda_i2c_exec(void *cookie, i2c_op_t op, i2c_addr_t addr, const void *_send, 933 size_t send_len, void *_recv, size_t recv_len, int flags) 934 { 935 struct cuda_softc *sc = cookie; 936 const uint8_t *send = _send; 937 uint8_t *recv = _recv; 938 uint8_t command[16] = {CUDA_PSEUDO, CMD_IIC}; 939 940 DPRINTF("cuda_i2c_exec(%02x)\n", addr); 941 command[2] = addr; 942 943 /* Copy command and output data bytes, if any, to buffer */ 944 if (send_len > 0) 945 memcpy(&command[3], send, min((int)send_len, 12)); 946 else if (I2C_OP_READ_P(op) && (recv_len == 0)) { 947 /* 948 * If no data bytes in either direction, it's a "quick" 949 * i2c operation. We don't know how to do a quick_read 950 * since that requires us to set the low bit of the 951 * address byte after it has been left-shifted. 952 */ 953 sc->sc_error = 0; 954 return -1; 955 } 956 957 sc->sc_iic_done = 0; 958 cuda_send(sc, sc->sc_polling, send_len + 3, command); 959 960 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 961 if (sc->sc_polling || cold) { 962 cuda_poll(sc); 963 } else 964 tsleep(&sc->sc_todev, 0, "i2c", 1000); 965 } 966 967 if (sc->sc_error) { 968 sc->sc_error = 0; 969 aprint_error_dev(sc->sc_dev, "error doing I2C\n"); 970 return -1; 971 } 972 973 /* see if we're supposed to do a read */ 974 if (recv_len > 0) { 975 sc->sc_iic_done = 0; 976 command[2] |= 1; 977 command[3] = 0; 978 979 /* 980 * XXX we need to do something to limit the size of the answer 981 * - apparently the chip keeps sending until we tell it to stop 982 */ 983 sc->sc_i2c_read_len = recv_len; 984 DPRINTF("rcv_len: %d\n", recv_len); 985 cuda_send(sc, sc->sc_polling, 3, command); 986 while ((sc->sc_iic_done == 0) && (sc->sc_error == 0)) { 987 if (sc->sc_polling || cold) { 988 cuda_poll(sc); 989 } else 990 tsleep(&sc->sc_todev, 0, "i2c", 1000); 991 } 992 993 if (sc->sc_error) { 994 aprint_error_dev(sc->sc_dev, 995 "error trying to read from I2C\n"); 996 sc->sc_error = 0; 997 return -1; 998 } 999 } 1000 1001 DPRINTF("received: %d\n", sc->sc_iic_done); 1002 if ((sc->sc_iic_done > 3) && (recv_len > 0)) { 1003 int rlen; 1004 1005 /* we got an answer */ 1006 rlen = min(sc->sc_iic_done - 3, recv_len); 1007 memcpy(recv, &sc->sc_in[4], rlen); 1008 #ifdef CUDA_DEBUG 1009 { 1010 int i; 1011 printf("ret:"); 1012 for (i = 0; i < rlen; i++) 1013 printf(" %02x", recv[i]); 1014 printf("\n"); 1015 } 1016 #endif 1017 return rlen; 1018 } 1019 return 0; 1020 } 1021