1 /* $NetBSD: if_mc_obio.c,v 1.11 2003/04/02 00:44:27 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym@bga.com> 5 * All rights reserved. 6 * 7 * Portions of this code are based on code by Denton Gentry <denny1@home.com> 8 * and Yanagisawa Takeshi <yanagisw@aa.ap.titech.ac.jp>. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 */ 30 31 /* 32 * Bus attachment and DMA routines for the mc driver (Centris/Quadra 33 * 660av and Quadra 840av onboard ethernet, based on the AMD Am79C940 34 * MACE ethernet chip). Also uses the PSC (Peripheral Subsystem 35 * Controller) for DMA to and from the MACE. 36 */ 37 38 #include "opt_ddb.h" 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/socket.h> 44 #include <sys/systm.h> 45 46 #include <net/if.h> 47 #include <net/if_ether.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <machine/bus.h> 52 #include <machine/psc.h> 53 54 #include <mac68k/obio/obiovar.h> 55 #include <mac68k/dev/if_mcreg.h> 56 #include <mac68k/dev/if_mcvar.h> 57 58 #define MACE_REG_BASE 0x50F1C000 59 #define MACE_PROM_BASE 0x50F08000 60 61 hide int mc_obio_match __P((struct device *, struct cfdata *, void *)); 62 hide void mc_obio_attach __P((struct device *, struct device *, void *)); 63 hide void mc_obio_init __P((struct mc_softc *sc)); 64 hide void mc_obio_put __P((struct mc_softc *sc, u_int len)); 65 hide int mc_dmaintr __P((void *arg)); 66 hide void mc_reset_rxdma __P((struct mc_softc *sc)); 67 hide void mc_reset_rxdma_set __P((struct mc_softc *, int set)); 68 hide void mc_reset_txdma __P((struct mc_softc *sc)); 69 hide int mc_obio_getaddr __P((struct mc_softc *, u_int8_t *)); 70 71 CFATTACH_DECL(mc_obio, sizeof(struct mc_softc), 72 mc_obio_match, mc_obio_attach, NULL, NULL); 73 74 hide int 75 mc_obio_match(parent, cf, aux) 76 struct device *parent; 77 struct cfdata *cf; 78 void *aux; 79 { 80 struct obio_attach_args *oa = aux; 81 bus_space_handle_t bsh; 82 int found = 0; 83 84 if (current_mac_model->class != MACH_CLASSAV) 85 return 0; 86 87 if (bus_space_map(oa->oa_tag, MACE_REG_BASE, MC_REGSIZE, 0, &bsh)) 88 return 0; 89 90 /* 91 * Make sure the MACE's I/O space is readable, and if it is, 92 * try to read the CHIPID register. A MACE will always have 93 * 0x?940, where the ? depends on the chip version. 94 */ 95 if (mac68k_bus_space_probe(oa->oa_tag, bsh, 0, 1)) { 96 if ((bus_space_read_1( 97 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDL)) == 0x40) && 98 ((bus_space_read_1( 99 oa->oa_tag, bsh, MACE_REG(MACE_CHIPIDH)) & 0xf) == 9)) 100 found = 1; 101 } 102 103 bus_space_unmap(oa->oa_tag, bsh, MC_REGSIZE); 104 105 return found; 106 } 107 108 hide void 109 mc_obio_attach(parent, self, aux) 110 struct device *parent, *self; 111 void *aux; 112 { 113 struct obio_attach_args *oa = (struct obio_attach_args *)aux; 114 struct mc_softc *sc = (void *)self; 115 u_int8_t myaddr[ETHER_ADDR_LEN]; 116 int i, noncontig = 0; 117 118 sc->sc_regt = oa->oa_tag; 119 sc->sc_biucc = XMTSP_64; 120 sc->sc_fifocc = XMTFW_16 | RCVFW_64 | XMTFWU | RCVFWU | 121 XMTBRST | RCVBRST; 122 sc->sc_plscc = PORTSEL_AUI; 123 124 if (bus_space_map(sc->sc_regt, MACE_REG_BASE, MC_REGSIZE, 0, 125 &sc->sc_regh)) { 126 printf(": failed to map space for MACE regs.\n"); 127 return; 128 } 129 130 if (mc_obio_getaddr(sc, myaddr)) { 131 printf(": failed to get MAC address.\n"); 132 return; 133 } 134 135 /* allocate memory for transmit buffer and mark it non-cacheable */ 136 sc->sc_txbuf = malloc(PAGE_SIZE, M_DEVBUF, M_WAITOK); 137 sc->sc_txbuf_phys = kvtop(sc->sc_txbuf); 138 physaccess (sc->sc_txbuf, (caddr_t)sc->sc_txbuf_phys, PAGE_SIZE, 139 PG_V | PG_RW | PG_CI); 140 141 /* 142 * allocate memory for receive buffer and mark it non-cacheable 143 * XXX This should use the bus_dma interface, since the buffer 144 * needs to be physically contiguous. However, it seems that 145 * at least on my system, malloc() does allocate contiguous 146 * memory. If it's not, suggest reducing the number of buffers 147 * to 2, which will fit in one 4K page. 148 */ 149 sc->sc_rxbuf = malloc(MC_NPAGES * PAGE_SIZE, M_DEVBUF, M_WAITOK); 150 sc->sc_rxbuf_phys = kvtop(sc->sc_rxbuf); 151 for (i = 0; i < MC_NPAGES; i++) { 152 int pa; 153 154 pa = kvtop(sc->sc_rxbuf + PAGE_SIZE*i); 155 physaccess (sc->sc_rxbuf + PAGE_SIZE*i, (caddr_t)pa, PAGE_SIZE, 156 PG_V | PG_RW | PG_CI); 157 if (pa != sc->sc_rxbuf_phys + PAGE_SIZE*i) 158 noncontig = 1; 159 } 160 161 if (noncontig) { 162 printf("%s: receive DMA buffer not contiguous! " 163 "Try compiling with \"options MC_RXDMABUFS=2\"\n", 164 sc->sc_dev.dv_xname); 165 return; 166 } 167 168 sc->sc_bus_init = mc_obio_init; 169 sc->sc_putpacket = mc_obio_put; 170 171 /* disable receive DMA */ 172 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 173 psc_reg2(PSC_ENETRD_CTL) = 0x1000; 174 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x1100; 175 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x1100; 176 177 /* disable transmit DMA */ 178 psc_reg2(PSC_ENETWR_CTL) = 0x8800; 179 psc_reg2(PSC_ENETWR_CTL) = 0x1000; 180 psc_reg2(PSC_ENETWR_CMD + PSC_SET0) = 0x1100; 181 psc_reg2(PSC_ENETWR_CMD + PSC_SET1) = 0x1100; 182 183 /* install interrupt handlers */ 184 add_psc_lev4_intr(PSCINTR_ENET_DMA, mc_dmaintr, sc); 185 add_psc_lev3_intr(mcintr, sc); 186 187 /* enable MACE DMA interrupts */ 188 psc_reg1(PSC_LEV4_IER) = 0x80 | (1 << PSCINTR_ENET_DMA); 189 190 /* don't know what this does */ 191 psc_reg2(PSC_ENETWR_CTL) = 0x9000; 192 psc_reg2(PSC_ENETRD_CTL) = 0x9000; 193 psc_reg2(PSC_ENETWR_CTL) = 0x0400; 194 psc_reg2(PSC_ENETRD_CTL) = 0x0400; 195 196 /* enable MACE interrupts */ 197 psc_reg1(PSC_LEV3_IER) = 0x80 | (1 << PSCINTR_ENET); 198 199 /* mcsetup returns 1 if something fails */ 200 if (mcsetup(sc, myaddr)) { 201 /* disable interrupts */ 202 psc_reg1(PSC_LEV4_IER) = (1 << PSCINTR_ENET_DMA); 203 psc_reg1(PSC_LEV3_IER) = (1 << PSCINTR_ENET); 204 /* remove interrupt handlers */ 205 remove_psc_lev4_intr(PSCINTR_ENET_DMA); 206 remove_psc_lev3_intr(); 207 208 bus_space_unmap(sc->sc_regt, sc->sc_regh, MC_REGSIZE); 209 return; 210 } 211 } 212 213 /* Bus-specific initialization */ 214 hide void 215 mc_obio_init(sc) 216 struct mc_softc *sc; 217 { 218 mc_reset_rxdma(sc); 219 mc_reset_txdma(sc); 220 } 221 222 hide void 223 mc_obio_put(sc, len) 224 struct mc_softc *sc; 225 u_int len; 226 { 227 psc_reg4(PSC_ENETWR_ADDR + sc->sc_txset) = sc->sc_txbuf_phys; 228 psc_reg4(PSC_ENETWR_LEN + sc->sc_txset) = len; 229 psc_reg2(PSC_ENETWR_CMD + sc->sc_txset) = 0x9800; 230 231 sc->sc_txset ^= 0x10; 232 } 233 234 /* 235 * Interrupt handler for the MACE DMA completion interrupts 236 */ 237 int 238 mc_dmaintr(arg) 239 void *arg; 240 { 241 struct mc_softc *sc = arg; 242 u_int16_t status; 243 u_int32_t bufsleft, which; 244 int head; 245 246 /* 247 * Not sure what this does... figure out if this interrupt is 248 * really ours? 249 */ 250 while ((which = psc_reg4(0x804)) != psc_reg4(0x804)) 251 ; 252 if ((which & 0x60000000) == 0) 253 return 0; 254 255 /* Get the read channel status */ 256 status = psc_reg2(PSC_ENETRD_CTL); 257 if (status & 0x2000) { 258 /* I think this is an exceptional condition. Reset the DMA */ 259 mc_reset_rxdma(sc); 260 #ifdef MCDEBUG 261 printf("%s: resetting receive DMA channel (status 0x%04x)\n", 262 sc->sc_dev.dv_xname, status); 263 #endif 264 } else if (status & 0x100) { 265 /* We've received some packets from the MACE */ 266 int offset; 267 268 /* Clear the interrupt */ 269 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x1100; 270 271 /* See how may receive buffers are left */ 272 bufsleft = psc_reg4(PSC_ENETRD_LEN + sc->sc_rxset); 273 head = MC_RXDMABUFS - bufsleft; 274 275 #if 0 /* I don't think this should ever happen */ 276 if (head == sc->sc_tail) { 277 #ifdef MCDEBUG 278 printf("%s: head == tail: suspending DMA?\n", 279 sc->sc_dev.dv_xname); 280 #endif 281 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9000; 282 } 283 #endif 284 285 /* Loop through, processing each of the packets */ 286 for (; sc->sc_tail < head; sc->sc_tail++) { 287 offset = sc->sc_tail * 0x800; 288 sc->sc_rxframe.rx_rcvcnt = sc->sc_rxbuf[offset]; 289 sc->sc_rxframe.rx_rcvsts = sc->sc_rxbuf[offset+2]; 290 sc->sc_rxframe.rx_rntpc = sc->sc_rxbuf[offset+4]; 291 sc->sc_rxframe.rx_rcvcc = sc->sc_rxbuf[offset+6]; 292 sc->sc_rxframe.rx_frame = sc->sc_rxbuf + offset + 16; 293 294 mc_rint(sc); 295 } 296 297 /* 298 * If we're out of buffers, reset this register set 299 * and switch to the other one. Otherwise, reactivate 300 * this set. 301 */ 302 if (bufsleft == 0) { 303 mc_reset_rxdma_set(sc, sc->sc_rxset); 304 sc->sc_rxset ^= 0x10; 305 } else 306 psc_reg2(PSC_ENETRD_CMD + sc->sc_rxset) = 0x9800; 307 } 308 309 /* Get the write channel status */ 310 status = psc_reg2(PSC_ENETWR_CTL); 311 if (status & 0x2000) { 312 /* I think this is an exceptional condition. Reset the DMA */ 313 mc_reset_txdma(sc); 314 #ifdef MCDEBUG 315 printf("%s: resetting transmit DMA channel (status 0x%04x)\n", 316 sc->sc_dev.dv_xname, status); 317 #endif 318 } else if (status & 0x100) { 319 /* Clear the interrupt and switch register sets */ 320 psc_reg2(PSC_ENETWR_CMD + sc->sc_txseti) = 0x100; 321 sc->sc_txseti ^= 0x10; 322 } 323 324 return 1; 325 } 326 327 328 hide void 329 mc_reset_rxdma(sc) 330 struct mc_softc *sc; 331 { 332 u_int8_t maccc; 333 334 /* Disable receiver, reset the DMA channels */ 335 maccc = NIC_GET(sc, MACE_MACCC); 336 NIC_PUT(sc, MACE_MACCC, maccc & ~ENRCV); 337 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 338 mc_reset_rxdma_set(sc, 0); 339 psc_reg2(PSC_ENETRD_CTL) = 0x400; 340 341 psc_reg2(PSC_ENETRD_CTL) = 0x8800; 342 mc_reset_rxdma_set(sc, 0x10); 343 psc_reg2(PSC_ENETRD_CTL) = 0x400; 344 345 /* Reenable receiver, reenable DMA */ 346 NIC_PUT(sc, MACE_MACCC, maccc); 347 sc->sc_rxset = 0; 348 349 psc_reg2(PSC_ENETRD_CMD + PSC_SET0) = 0x9800; 350 psc_reg2(PSC_ENETRD_CMD + PSC_SET1) = 0x9800; 351 } 352 353 hide void 354 mc_reset_rxdma_set(sc, set) 355 struct mc_softc *sc; 356 int set; 357 { 358 /* disable DMA while modifying the registers, then reenable DMA */ 359 psc_reg2(PSC_ENETRD_CMD + set) = 0x0100; 360 psc_reg4(PSC_ENETRD_ADDR + set) = sc->sc_rxbuf_phys; 361 psc_reg4(PSC_ENETRD_LEN + set) = MC_RXDMABUFS; 362 psc_reg2(PSC_ENETRD_CMD + set) = 0x9800; 363 sc->sc_tail = 0; 364 } 365 366 hide void 367 mc_reset_txdma(sc) 368 struct mc_softc *sc; 369 { 370 u_int8_t maccc; 371 372 psc_reg2(PSC_ENETWR_CTL) = 0x8800; 373 maccc = NIC_GET(sc, MACE_MACCC); 374 NIC_PUT(sc, MACE_MACCC, maccc & ~ENXMT); 375 sc->sc_txset = sc->sc_txseti = 0; 376 psc_reg2(PSC_ENETWR_CTL) = 0x400; 377 NIC_PUT(sc, MACE_MACCC, maccc); 378 } 379 380 hide int 381 mc_obio_getaddr(sc, lladdr) 382 struct mc_softc *sc; 383 u_int8_t *lladdr; 384 { 385 bus_space_handle_t bsh; 386 u_char csum; 387 388 if (bus_space_map(sc->sc_regt, MACE_PROM_BASE, 8*16, 0, &bsh)) { 389 printf(": failed to map space to read MACE address.\n%s", 390 sc->sc_dev.dv_xname); 391 return (-1); 392 } 393 394 if (!mac68k_bus_space_probe(sc->sc_regt, bsh, 0, 1)) { 395 bus_space_unmap(sc->sc_regt, bsh, 8*16); 396 return (-1); 397 } 398 399 csum = mc_get_enaddr(sc->sc_regt, bsh, 1, lladdr); 400 if (csum != 0xff) 401 printf(": ethernet PROM checksum failed (0x%x != 0xff)\n%s", 402 (int)csum, sc->sc_dev.dv_xname); 403 404 bus_space_unmap(sc->sc_regt, bsh, 8*16); 405 406 return (csum == 0xff ? 0 : -1); 407 } 408