1 /* $NetBSD: cpi_nubus.c,v 1.8 2014/03/16 05:20:25 dholland Exp $ */ 2 3 /*- 4 * Copyright (c) 2008 Hauke Fath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: cpi_nubus.c,v 1.8 2014/03/16 05:20:25 dholland Exp $"); 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/proc.h> 32 #include <sys/device.h> 33 #include <sys/malloc.h> 34 #include <sys/event.h> 35 #include <sys/callout.h> 36 #include <sys/conf.h> 37 #include <sys/file.h> 38 #include <sys/uio.h> 39 #include <sys/ioctl.h> 40 #include <sys/tty.h> 41 #include <sys/time.h> 42 #include <sys/timetc.h> 43 #include <sys/kernel.h> 44 #include <sys/syslog.h> 45 #include <sys/errno.h> 46 47 #include <machine/intr.h> 48 #include <machine/bus.h> 49 #include <machine/viareg.h> 50 51 #include <dev/ic/z8536reg.h> 52 #include <mac68k/nubus/nubus.h> 53 #include <mac68k/nubus/cpi_nubusvar.h> 54 55 #include "ioconf.h" 56 57 #ifdef DEBUG 58 #define CPI_DEBUG 59 #endif 60 61 /* 62 * Stuff taken from Egan/Teixeira ch 8: 'if(TRACE_FOO)' debug output 63 * statements don't break indentation, and when DEBUG is not defined, 64 * the compiler code optimizer drops them as dead code. 65 */ 66 #ifdef CPI_DEBUG 67 #define M_TRACE_CONFIG 0x0001 68 #define M_TRACE_OPEN 0x0002 69 #define M_TRACE_CLOSE 0x0004 70 #define M_TRACE_READ 0x0008 71 #define M_TRACE_WRITE 0x0010 72 #define M_TRACE_IOCTL 0x0020 73 #define M_TRACE_STATUS 0x0040 74 #define M_TRACE_TCNTR 0x0080 75 #define M_TRACE_ALL 0xFFFF 76 #define M_TRACE_NONE 0x0000 77 78 #define TRACE_CONFIG (cpi_debug_mask & M_TRACE_CONFIG) 79 #define TRACE_OPEN (cpi_debug_mask & M_TRACE_OPEN) 80 #define TRACE_CLOSE (cpi_debug_mask & M_TRACE_CLOSE) 81 #define TRACE_READ (cpi_debug_mask & M_TRACE_READ) 82 #define TRACE_WRITE (cpi_debug_mask & M_TRACE_WRITE) 83 #define TRACE_IOCTL (cpi_debug_mask & M_TRACE_IOCTL) 84 #define TRACE_STATUS (cpi_debug_mask & M_TRACE_STATUS) 85 #define TRACE_TCNTR (cpi_debug_mask & M_TRACE_TCNTR) 86 #define TRACE_ALL (cpi_debug_mask & M_TRACE_ALL) 87 #define TRACE_NONE (cpi_debug_mask & M_TRACE_NONE) 88 89 uint32_t cpi_debug_mask = M_TRACE_NONE /* | M_TRACE_TCNTR | M_TRACE_WRITE */ ; 90 #else /* CPI_DEBUG */ 91 #define TRACE_CONFIG 0 92 #define TRACE_OPEN 0 93 #define TRACE_CLOSE 0 94 #define TRACE_READ 0 95 #define TRACE_WRITE 0 96 #define TRACE_IOCTL 0 97 #define TRACE_STATUS 0 98 #define TRACE_TCNTR 0 99 #define TRACE_ALL 0 100 #define TRACE_NONE 0 101 #endif /* CPI_DEBUG */ 102 103 /* autoconf interface */ 104 int cpi_nubus_match(device_t, cfdata_t, void *); 105 void cpi_nubus_attach(device_t, device_t, void *); 106 void cpi_nubus_intr(void *); 107 108 CFATTACH_DECL_NEW(cpi, sizeof(struct cpi_softc), 109 cpi_nubus_match, cpi_nubus_attach, NULL, NULL); 110 111 dev_type_open(cpi_open); 112 dev_type_close(cpi_close); 113 dev_type_read(cpi_read); 114 dev_type_write(cpi_write); 115 dev_type_ioctl(cpi_ioctl); 116 117 const struct cdevsw cpi_cdevsw = { 118 .d_open = cpi_open, 119 .d_close = cpi_close, 120 .d_read = noread, 121 .d_write = cpi_write, 122 .d_ioctl = cpi_ioctl, 123 .d_stop = nostop, 124 .d_tty = notty, 125 .d_poll = nopoll, 126 .d_mmap = nommap, 127 .d_kqfilter = nokqfilter, 128 .d_flag = D_OTHER 129 }; 130 131 /* prototypes */ 132 static void cpi_lpreset(struct cpi_softc *); 133 static int cpi_notready(struct cpi_softc *); 134 static void cpi_wakeup(void *); 135 static int cpi_flush(struct cpi_softc *); 136 static void cpi_intr(void *); 137 138 static void cpi_tc_initclock(struct cpi_softc *); 139 static uint cpi_get_timecount(struct timecounter *); 140 static uint z8536_read_counter1(bus_space_tag_t, bus_space_handle_t); 141 static uint z8536_read_counter2(bus_space_tag_t, bus_space_handle_t); 142 static void z8536_reg_set(bus_space_tag_t, bus_space_handle_t, 143 uint8_t, uint8_t); 144 static uint8_t z8536_reg_get(bus_space_tag_t, bus_space_handle_t, 145 uint8_t); 146 147 148 const uint8_t cio_reset[] = { 149 /* register value */ 150 Z8536_MICR, 0x00, 151 Z8536_MICR, MICR_RESET, 152 Z8536_MICR, 0x00 153 }; 154 155 const uint8_t cio_init[] = { 156 /* register value */ 157 158 /* Interrupt vectors - clear all */ 159 Z8536_IVRA, 0x00, 160 Z8536_IVRB, 0x00, 161 Z8536_IVRCT, 0x20 /* ??? Do we use this? */, 162 163 /* 164 * Port A specification - bit port, single buffered, 165 * latched output, pulsed handshake, all bits non-inverting 166 * non-special I/O 167 */ 168 Z8536_PMSRA, PMSR_PTS_OUT | PMSR_LPM, 169 Z8536_PHSRA, PHSR_HTS_PUL, 170 Z8536_DPPRA, 0x00, 171 Z8536_DDRA, 0x00, 172 Z8536_SIOCRA, 0x00, 173 174 /* 175 * Port B specification - bit port, transparent output, 176 * pulsed handshake, all bits non-inverting 177 * bits 0, 4 output; bits 1-3, 5-8 input, 178 * non-special I/O 179 * Pattern matching: Bit 6 (BUSY) matching "1" 180 * Alternatively: Bit 3 (/ACK) matching "0" 181 */ 182 Z8536_PMSRB, PMSR_PMS_OR_PEV, 183 Z8536_PHSRB, 0x00, 184 Z8536_DPPRB, 0x00, 185 Z8536_DDRB, 0xee /*11101110b*/, 186 Z8536_SIOCRB, 0x00, 187 Z8536_PPRB, 0x00, 188 Z8536_PTRB, 0x00, 189 Z8536_PMRB, 0x40 /*01000000b = PB6 */, 190 191 Z8536_PDRB, 0xFE, /* Assign printer -RESET */ 192 Z8536_PCSRA, 0x00, /* Clear port A interrupt bits */ 193 194 /* 195 * Port C specification - bit 3 out, bits 0-2 in, 196 * all 4 non-inverting, non-special I/O 197 */ 198 Z8536_DDRC, 0x07 /*00000111b*/, 199 Z8536_DPPRC, 0x00, 200 Z8536_SIOCRC, 0x00, 201 202 /* 203 * We need Timer 3 for running port A in strobed mode. 204 * 205 * Counter/Timer 3 specification -- clear IP & IUS, trigger + 206 * gate command bit, one-shot operation 207 */ 208 Z8536_CTCSR3, CTCS_CLR_IP_IUS | CTCS_GCB | CTCS_TCB, 209 Z8536_CTMSR3, CTMS_DCS_ONESHOT, 210 Z8536_CTTCR3_MSB, 0x00, 211 Z8536_CTTCR3_LSB, 0x03, 212 213 /* Enable ports A+B+C+CT3 */ 214 Z8536_MCCR, MCCR_PAE | MCCR_PBE | MCCR_PC_CT3E, 215 216 /* Master Interrupt Enable, Disable Lower Chain, 217 * No Interrupt Vector, port A+B+CT vectors include status */ 218 Z8536_MICR, MICR_MIE | MICR_DLC | MICR_NV | MICR_PAVIS | 219 MICR_PBVIS | MICR_CTVIS, 220 Z8536_PDRB, 0xFE, /* Clear printer -RESET */ 221 }; 222 223 /* CPI default options */ 224 /* int cpi_options = 0 | CPI_CTC12_IS_TIMECOUNTER; */ 225 226 227 /* 228 * Look for Creative Systems Inc. "Hurdler Centronics Parallel Interface" 229 */ 230 int 231 cpi_nubus_match(device_t parent, cfdata_t cf, void *aux) 232 { 233 struct nubus_attach_args *na; 234 235 na = aux; 236 if ((na->category == NUBUS_CATEGORY_COMMUNICATIONS) && 237 (na->type == NUBUS_TYPE_CENTRONICS) && 238 (na->drsw == NUBUS_DRSW_CPI) && 239 (na->drhw == NUBUS_DRHW_CPI)) 240 return 1; 241 else 242 return 0; 243 } 244 245 void 246 cpi_nubus_attach(device_t parent, device_t self, void *aux) 247 { 248 struct cpi_softc *sc; 249 struct nubus_attach_args *na; 250 int err, ii; 251 252 sc = device_private(self); 253 sc->sc_options = (device_cfdata(self)->cf_flags & CPI_OPTIONS_MASK); 254 255 na = aux; 256 sc->sc_bst = na->na_tag; 257 memcpy(&sc->sc_slot, na->fmt, sizeof(nubus_slot)); 258 sc->sc_basepa = (bus_addr_t)NUBUS_SLOT2PA(na->slot); 259 260 /* 261 * The CIO sits eight bit wide on the top byte lane of 262 * Nubus, so map 16 byte. 263 */ 264 if (TRACE_CONFIG) { 265 printf("\n"); 266 printf("\tcpi_nubus_attach() mapping 8536 CIO at 0x%lx.\n", 267 sc->sc_basepa + CIO_BASE_OFFSET); 268 } 269 270 err = bus_space_map(sc->sc_bst, sc->sc_basepa + CIO_BASE_OFFSET, 271 (Z8536_IOSIZE << 4), 0, &sc->sc_bsh); 272 if (err) { 273 aprint_normal(": failed to map memory space.\n"); 274 return; 275 } 276 277 sc->sc_lpstate = LP_INITIAL; 278 sc->sc_intcount = 0; 279 sc->sc_bytestoport = 0; 280 281 if (TRACE_CONFIG) 282 printf("\tcpi_nubus_attach() about to set up 8536 CIO.\n"); 283 284 for (ii = 0; ii < sizeof(cio_reset); ii += 2) 285 z8536_reg_set(sc->sc_bst, sc->sc_bsh, cio_reset[ii], 286 cio_reset[ii + 1]); 287 288 delay(1000); /* Give the CIO time to set itself up */ 289 for (ii = 0; ii < sizeof(cio_init); ii += 2) { 290 z8536_reg_set(sc->sc_bst, sc->sc_bsh, cio_init[ii], 291 cio_init[ii + 1]); 292 } 293 294 if (TRACE_CONFIG) 295 printf("\tcpi_nubus_attach() done with 8536 CIO setup.\n"); 296 297 /* XXX Get information strings from the card ROM */ 298 aprint_normal(": CSI Hurdler II Centronics\n"); 299 300 /* Attach CIO timers 1+2 as timecounter */ 301 if (sc->sc_options & CPI_CTC12_IS_TIMECOUNTER) { 302 cpi_tc_initclock(sc); 303 } 304 305 callout_init(&sc->sc_wakeupchan, 0); /* XXX */ 306 307 /* make sure interrupts are vectored to us */ 308 add_nubus_intr(na->slot, cpi_nubus_intr, sc); 309 } 310 311 void 312 cpi_nubus_intr(void *arg) 313 { 314 struct cpi_softc *sc; 315 int s; 316 317 sc = (struct cpi_softc *)arg; 318 319 s = spltty(); 320 321 sc->sc_intcount++; 322 323 /* Check for interrupt source, and clear interrupt */ 324 325 /* 326 * Clear port A interrupt 327 * Interrupt from register A, clear "pending" 328 * and set "under service" 329 */ 330 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_CLR_IE); 331 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_CLR_IP); 332 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_SET_IUS); 333 334 cpi_intr(sc); 335 336 /* Interrupt from register A, mark serviced */ 337 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_CLR_IUS); 338 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_SET_IE); 339 340 splx(s); 341 } 342 343 344 /* cpi nuts and bolts */ 345 346 int 347 cpi_open(dev_t device, int flag, int mode, struct lwp *l) 348 { 349 int err, ii, s; 350 struct cpi_softc *sc; 351 352 if (TRACE_OPEN) 353 printf("\tcpi_open() called...\n"); 354 355 /* Consistency checks: Valid unit number, softc, device state */ 356 sc = device_lookup_private(&cpi_cd, CPI_UNIT(device)); 357 if (NULL == sc) { 358 if (TRACE_OPEN) 359 printf("Tried to cpi_open() with NULL softc\n"); 360 return ENXIO; 361 } 362 if (sc->sc_lpstate != LP_INITIAL) { 363 if (TRACE_OPEN) 364 printf("Not in initial state (%x).\n", 365 sc->sc_lpstate); 366 return EBUSY; 367 } 368 sc->sc_lpstate = LP_OPENING; 369 370 if (TRACE_OPEN) 371 printf("\tcpi_open() resetting the printer...\n"); 372 cpi_lpreset(sc); 373 374 if (TRACE_OPEN) 375 printf("\tcpi_open() waiting for printer ready...\n"); 376 377 /* Wait max 15 sec for printer to get ready */ 378 for (ii = 15; cpi_notready(sc); ii--) { 379 if (0 == ii) { 380 sc->sc_lpstate = LP_INITIAL; 381 return EBUSY; 382 } 383 /* sleep for a second, unless we get a signal */ 384 err = tsleep(sc, PZERO | PCATCH, "cpi_open", hz); 385 if (err != EWOULDBLOCK) { 386 sc->sc_lpstate = LP_INITIAL; 387 return err; 388 } 389 } 390 if (TRACE_OPEN) 391 printf("\tcpi_open() allocating printer buffer...\n"); 392 393 /* Allocate the driver's line buffer */ 394 sc->sc_printbuf = malloc(CPI_BUFSIZE, M_DEVBUF, M_WAITOK); 395 sc->sc_bufbytes = 0; 396 sc->sc_lpstate = LP_OPEN; 397 398 /* Statistics */ 399 sc->sc_intcount = 0; 400 sc->sc_bytestoport = 0; 401 402 /* Kick off transfer */ 403 cpi_wakeup(sc); 404 405 /* 406 * Reset "interrupt {pending, under service}" bits, then 407 * enable Port A interrupts 408 */ 409 s = spltty(); 410 411 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_CLR_IP_IUS); 412 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_SET_IE); 413 splx(s); 414 415 if (TRACE_OPEN) 416 printf("\tcpi_open() done...\n"); 417 418 return 0; 419 } 420 421 int 422 cpi_close(dev_t device, int flag, int mode, struct lwp *l) 423 { 424 struct cpi_softc *sc; 425 426 sc = device_lookup_private(&cpi_cd, CPI_UNIT(device)); 427 428 if (TRACE_CLOSE) 429 printf("\tcpi_close() called (%lu hard, %lu bytes to port)\n", 430 sc->sc_intcount, sc->sc_bytestoport); 431 432 /* Flush the remaining buffer content, ignoring any errors */ 433 if (0 < sc->sc_bufbytes) 434 (void)cpi_flush(sc); 435 436 callout_stop(&sc->sc_wakeupchan); 437 438 /* Disable Port A interrupts */ 439 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_CLR_IE); 440 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PCSRA, PCSR_CLR_IP_IUS); 441 442 sc->sc_lpstate = LP_INITIAL; 443 free(sc->sc_printbuf, M_DEVBUF); 444 445 return 0; 446 } 447 448 int 449 cpi_write(dev_t device, struct uio *uio, int flags) 450 { 451 int err; 452 size_t numbytes; 453 struct cpi_softc *sc; 454 455 err = 0; 456 457 if (TRACE_WRITE) 458 printf("\tcpi_write() called for %u bytes\n", uio->uio_resid); 459 460 sc = device_lookup_private(&cpi_cd, CPI_UNIT(device)); 461 462 /* Send data to printer, a line buffer full at a time */ 463 while (uio->uio_resid > 0) { 464 numbytes = min(CPI_BUFSIZE, uio->uio_resid); 465 sc->sc_cp = sc->sc_printbuf; 466 uiomove(sc->sc_cp, numbytes, uio); 467 sc->sc_bufbytes = numbytes; 468 469 if (TRACE_WRITE) 470 printf("\tQueuing %u bytes\n", numbytes); 471 err = cpi_flush(sc); 472 if (err) { 473 /* Failure; adjust residual counter */ 474 if (TRACE_WRITE) 475 printf("\tQueuing failed with %d\n", err); 476 uio->uio_resid += sc->sc_bufbytes; 477 sc->sc_bufbytes = 0; 478 break; 479 } 480 } 481 return err; 482 } 483 484 int 485 cpi_ioctl(dev_t device, unsigned long cmd, void *data, 486 int flag, struct lwp *l) 487 { 488 int err; 489 490 err = 0; 491 492 if (TRACE_IOCTL) 493 printf("\tcpi_ioctl() called with %ld...\n", cmd); 494 495 switch (cmd) { 496 default: 497 if (TRACE_IOCTL) 498 printf("\tcpi_ioctl() unknown ioctl %ld\n", cmd); 499 err = ENODEV; 500 break; 501 } 502 return err; 503 } 504 505 /* 506 * Flush the print buffer that our top half uses to provide data to 507 * our bottom, interrupt-driven half. 508 */ 509 static int 510 cpi_flush(struct cpi_softc *sc) 511 { 512 int err, s; 513 514 err = 0; 515 while (0 < sc->sc_bufbytes) { 516 /* Feed the printer a char, if it's ready */ 517 if ( !cpi_notready(sc)) { 518 if (TRACE_WRITE) 519 printf("\tcpi_flush() writes %u bytes " 520 "(%lu hard, %lu bytes to port)\n", 521 sc->sc_bufbytes, sc->sc_intcount, 522 sc->sc_bytestoport); 523 s = spltty(); 524 cpi_intr(sc); 525 splx(s); 526 } 527 /* XXX Sure we want to wait forever for the printer? */ 528 err = tsleep((void *)sc, PZERO | PCATCH, 529 "cpi_flush", (60 * hz)); 530 } 531 return err; 532 } 533 534 535 static void 536 cpi_wakeup(void *param) 537 { 538 struct cpi_softc *sc; 539 int s; 540 541 sc = param; 542 543 s = spltty(); 544 cpi_intr(sc); 545 splx(s); 546 547 callout_reset(&sc->sc_wakeupchan, hz, cpi_wakeup, sc); 548 } 549 550 551 static void 552 cpi_lpreset(struct cpi_softc *sc) 553 { 554 uint8_t portb; /* Centronics -RESET is on port B, bit 0 */ 555 556 portb = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_PDRB); 557 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PDRB, portb & ~CPI_RESET); 558 delay(100); 559 portb = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_PDRB); 560 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_PDRB, portb | CPI_RESET); 561 } 562 563 564 /* 565 * Centronics BUSY is on port B, bit 6 566 * SELECT is on Port B, bit 5 567 * /FAULT is on Port B, bit 1 568 * PAPER EMPTY is on Port C, bit 1 569 */ 570 static int 571 cpi_notready(struct cpi_softc *sc) 572 { 573 uint8_t portb, portc; 574 int is_busy, is_select, is_fault, is_paper_empty; 575 576 if (TRACE_STATUS) 577 printf("\tcpi_notready() checking printer status...\n"); 578 579 portb = bus_space_read_1(sc->sc_bst, sc->sc_bsh, CIO_PORTB); 580 if (TRACE_STATUS) 581 printf("\tPort B has 0x0%X\n", portb); 582 583 is_busy = CPI_BUSY & portb; 584 if (TRACE_STATUS) 585 printf("\t\tBUSY = %d\n", is_busy); 586 587 is_select = CPI_SELECT & portb; 588 if (TRACE_STATUS) 589 printf("\t\tSELECT = %d\n", is_select); 590 591 is_fault = CPI_FAULT & portb; 592 if (TRACE_STATUS) 593 printf("\t\t/FAULT = %d\n", is_fault); 594 595 portc = bus_space_read_1(sc->sc_bst, sc->sc_bsh, CIO_PORTC); 596 if (TRACE_STATUS) 597 printf("\tPort C has 0x0%X\n", portc); 598 599 is_paper_empty = CPI_PAPER_EMPTY & portc; 600 if (TRACE_STATUS) 601 printf("\t\tPAPER EMPTY = %d\n", is_paper_empty); 602 603 return (is_busy || !is_select || !is_fault || is_paper_empty); 604 } 605 606 static void 607 cpi_intr(void *arg) 608 { 609 struct cpi_softc *sc; 610 611 sc = arg; 612 613 /* Printer ready for output? */ 614 if (cpi_notready(sc)) 615 return; 616 617 if (0 && TRACE_WRITE) 618 printf("\tcpi_soft_intr() has %u bytes.\n", sc->sc_bufbytes); 619 620 /* Anything to print? */ 621 if (sc->sc_bufbytes) { 622 /* Data byte */ 623 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 624 CIO_PORTA, *sc->sc_cp++); 625 sc->sc_bufbytes--; 626 sc->sc_bytestoport++; 627 } 628 if (0 == sc->sc_bufbytes) 629 /* line buffer empty, wake up our top half */ 630 wakeup((void *)sc); 631 } 632 633 static void 634 cpi_tc_initclock(struct cpi_softc *sc) 635 { 636 uint8_t reg; 637 638 /* 639 * Set up c/t 1 and 2 as a single, free-running 32 bit counter 640 */ 641 642 /* Disable counters 1 and 2 */ 643 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_MCCR); 644 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_MCCR, 645 reg & ~(MCCR_CT1E | MCCR_CT2E)); 646 647 /* Make sure interrupt enable bits are cleared */ 648 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1, CTCS_CLR_IE); 649 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR2, CTCS_CLR_IE); 650 651 /* Initialise counter start values, and set to continuous cycle */ 652 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTMSR1, 653 CTMS_CSC | CTMS_DCS_PULSE); 654 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTTCR1_MSB, 0x00); 655 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTTCR1_LSB, 0x00); 656 657 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTMSR2, 658 CTMS_CSC | CTMS_DCS_PULSE); 659 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTTCR2_MSB, 0x00); 660 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTTCR2_LSB, 0x00); 661 662 /* Link counters 1 and 2 */ 663 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_MCCR); 664 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_MCCR, reg | MCCR_CT1CT2); 665 666 /* Enable and counter pair */ 667 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_MCCR); 668 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_MCCR, 669 reg | (MCCR_CT1E | MCCR_CT2E)); 670 671 /* Start c/t 1; c/t 2 gets started by c/t 1 pulse */ 672 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1); 673 z8536_reg_set(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1, 674 CTCSR_MASK(reg | CTCS_TCB | CTCS_GCB)); 675 676 if (TRACE_TCNTR) { 677 printf("Before tc_init():\n"); 678 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1); 679 printf("Counter 1 CTCSR setup bits are 0x%03x\n", reg); 680 printf("Counter 1 (LSW) is now 0x%05x\n", 681 z8536_read_counter1(sc->sc_bst, sc->sc_bsh)); 682 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR2); 683 printf("Counter 2 CTCSR setup bits are 0x%03x\n", reg); 684 printf("Counter 2 (MSW) is now 0x%05x\n", 685 z8536_read_counter2(sc->sc_bst, sc->sc_bsh)); 686 687 delay(1000); 688 } 689 690 sc->sc_timecounter.tc_get_timecount = cpi_get_timecount; 691 sc->sc_timecounter.tc_poll_pps = 0; 692 sc->sc_timecounter.tc_counter_mask = ~0u; 693 sc->sc_timecounter.tc_frequency = CPI_CLK_FREQ; 694 sc->sc_timecounter.tc_name = "Nubus CPI"; 695 sc->sc_timecounter.tc_quality = 1000; 696 /* 697 * Squirrel away the device's sc so we can talk 698 * to the CIO later 699 */ 700 sc->sc_timecounter.tc_priv = sc; 701 sc->sc_timecounter.tc_next = NULL; 702 703 tc_init(&(sc->sc_timecounter)); 704 705 if (TRACE_TCNTR) { 706 delay(1000); 707 708 printf("After tc_init():\n"); 709 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR1); 710 printf("Counter 1 CTCSR setup bits are 0x%03x\n", reg); 711 printf("Counter 1 (LSW) is now 0x%05x\n", 712 z8536_read_counter1(sc->sc_bst, sc->sc_bsh)); 713 reg = z8536_reg_get(sc->sc_bst, sc->sc_bsh, Z8536_CTCSR2); 714 printf("Counter 2 CTCSR setup bits are 0x%03x\n", reg); 715 printf("Counter 2 (MSW) is now 0x%05x\n", 716 z8536_read_counter2(sc->sc_bst, sc->sc_bsh)); 717 } 718 } 719 720 static u_int 721 cpi_get_timecount(struct timecounter *tc) 722 { 723 int s; 724 uint msw, msw2, lsw; 725 uint8_t reg; 726 bus_space_tag_t bst; 727 bus_space_handle_t bsh; 728 729 bst = ((struct cpi_softc *)tc->tc_priv)->sc_bst; 730 bsh = ((struct cpi_softc *)tc->tc_priv)->sc_bsh; 731 /* 732 * We run CIO counters 1 and 2 in an internally coupled mode, 733 * where the output of counter 1 (LSW) clocks counter 2 (MSW). 734 * The counters are buffered, and the buffers have to be 735 * locked before we can read out a consistent counter 736 * value. Reading the LSB releases the buffer lock. 737 * 738 * Unfortunately, there is no such mechanism between MSW and 739 * LSW of the coupled counter. To ensure a consistent 740 * read-out, we read the MSW, then the LSW, then re-read the 741 * MSW and compare with the old value. If we find that the MSW 742 * has just been incremented, we re-read the LSW. This avoids 743 * a race that could leave us with a new (just wrapped) LSW 744 * and an old MSW value. 745 * 746 * For simplicity, we roll the procedure into a loop - the 747 * rollover case is rare. 748 */ 749 do { 750 751 #define delay(a) 752 753 /* Guard HW timer access */ 754 s = splhigh(); 755 756 /* Lock counter 2 latch in preparation for read-out */ 757 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR2); 758 delay(1); 759 reg = bus_space_read_1(bst, bsh, CIO_CTRL); 760 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR2); 761 bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC)); 762 763 /* Read out counter 2 MSB,then LSB (releasing the latch) */ 764 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR2_MSB); 765 delay(1); 766 msw = bus_space_read_1(bst, bsh, CIO_CTRL) << 8; 767 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR2_LSB); 768 delay(1); 769 msw |= bus_space_read_1(bst, bsh, CIO_CTRL); 770 771 /* Lock counter 1 latch in preparation for read-out */ 772 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR1); 773 delay(1); 774 reg = bus_space_read_1(bst, bsh, CIO_CTRL); 775 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR1); 776 bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg |CTCS_RCC)); 777 778 /* Read out counter 1 MSB,then LSB (releasing the latch) */ 779 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR1_MSB); 780 delay(1); 781 lsw = bus_space_read_1(bst, bsh, CIO_CTRL) << 8; 782 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR1_LSB); 783 delay(1); 784 lsw |= bus_space_read_1(bst, bsh, CIO_CTRL); 785 786 /* Lock counter 2 latch in preparation for read-out */ 787 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR2); 788 delay(1); 789 reg = bus_space_read_1(bst, bsh, CIO_CTRL); 790 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR2); 791 bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC)); 792 793 /* Read out counter 2 MSB,then LSB (releasing the latch) */ 794 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR2_MSB); 795 delay(1); 796 msw2 = bus_space_read_1(bst, bsh, CIO_CTRL) << 8; 797 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR2_LSB); 798 delay(1); 799 msw2 |= bus_space_read_1(bst, bsh, CIO_CTRL); 800 801 splx(s); 802 803 } while (msw2 != msw); 804 805 /* timecounter expects an upward counter */ 806 return ~0u - ((msw << 16) | lsw); 807 } 808 809 /* 810 * Z8536 CIO convenience atomic register getter/setter 811 */ 812 813 static uint 814 z8536_read_counter1(bus_space_tag_t bst, bus_space_handle_t bsh) 815 { 816 uint8_t reg; 817 uint32_t lsw; 818 int s; 819 820 s = splhigh(); 821 822 /* Lock counter 1 latch in preparation for read-out */ 823 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR1); 824 delay(1); 825 reg = bus_space_read_1(bst, bsh, CIO_CTRL); 826 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR1); 827 bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC)); 828 829 /* Read out counter 1 MSB,then LSB (releasing the latch) */ 830 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR1_MSB); 831 delay(1); 832 lsw = bus_space_read_1(bst, bsh, CIO_CTRL) << 8; 833 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR1_LSB); 834 delay(1); 835 lsw |= bus_space_read_1(bst, bsh, CIO_CTRL); 836 837 splx(s); 838 839 return lsw; 840 } 841 842 static uint 843 z8536_read_counter2(bus_space_tag_t bst, bus_space_handle_t bsh) 844 { 845 uint8_t reg; 846 uint32_t msw; 847 int s; 848 849 s = splhigh(); 850 851 /* Lock counter 2 latch in preparation for read-out */ 852 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR2); 853 delay(1); 854 reg = bus_space_read_1(bst, bsh, CIO_CTRL); 855 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCSR2); 856 bus_space_write_1(bst, bsh, CIO_CTRL, CTCSR_MASK(reg | CTCS_RCC)); 857 858 /* Read out counter 2 MSB,then LSB (releasing the latch) */ 859 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR2_MSB); 860 delay(1); 861 msw = bus_space_read_1(bst, bsh, CIO_CTRL) << 8; 862 bus_space_write_1(bst, bsh, CIO_CTRL, Z8536_CTCCR2_LSB); 863 delay(1); 864 msw |= bus_space_read_1(bst, bsh, CIO_CTRL); 865 866 splx(s); 867 868 return msw; 869 } 870 871 static void 872 z8536_reg_set(bus_space_tag_t bspace, bus_space_handle_t bhandle, 873 uint8_t reg, uint8_t val) 874 { 875 int s; 876 877 s = splhigh(); 878 bus_space_write_1(bspace, bhandle, CIO_CTRL, reg); 879 delay(1); 880 bus_space_write_1(bspace, bhandle, CIO_CTRL, val); 881 splx(s); 882 } 883 884 static uint8_t 885 z8536_reg_get(bus_space_tag_t bspace, bus_space_handle_t bhandle, uint8_t reg) 886 { 887 int s; 888 uint8_t val; 889 890 s = splhigh(); 891 bus_space_write_1(bspace, bhandle, CIO_CTRL, reg); 892 delay(1); 893 val = bus_space_read_1(bspace, bhandle, CIO_CTRL); 894 splx(s); 895 896 return val; 897 } 898