xref: /netbsd-src/sys/arch/mac68k/include/intr.h (revision d0fed6c87ddc40a8bffa6f99e7433ddfc864dd83)
1 /*	$NetBSD: intr.h,v 1.2 1997/04/14 06:25:32 scottr Exp $	*/
2 
3 /*
4  * Copyright (C) 1997 Scott Reynolds
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *      This product includes software developed by Scott Reynolds for
18  *      the NetBSD Project.
19  * 4. The name of the author may not be used to endorse or promote products
20  *    derived from this software without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #ifndef _MAC68K_INTR_H_
35 #define _MAC68K_INTR_H_
36 
37 #ifdef _KERNEL
38 /*
39  * spl functions; all but spl0 are done in-line
40  */
41 
42 #define _spl(s)								\
43 ({									\
44         register int _spl_r;						\
45 									\
46         __asm __volatile ("clrl %0; movew sr,%0; movew %1,sr" :		\
47                 "&=d" (_spl_r) : "di" (s));				\
48         _spl_r;								\
49 })
50 
51 #define _splraise(s)							\
52 ({									\
53 	register int _spl_r;						\
54 									\
55 	__asm __volatile ("clrl %0; movew sr,%0;" : "&=d" (_spl_r) : );	\
56 	if ((_spl_r & PSL_IPL) < ((s) & PSL_IPL))			\
57 		__asm __volatile ("movew %0,sr;" : : "di" (s));		\
58 	_spl_r;								\
59 })
60 
61 /* spl0 requires checking for software interrupts */
62 #define spl1()  _spl(PSL_S|PSL_IPL1)
63 #define spl2()  _spl(PSL_S|PSL_IPL2)
64 #define spl3()  _spl(PSL_S|PSL_IPL3)
65 #define spl4()  _spl(PSL_S|PSL_IPL4)
66 #define spl5()  _spl(PSL_S|PSL_IPL5)
67 #define spl6()  _spl(PSL_S|PSL_IPL6)
68 #define spl7()  _spl(PSL_S|PSL_IPL7)
69 
70 /*
71  * These should be used for:
72  * 1) ensuring mutual exclusion (why use processor level?)
73  * 2) allowing faster devices to take priority
74  *
75  * Note that on the Mac, most things are masked at spl1, almost
76  * everything at spl2, and everything but the panic switch and
77  * power at spl4.
78  */
79 #define	splsoftclock()	spl1()	/* disallow softclock */
80 #define	splsoftnet()	spl1()	/* disallow network */
81 #define	spltty()	spl1()	/* disallow tty (softserial & ADB) */
82 #define	splbio()	spl2()	/* disallow block I/O */
83 #define	splnet()	spl2()	/* disallow network */
84 #define	splimp()	spl2()	/* mutual exclusion for memory allocation */
85 #define	splclock()	spl2()	/* disallow clock (and other) interrupts */
86 #define	splstatclock()	spl2()	/* ditto */
87 #define	splzs()		spl4()	/* disallow serial hw interrupts */
88 #define	spladb()	spl7()	/* disallow adb interrupts */
89 #define	splhigh()	spl7()	/* disallow everything */
90 #define	splsched()	spl7()	/* disallow scheduling */
91 
92 /* watch out for side effects */
93 #define splx(s)         ((s) & PSL_IPL ? _spl(s) : spl0())
94 
95 /*
96  * simulated software interrupt register
97  */
98 extern volatile u_int8_t ssir;
99 
100 #define	SIR_NET		0x01
101 #define	SIR_CLOCK	0x02
102 #define	SIR_SERIAL	0x04
103 
104 #define	siron(mask)	\
105 	__asm __volatile ( "orb %0,_ssir" : : "i" (mask))
106 #define	siroff(mask)	\
107 	__asm __volatile ( "andb %0,_ssir" : : "ir" (~(mask)));
108 
109 #define	setsoftnet()	siron(SIR_NET)
110 #define	setsoftclock()	siron(SIR_CLOCK)
111 #define	setsoftserial()	siron(SIR_SERIAL)
112 
113 /* locore.s */
114 int	spl0 __P((void));
115 #endif /* _KERNEL */
116 
117 #endif /* _MAC68K_INTR_H_ */
118